1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <config.h>
17
18 #include <dm/device.h>
19 #include <linux/compat.h>
20 #include <linux/mtd/mtd.h>
21 #include <linux/mtd/flashchip.h>
22 #include <linux/mtd/bbm.h>
23 #include <asm/cache.h>
24
25 struct mtd_info;
26 struct nand_chip;
27 struct nand_flash_dev;
28 struct device_node;
29
30 /* Get the flash and manufacturer id and lookup if the type is supported. */
31 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
32 struct nand_chip *chip,
33 int *maf_id, int *dev_id,
34 struct nand_flash_dev *type);
35
36 /* Scan and identify a NAND device */
37 int nand_scan(struct mtd_info *mtd, int max_chips);
38 /*
39 * Separate phases of nand_scan(), allowing board driver to intervene
40 * and override command or ECC setup according to flash type.
41 */
42 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
43 struct nand_flash_dev *table);
44 int nand_scan_tail(struct mtd_info *mtd);
45
46 /* Free resources held by the NAND device */
47 void nand_release(struct mtd_info *mtd);
48
49 /* Internal helper for board drivers which need to override command function */
50 void nand_wait_ready(struct mtd_info *mtd);
51
52 /*
53 * This constant declares the max. oobsize / page, which
54 * is supported now. If you add a chip with bigger oobsize/page
55 * adjust this accordingly.
56 */
57 #define NAND_MAX_OOBSIZE 1664
58 #define NAND_MAX_PAGESIZE 16384
59
60 /*
61 * Constants for hardware specific CLE/ALE/NCE function
62 *
63 * These are bits which can be or'ed to set/clear multiple
64 * bits in one go.
65 */
66 /* Select the chip by setting nCE to low */
67 #define NAND_NCE 0x01
68 /* Select the command latch by setting CLE to high */
69 #define NAND_CLE 0x02
70 /* Select the address latch by setting ALE to high */
71 #define NAND_ALE 0x04
72
73 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
74 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
75 #define NAND_CTRL_CHANGE 0x80
76
77 /*
78 * Standard NAND flash commands
79 */
80 #define NAND_CMD_READ0 0
81 #define NAND_CMD_READ1 1
82 #define NAND_CMD_RNDOUT 5
83 #define NAND_CMD_PAGEPROG 0x10
84 #define NAND_CMD_READOOB 0x50
85 #define NAND_CMD_ERASE1 0x60
86 #define NAND_CMD_STATUS 0x70
87 #define NAND_CMD_SEQIN 0x80
88 #define NAND_CMD_RNDIN 0x85
89 #define NAND_CMD_READID 0x90
90 #define NAND_CMD_ERASE2 0xd0
91 #define NAND_CMD_PARAM 0xec
92 #define NAND_CMD_GET_FEATURES 0xee
93 #define NAND_CMD_SET_FEATURES 0xef
94 #define NAND_CMD_RESET 0xff
95
96 #define NAND_CMD_LOCK 0x2a
97 #define NAND_CMD_UNLOCK1 0x23
98 #define NAND_CMD_UNLOCK2 0x24
99
100 /* Extended commands for large page devices */
101 #define NAND_CMD_READSTART 0x30
102 #define NAND_CMD_RNDOUTSTART 0xE0
103 #define NAND_CMD_CACHEDPROG 0x15
104
105 /* Extended commands for AG-AND device */
106 /*
107 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
108 * there is no way to distinguish that from NAND_CMD_READ0
109 * until the remaining sequence of commands has been completed
110 * so add a high order bit and mask it off in the command.
111 */
112 #define NAND_CMD_DEPLETE1 0x100
113 #define NAND_CMD_DEPLETE2 0x38
114 #define NAND_CMD_STATUS_MULTI 0x71
115 #define NAND_CMD_STATUS_ERROR 0x72
116 /* multi-bank error status (banks 0-3) */
117 #define NAND_CMD_STATUS_ERROR0 0x73
118 #define NAND_CMD_STATUS_ERROR1 0x74
119 #define NAND_CMD_STATUS_ERROR2 0x75
120 #define NAND_CMD_STATUS_ERROR3 0x76
121 #define NAND_CMD_STATUS_RESET 0x7f
122 #define NAND_CMD_STATUS_CLEAR 0xff
123
124 #define NAND_CMD_NONE -1
125
126 /* Status bits */
127 #define NAND_STATUS_FAIL 0x01
128 #define NAND_STATUS_FAIL_N1 0x02
129 #define NAND_STATUS_TRUE_READY 0x20
130 #define NAND_STATUS_READY 0x40
131 #define NAND_STATUS_WP 0x80
132
133 #define NAND_DATA_IFACE_CHECK_ONLY -1
134
135 /*
136 * Constants for ECC_MODES
137 */
138 typedef enum {
139 NAND_ECC_NONE,
140 NAND_ECC_SOFT,
141 NAND_ECC_HW,
142 NAND_ECC_HW_SYNDROME,
143 NAND_ECC_HW_OOB_FIRST,
144 NAND_ECC_SOFT_BCH,
145 } nand_ecc_modes_t;
146
147 enum nand_ecc_algo {
148 NAND_ECC_UNKNOWN,
149 NAND_ECC_HAMMING,
150 NAND_ECC_BCH,
151 };
152
153 /*
154 * Constants for Hardware ECC
155 */
156 /* Reset Hardware ECC for read */
157 #define NAND_ECC_READ 0
158 /* Reset Hardware ECC for write */
159 #define NAND_ECC_WRITE 1
160 /* Enable Hardware ECC before syndrome is read back from flash */
161 #define NAND_ECC_READSYN 2
162
163 /*
164 * Enable generic NAND 'page erased' check. This check is only done when
165 * ecc.correct() returns -EBADMSG.
166 * Set this flag if your implementation does not fix bitflips in erased
167 * pages and you want to rely on the default implementation.
168 */
169 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
170 #define NAND_ECC_MAXIMIZE BIT(1)
171 /*
172 * If your controller already sends the required NAND commands when
173 * reading or writing a page, then the framework is not supposed to
174 * send READ0 and SEQIN/PAGEPROG respectively.
175 */
176 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
177
178 /* Bit mask for flags passed to do_nand_read_ecc */
179 #define NAND_GET_DEVICE 0x80
180
181
182 /*
183 * Option constants for bizarre disfunctionality and real
184 * features.
185 */
186 /* Buswidth is 16 bit */
187 #define NAND_BUSWIDTH_16 0x00000002
188 /* Device supports partial programming without padding */
189 #define NAND_NO_PADDING 0x00000004
190 /* Chip has cache program function */
191 #define NAND_CACHEPRG 0x00000008
192 /* Chip has copy back function */
193 #define NAND_COPYBACK 0x00000010
194 /*
195 * Chip requires ready check on read (for auto-incremented sequential read).
196 * True only for small page devices; large page devices do not support
197 * autoincrement.
198 */
199 #define NAND_NEED_READRDY 0x00000100
200
201 /* Chip does not allow subpage writes */
202 #define NAND_NO_SUBPAGE_WRITE 0x00000200
203
204 /* Device is one of 'new' xD cards that expose fake nand command set */
205 #define NAND_BROKEN_XD 0x00000400
206
207 /* Device behaves just like nand, but is readonly */
208 #define NAND_ROM 0x00000800
209
210 /* Device supports subpage reads */
211 #define NAND_SUBPAGE_READ 0x00001000
212
213 /*
214 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
215 * patterns.
216 */
217 #define NAND_NEED_SCRAMBLING 0x00002000
218
219 /* Device needs 3rd row address cycle */
220 #define NAND_ROW_ADDR_3 0x00004000
221
222 /* Options valid for Samsung large page devices */
223 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
224
225 /* Macros to identify the above */
226 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
227 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
228 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
229
230 /* Non chip related options */
231 /* This option skips the bbt scan during initialization. */
232 #define NAND_SKIP_BBTSCAN 0x00010000
233 /*
234 * This option is defined if the board driver allocates its own buffers
235 * (e.g. because it needs them DMA-coherent).
236 */
237 #define NAND_OWN_BUFFERS 0x00020000
238 /* Chip may not exist, so silence any errors in scan */
239 #define NAND_SCAN_SILENT_NODEV 0x00040000
240 /*
241 * Autodetect nand buswidth with readid/onfi.
242 * This suppose the driver will configure the hardware in 8 bits mode
243 * when calling nand_scan_ident, and update its configuration
244 * before calling nand_scan_tail.
245 */
246 #define NAND_BUSWIDTH_AUTO 0x00080000
247 /*
248 * This option could be defined by controller drivers to protect against
249 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
250 */
251 #define NAND_USE_BOUNCE_BUFFER 0x00100000
252
253 /* Options set by nand scan */
254 /* bbt has already been read */
255 #define NAND_BBT_SCANNED 0x40000000
256 /* Nand scan has allocated controller struct */
257 #define NAND_CONTROLLER_ALLOC 0x80000000
258
259 /* Cell info constants */
260 #define NAND_CI_CHIPNR_MSK 0x03
261 #define NAND_CI_CELLTYPE_MSK 0x0C
262 #define NAND_CI_CELLTYPE_SHIFT 2
263
264 /* ONFI features */
265 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
266 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
267
268 /* ONFI timing mode, used in both asynchronous and synchronous mode */
269 #define ONFI_TIMING_MODE_0 (1 << 0)
270 #define ONFI_TIMING_MODE_1 (1 << 1)
271 #define ONFI_TIMING_MODE_2 (1 << 2)
272 #define ONFI_TIMING_MODE_3 (1 << 3)
273 #define ONFI_TIMING_MODE_4 (1 << 4)
274 #define ONFI_TIMING_MODE_5 (1 << 5)
275 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
276
277 /* ONFI feature address */
278 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
279
280 /* Vendor-specific feature address (Micron) */
281 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
282
283 /* ONFI subfeature parameters length */
284 #define ONFI_SUBFEATURE_PARAM_LEN 4
285
286 /* ONFI optional commands SET/GET FEATURES supported? */
287 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
288
289 struct nand_onfi_params {
290 /* rev info and features block */
291 /* 'O' 'N' 'F' 'I' */
292 u8 sig[4];
293 __le16 revision;
294 __le16 features;
295 __le16 opt_cmd;
296 u8 reserved0[2];
297 __le16 ext_param_page_length; /* since ONFI 2.1 */
298 u8 num_of_param_pages; /* since ONFI 2.1 */
299 u8 reserved1[17];
300
301 /* manufacturer information block */
302 char manufacturer[12];
303 char model[20];
304 u8 jedec_id;
305 __le16 date_code;
306 u8 reserved2[13];
307
308 /* memory organization block */
309 __le32 byte_per_page;
310 __le16 spare_bytes_per_page;
311 __le32 data_bytes_per_ppage;
312 __le16 spare_bytes_per_ppage;
313 __le32 pages_per_block;
314 __le32 blocks_per_lun;
315 u8 lun_count;
316 u8 addr_cycles;
317 u8 bits_per_cell;
318 __le16 bb_per_lun;
319 __le16 block_endurance;
320 u8 guaranteed_good_blocks;
321 __le16 guaranteed_block_endurance;
322 u8 programs_per_page;
323 u8 ppage_attr;
324 u8 ecc_bits;
325 u8 interleaved_bits;
326 u8 interleaved_ops;
327 u8 reserved3[13];
328
329 /* electrical parameter block */
330 u8 io_pin_capacitance_max;
331 __le16 async_timing_mode;
332 __le16 program_cache_timing_mode;
333 __le16 t_prog;
334 __le16 t_bers;
335 __le16 t_r;
336 __le16 t_ccs;
337 __le16 src_sync_timing_mode;
338 u8 src_ssync_features;
339 __le16 clk_pin_capacitance_typ;
340 __le16 io_pin_capacitance_typ;
341 __le16 input_pin_capacitance_typ;
342 u8 input_pin_capacitance_max;
343 u8 driver_strength_support;
344 __le16 t_int_r;
345 __le16 t_adl;
346 u8 reserved4[8];
347
348 /* vendor */
349 __le16 vendor_revision;
350 u8 vendor[88];
351
352 __le16 crc;
353 } __packed;
354
355 #define ONFI_CRC_BASE 0x4F4E
356
357 /* Extended ECC information Block Definition (since ONFI 2.1) */
358 struct onfi_ext_ecc_info {
359 u8 ecc_bits;
360 u8 codeword_size;
361 __le16 bb_per_lun;
362 __le16 block_endurance;
363 u8 reserved[2];
364 } __packed;
365
366 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
367 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
368 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
369 struct onfi_ext_section {
370 u8 type;
371 u8 length;
372 } __packed;
373
374 #define ONFI_EXT_SECTION_MAX 8
375
376 /* Extended Parameter Page Definition (since ONFI 2.1) */
377 struct onfi_ext_param_page {
378 __le16 crc;
379 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
380 u8 reserved0[10];
381 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
382
383 /*
384 * The actual size of the Extended Parameter Page is in
385 * @ext_param_page_length of nand_onfi_params{}.
386 * The following are the variable length sections.
387 * So we do not add any fields below. Please see the ONFI spec.
388 */
389 } __packed;
390
391 struct nand_onfi_vendor_micron {
392 u8 two_plane_read;
393 u8 read_cache;
394 u8 read_unique_id;
395 u8 dq_imped;
396 u8 dq_imped_num_settings;
397 u8 dq_imped_feat_addr;
398 u8 rb_pulldown_strength;
399 u8 rb_pulldown_strength_feat_addr;
400 u8 rb_pulldown_strength_num_settings;
401 u8 otp_mode;
402 u8 otp_page_start;
403 u8 otp_data_prot_addr;
404 u8 otp_num_pages;
405 u8 otp_feat_addr;
406 u8 read_retry_options;
407 u8 reserved[72];
408 u8 param_revision;
409 } __packed;
410
411 struct jedec_ecc_info {
412 u8 ecc_bits;
413 u8 codeword_size;
414 __le16 bb_per_lun;
415 __le16 block_endurance;
416 u8 reserved[2];
417 } __packed;
418
419 /* JEDEC features */
420 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
421
422 struct nand_jedec_params {
423 /* rev info and features block */
424 /* 'J' 'E' 'S' 'D' */
425 u8 sig[4];
426 __le16 revision;
427 __le16 features;
428 u8 opt_cmd[3];
429 __le16 sec_cmd;
430 u8 num_of_param_pages;
431 u8 reserved0[18];
432
433 /* manufacturer information block */
434 char manufacturer[12];
435 char model[20];
436 u8 jedec_id[6];
437 u8 reserved1[10];
438
439 /* memory organization block */
440 __le32 byte_per_page;
441 __le16 spare_bytes_per_page;
442 u8 reserved2[6];
443 __le32 pages_per_block;
444 __le32 blocks_per_lun;
445 u8 lun_count;
446 u8 addr_cycles;
447 u8 bits_per_cell;
448 u8 programs_per_page;
449 u8 multi_plane_addr;
450 u8 multi_plane_op_attr;
451 u8 reserved3[38];
452
453 /* electrical parameter block */
454 __le16 async_sdr_speed_grade;
455 __le16 toggle_ddr_speed_grade;
456 __le16 sync_ddr_speed_grade;
457 u8 async_sdr_features;
458 u8 toggle_ddr_features;
459 u8 sync_ddr_features;
460 __le16 t_prog;
461 __le16 t_bers;
462 __le16 t_r;
463 __le16 t_r_multi_plane;
464 __le16 t_ccs;
465 __le16 io_pin_capacitance_typ;
466 __le16 input_pin_capacitance_typ;
467 __le16 clk_pin_capacitance_typ;
468 u8 driver_strength_support;
469 __le16 t_adl;
470 u8 reserved4[36];
471
472 /* ECC and endurance block */
473 u8 guaranteed_good_blocks;
474 __le16 guaranteed_block_endurance;
475 struct jedec_ecc_info ecc_info[4];
476 u8 reserved5[29];
477
478 /* reserved */
479 u8 reserved6[148];
480
481 /* vendor */
482 __le16 vendor_rev_num;
483 u8 reserved7[88];
484
485 /* CRC for Parameter Page */
486 __le16 crc;
487 } __packed;
488
489 /**
490 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
491 * @lock: protection lock
492 * @active: the mtd device which holds the controller currently
493 * @wq: wait queue to sleep on if a NAND operation is in
494 * progress used instead of the per chip wait queue
495 * when a hw controller is available.
496 */
497 struct nand_hw_control {
498 spinlock_t lock;
499 struct nand_chip *active;
500 };
501
nand_hw_control_init(struct nand_hw_control * nfc)502 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
503 {
504 nfc->active = NULL;
505 spin_lock_init(&nfc->lock);
506 init_waitqueue_head(&nfc->wq);
507 }
508
509 /**
510 * struct nand_ecc_step_info - ECC step information of ECC engine
511 * @stepsize: data bytes per ECC step
512 * @strengths: array of supported strengths
513 * @nstrengths: number of supported strengths
514 */
515 struct nand_ecc_step_info {
516 int stepsize;
517 const int *strengths;
518 int nstrengths;
519 };
520
521 /**
522 * struct nand_ecc_caps - capability of ECC engine
523 * @stepinfos: array of ECC step information
524 * @nstepinfos: number of ECC step information
525 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
526 */
527 struct nand_ecc_caps {
528 const struct nand_ecc_step_info *stepinfos;
529 int nstepinfos;
530 int (*calc_ecc_bytes)(int step_size, int strength);
531 };
532
533 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
534 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
535 static const int __name##_strengths[] = { __VA_ARGS__ }; \
536 static const struct nand_ecc_step_info __name##_stepinfo = { \
537 .stepsize = __step, \
538 .strengths = __name##_strengths, \
539 .nstrengths = ARRAY_SIZE(__name##_strengths), \
540 }; \
541 static const struct nand_ecc_caps __name = { \
542 .stepinfos = &__name##_stepinfo, \
543 .nstepinfos = 1, \
544 .calc_ecc_bytes = __calc, \
545 }
546
547 /**
548 * struct nand_ecc_ctrl - Control structure for ECC
549 * @mode: ECC mode
550 * @algo: ECC algorithm
551 * @steps: number of ECC steps per page
552 * @size: data bytes per ECC step
553 * @bytes: ECC bytes per step
554 * @strength: max number of correctible bits per ECC step
555 * @total: total number of ECC bytes per page
556 * @prepad: padding information for syndrome based ECC generators
557 * @postpad: padding information for syndrome based ECC generators
558 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
559 * @layout: ECC layout control struct pointer
560 * @priv: pointer to private ECC control data
561 * @hwctl: function to control hardware ECC generator. Must only
562 * be provided if an hardware ECC is available
563 * @calculate: function for ECC calculation or readback from ECC hardware
564 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
565 * Should return a positive number representing the number of
566 * corrected bitflips, -EBADMSG if the number of bitflips exceed
567 * ECC strength, or any other error code if the error is not
568 * directly related to correction.
569 * If -EBADMSG is returned the input buffers should be left
570 * untouched.
571 * @read_page_raw: function to read a raw page without ECC. This function
572 * should hide the specific layout used by the ECC
573 * controller and always return contiguous in-band and
574 * out-of-band data even if they're not stored
575 * contiguously on the NAND chip (e.g.
576 * NAND_ECC_HW_SYNDROME interleaves in-band and
577 * out-of-band data).
578 * @write_page_raw: function to write a raw page without ECC. This function
579 * should hide the specific layout used by the ECC
580 * controller and consider the passed data as contiguous
581 * in-band and out-of-band data. ECC controller is
582 * responsible for doing the appropriate transformations
583 * to adapt to its specific layout (e.g.
584 * NAND_ECC_HW_SYNDROME interleaves in-band and
585 * out-of-band data).
586 * @read_page: function to read a page according to the ECC generator
587 * requirements; returns maximum number of bitflips corrected in
588 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
589 * @read_subpage: function to read parts of the page covered by ECC;
590 * returns same as read_page()
591 * @write_subpage: function to write parts of the page covered by ECC.
592 * @write_page: function to write a page according to the ECC generator
593 * requirements.
594 * @write_oob_raw: function to write chip OOB data without ECC
595 * @read_oob_raw: function to read chip OOB data without ECC
596 * @read_oob: function to read chip OOB data
597 * @write_oob: function to write chip OOB data
598 */
599 struct nand_ecc_ctrl {
600 nand_ecc_modes_t mode;
601 enum nand_ecc_algo algo;
602 int steps;
603 int size;
604 int bytes;
605 int total;
606 int strength;
607 int prepad;
608 int postpad;
609 unsigned int options;
610 struct nand_ecclayout *layout;
611 void *priv;
612 void (*hwctl)(struct mtd_info *mtd, int mode);
613 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
614 uint8_t *ecc_code);
615 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
616 uint8_t *calc_ecc);
617 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
618 uint8_t *buf, int oob_required, int page);
619 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
620 const uint8_t *buf, int oob_required, int page);
621 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
622 uint8_t *buf, int oob_required, int page);
623 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
624 uint32_t offs, uint32_t len, uint8_t *buf, int page);
625 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
626 uint32_t offset, uint32_t data_len,
627 const uint8_t *data_buf, int oob_required, int page);
628 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
629 const uint8_t *buf, int oob_required, int page);
630 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
631 int page);
632 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
633 int page);
634 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
635 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
636 int page);
637 };
638
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)639 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
640 {
641 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
642 }
643
644 /**
645 * struct nand_buffers - buffer structure for read/write
646 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
647 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
648 * @databuf: buffer pointer for data, size is (page size + oobsize).
649 *
650 * Do not change the order of buffers. databuf and oobrbuf must be in
651 * consecutive order.
652 */
653 struct nand_buffers {
654 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
655 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
656 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
657 ARCH_DMA_MINALIGN)];
658 };
659
660 /**
661 * struct nand_sdr_timings - SDR NAND chip timings
662 *
663 * This struct defines the timing requirements of a SDR NAND chip.
664 * These information can be found in every NAND datasheets and the timings
665 * meaning are described in the ONFI specifications:
666 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
667 * Parameters)
668 *
669 * All these timings are expressed in picoseconds.
670 *
671 * @tBERS_max: Block erase time
672 * @tCCS_min: Change column setup time
673 * @tPROG_max: Page program time
674 * @tR_max: Page read time
675 * @tALH_min: ALE hold time
676 * @tADL_min: ALE to data loading time
677 * @tALS_min: ALE setup time
678 * @tAR_min: ALE to RE# delay
679 * @tCEA_max: CE# access time
680 * @tCEH_min: CE# high hold time
681 * @tCH_min: CE# hold time
682 * @tCHZ_max: CE# high to output hi-Z
683 * @tCLH_min: CLE hold time
684 * @tCLR_min: CLE to RE# delay
685 * @tCLS_min: CLE setup time
686 * @tCOH_min: CE# high to output hold
687 * @tCS_min: CE# setup time
688 * @tDH_min: Data hold time
689 * @tDS_min: Data setup time
690 * @tFEAT_max: Busy time for Set Features and Get Features
691 * @tIR_min: Output hi-Z to RE# low
692 * @tITC_max: Interface and Timing Mode Change time
693 * @tRC_min: RE# cycle time
694 * @tREA_max: RE# access time
695 * @tREH_min: RE# high hold time
696 * @tRHOH_min: RE# high to output hold
697 * @tRHW_min: RE# high to WE# low
698 * @tRHZ_max: RE# high to output hi-Z
699 * @tRLOH_min: RE# low to output hold
700 * @tRP_min: RE# pulse width
701 * @tRR_min: Ready to RE# low (data only)
702 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
703 * rising edge of R/B#.
704 * @tWB_max: WE# high to SR[6] low
705 * @tWC_min: WE# cycle time
706 * @tWH_min: WE# high hold time
707 * @tWHR_min: WE# high to RE# low
708 * @tWP_min: WE# pulse width
709 * @tWW_min: WP# transition to WE# low
710 */
711 struct nand_sdr_timings {
712 u64 tBERS_max;
713 u32 tCCS_min;
714 u64 tPROG_max;
715 u64 tR_max;
716 u32 tALH_min;
717 u32 tADL_min;
718 u32 tALS_min;
719 u32 tAR_min;
720 u32 tCEA_max;
721 u32 tCEH_min;
722 u32 tCH_min;
723 u32 tCHZ_max;
724 u32 tCLH_min;
725 u32 tCLR_min;
726 u32 tCLS_min;
727 u32 tCOH_min;
728 u32 tCS_min;
729 u32 tDH_min;
730 u32 tDS_min;
731 u32 tFEAT_max;
732 u32 tIR_min;
733 u32 tITC_max;
734 u32 tRC_min;
735 u32 tREA_max;
736 u32 tREH_min;
737 u32 tRHOH_min;
738 u32 tRHW_min;
739 u32 tRHZ_max;
740 u32 tRLOH_min;
741 u32 tRP_min;
742 u32 tRR_min;
743 u64 tRST_max;
744 u32 tWB_max;
745 u32 tWC_min;
746 u32 tWH_min;
747 u32 tWHR_min;
748 u32 tWP_min;
749 u32 tWW_min;
750 };
751
752 /**
753 * enum nand_data_interface_type - NAND interface timing type
754 * @NAND_SDR_IFACE: Single Data Rate interface
755 */
756 enum nand_data_interface_type {
757 NAND_SDR_IFACE,
758 };
759
760 /**
761 * struct nand_data_interface - NAND interface timing
762 * @type: type of the timing
763 * @timings: The timing, type according to @type
764 */
765 struct nand_data_interface {
766 enum nand_data_interface_type type;
767 union {
768 struct nand_sdr_timings sdr;
769 } timings;
770 };
771
772 /**
773 * nand_get_sdr_timings - get SDR timing from data interface
774 * @conf: The data interface
775 */
776 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)777 nand_get_sdr_timings(const struct nand_data_interface *conf)
778 {
779 if (conf->type != NAND_SDR_IFACE)
780 return ERR_PTR(-EINVAL);
781
782 return &conf->timings.sdr;
783 }
784
785 /**
786 * struct nand_chip - NAND Private Flash Chip Data
787 * @mtd: MTD device registered to the MTD framework
788 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
789 * flash device
790 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
791 * flash device.
792 * @flash_node: [BOARDSPECIFIC] device node describing this instance
793 * @read_byte: [REPLACEABLE] read one byte from the chip
794 * @read_word: [REPLACEABLE] read one word from the chip
795 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
796 * low 8 I/O lines
797 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
798 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
799 * @select_chip: [REPLACEABLE] select chip nr
800 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
801 * @block_markbad: [REPLACEABLE] mark a block bad
802 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
803 * ALE/CLE/nCE. Also used to write command and address
804 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
805 * device ready/busy line. If set to NULL no access to
806 * ready/busy is available and the ready/busy information
807 * is read from the chip status register.
808 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
809 * commands to the chip.
810 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
811 * ready.
812 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
813 * setting the read-retry mode. Mostly needed for MLC NAND.
814 * @ecc: [BOARDSPECIFIC] ECC control structure
815 * @buffers: buffer structure for read/write
816 * @buf_align: minimum buffer alignment required by a platform
817 * @hwcontrol: platform-specific hardware control structure
818 * @erase: [REPLACEABLE] erase function
819 * @scan_bbt: [REPLACEABLE] function to scan bad block table
820 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
821 * data from array to read regs (tR).
822 * @state: [INTERN] the current state of the NAND device
823 * @oob_poi: "poison value buffer," used for laying out OOB data
824 * before writing
825 * @page_shift: [INTERN] number of address bits in a page (column
826 * address bits).
827 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
828 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
829 * @chip_shift: [INTERN] number of address bits in one chip
830 * @options: [BOARDSPECIFIC] various chip options. They can partly
831 * be set to inform nand_scan about special functionality.
832 * See the defines for further explanation.
833 * @bbt_options: [INTERN] bad block specific options. All options used
834 * here must come from bbm.h. By default, these options
835 * will be copied to the appropriate nand_bbt_descr's.
836 * @badblockpos: [INTERN] position of the bad block marker in the oob
837 * area.
838 * @badblockbits: [INTERN] minimum number of set bits in a good block's
839 * bad block marker position; i.e., BBM == 11110111b is
840 * not bad when badblockbits == 7
841 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
842 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
843 * Minimum amount of bit errors per @ecc_step_ds guaranteed
844 * to be correctable. If unknown, set to zero.
845 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
846 * also from the datasheet. It is the recommended ECC step
847 * size, if known; if unknown, set to zero.
848 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
849 * set to the actually used ONFI mode if the chip is
850 * ONFI compliant or deduced from the datasheet if
851 * the NAND chip is not ONFI compliant.
852 * @numchips: [INTERN] number of physical chips
853 * @chipsize: [INTERN] the size of one chip for multichip arrays
854 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
855 * @pagebuf: [INTERN] holds the pagenumber which is currently in
856 * data_buf.
857 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
858 * currently in data_buf.
859 * @subpagesize: [INTERN] holds the subpagesize
860 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
861 * non 0 if ONFI supported.
862 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
863 * non 0 if JEDEC supported.
864 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
865 * supported, 0 otherwise.
866 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
867 * supported, 0 otherwise.
868 * @read_retries: [INTERN] the number of read retry modes supported
869 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
870 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
871 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
872 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
873 * means the configuration should not be applied but
874 * only checked.
875 * @bbt: [INTERN] bad block table pointer
876 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
877 * lookup.
878 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
879 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
880 * bad block scan.
881 * @controller: [REPLACEABLE] a pointer to a hardware controller
882 * structure which is shared among multiple independent
883 * devices.
884 * @priv: [OPTIONAL] pointer to private chip data
885 * @write_page: [REPLACEABLE] High-level page write function
886 */
887
888 struct nand_chip {
889 struct mtd_info mtd;
890 void __iomem *IO_ADDR_R;
891 void __iomem *IO_ADDR_W;
892
893 int flash_node;
894
895 uint8_t (*read_byte)(struct mtd_info *mtd);
896 u16 (*read_word)(struct mtd_info *mtd);
897 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
898 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
899 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
900 void (*select_chip)(struct mtd_info *mtd, int chip);
901 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
902 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
903 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
904 int (*dev_ready)(struct mtd_info *mtd);
905 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
906 int page_addr);
907 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
908 int (*erase)(struct mtd_info *mtd, int page);
909 int (*scan_bbt)(struct mtd_info *mtd);
910 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
911 uint32_t offset, int data_len, const uint8_t *buf,
912 int oob_required, int page, int raw);
913 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
914 int feature_addr, uint8_t *subfeature_para);
915 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
916 int feature_addr, uint8_t *subfeature_para);
917 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
918 int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
919 const struct nand_data_interface *conf);
920
921
922 int chip_delay;
923 unsigned int options;
924 unsigned int bbt_options;
925
926 int page_shift;
927 int phys_erase_shift;
928 int bbt_erase_shift;
929 int chip_shift;
930 int numchips;
931 uint64_t chipsize;
932 int pagemask;
933 int pagebuf;
934 unsigned int pagebuf_bitflips;
935 int subpagesize;
936 uint8_t bits_per_cell;
937 uint16_t ecc_strength_ds;
938 uint16_t ecc_step_ds;
939 int onfi_timing_mode_default;
940 int badblockpos;
941 int badblockbits;
942
943 int onfi_version;
944 int jedec_version;
945 struct nand_onfi_params onfi_params;
946 struct nand_jedec_params jedec_params;
947
948 struct nand_data_interface *data_interface;
949
950 int read_retries;
951
952 flstate_t state;
953
954 uint8_t *oob_poi;
955 struct nand_hw_control *controller;
956 struct nand_ecclayout *ecclayout;
957
958 struct nand_ecc_ctrl ecc;
959 struct nand_buffers *buffers;
960 unsigned long buf_align;
961 struct nand_hw_control hwcontrol;
962
963 uint8_t *bbt;
964 struct nand_bbt_descr *bbt_td;
965 struct nand_bbt_descr *bbt_md;
966
967 struct nand_bbt_descr *badblock_pattern;
968
969 void *priv;
970 };
971
nand_set_flash_node(struct nand_chip * chip,ofnode node)972 static inline void nand_set_flash_node(struct nand_chip *chip,
973 ofnode node)
974 {
975 chip->flash_node = ofnode_to_offset(node);
976 }
977
nand_get_flash_node(struct nand_chip * chip)978 static inline ofnode nand_get_flash_node(struct nand_chip *chip)
979 {
980 return offset_to_ofnode(chip->flash_node);
981 }
982
mtd_to_nand(struct mtd_info * mtd)983 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
984 {
985 return container_of(mtd, struct nand_chip, mtd);
986 }
987
nand_to_mtd(struct nand_chip * chip)988 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
989 {
990 return &chip->mtd;
991 }
992
nand_get_controller_data(struct nand_chip * chip)993 static inline void *nand_get_controller_data(struct nand_chip *chip)
994 {
995 return chip->priv;
996 }
997
nand_set_controller_data(struct nand_chip * chip,void * priv)998 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
999 {
1000 chip->priv = priv;
1001 }
1002
1003 /*
1004 * NAND Flash Manufacturer ID Codes
1005 */
1006 #define NAND_MFR_TOSHIBA 0x98
1007 #define NAND_MFR_SAMSUNG 0xec
1008 #define NAND_MFR_FUJITSU 0x04
1009 #define NAND_MFR_NATIONAL 0x8f
1010 #define NAND_MFR_RENESAS 0x07
1011 #define NAND_MFR_STMICRO 0x20
1012 #define NAND_MFR_HYNIX 0xad
1013 #define NAND_MFR_MICRON 0x2c
1014 #define NAND_MFR_AMD 0x01
1015 #define NAND_MFR_MACRONIX 0xc2
1016 #define NAND_MFR_EON 0x92
1017 #define NAND_MFR_SANDISK 0x45
1018 #define NAND_MFR_INTEL 0x89
1019 #define NAND_MFR_ATO 0x9b
1020
1021 /* The maximum expected count of bytes in the NAND ID sequence */
1022 #define NAND_MAX_ID_LEN 8
1023
1024 /*
1025 * A helper for defining older NAND chips where the second ID byte fully
1026 * defined the chip, including the geometry (chip size, eraseblock size, page
1027 * size). All these chips have 512 bytes NAND page size.
1028 */
1029 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1030 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1031 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1032
1033 /*
1034 * A helper for defining newer chips which report their page size and
1035 * eraseblock size via the extended ID bytes.
1036 *
1037 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1038 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1039 * device ID now only represented a particular total chip size (and voltage,
1040 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1041 * using the same device ID.
1042 */
1043 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1044 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1045 .options = (opts) }
1046
1047 #define NAND_ECC_INFO(_strength, _step) \
1048 { .strength_ds = (_strength), .step_ds = (_step) }
1049 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1050 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1051
1052 /**
1053 * struct nand_flash_dev - NAND Flash Device ID Structure
1054 * @name: a human-readable name of the NAND chip
1055 * @dev_id: the device ID (the second byte of the full chip ID array)
1056 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1057 * memory address as @id[0])
1058 * @dev_id: device ID part of the full chip ID array (refers the same memory
1059 * address as @id[1])
1060 * @id: full device ID array
1061 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1062 * well as the eraseblock size) is determined from the extended NAND
1063 * chip ID array)
1064 * @chipsize: total chip size in MiB
1065 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1066 * @options: stores various chip bit options
1067 * @id_len: The valid length of the @id.
1068 * @oobsize: OOB size
1069 * @ecc: ECC correctability and step information from the datasheet.
1070 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1071 * @ecc_strength_ds in nand_chip{}.
1072 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1073 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1074 * For example, the "4bit ECC for each 512Byte" can be set with
1075 * NAND_ECC_INFO(4, 512).
1076 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1077 * reset. Should be deduced from timings described
1078 * in the datasheet.
1079 *
1080 */
1081 struct nand_flash_dev {
1082 char *name;
1083 union {
1084 struct {
1085 uint8_t mfr_id;
1086 uint8_t dev_id;
1087 };
1088 uint8_t id[NAND_MAX_ID_LEN];
1089 };
1090 unsigned int pagesize;
1091 unsigned int chipsize;
1092 unsigned int erasesize;
1093 unsigned int options;
1094 uint16_t id_len;
1095 uint16_t oobsize;
1096 struct {
1097 uint16_t strength_ds;
1098 uint16_t step_ds;
1099 } ecc;
1100 int onfi_timing_mode_default;
1101 };
1102
1103 /**
1104 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1105 * @name: Manufacturer name
1106 * @id: manufacturer ID code of device.
1107 */
1108 struct nand_manufacturers {
1109 int id;
1110 char *name;
1111 };
1112
1113 extern struct nand_flash_dev nand_flash_ids[];
1114 extern struct nand_manufacturers nand_manuf_ids[];
1115
1116 int nand_default_bbt(struct mtd_info *mtd);
1117 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1118 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1119 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1120 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1121 int allowbbt);
1122 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1123 size_t *retlen, uint8_t *buf);
1124
1125 /*
1126 * Constants for oob configuration
1127 */
1128 #define NAND_SMALL_BADBLOCK_POS 5
1129 #define NAND_LARGE_BADBLOCK_POS 0
1130
1131 /**
1132 * struct platform_nand_chip - chip level device structure
1133 * @nr_chips: max. number of chips to scan for
1134 * @chip_offset: chip number offset
1135 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1136 * @partitions: mtd partition list
1137 * @chip_delay: R/B delay value in us
1138 * @options: Option flags, e.g. 16bit buswidth
1139 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1140 * @part_probe_types: NULL-terminated array of probe types
1141 */
1142 struct platform_nand_chip {
1143 int nr_chips;
1144 int chip_offset;
1145 int nr_partitions;
1146 struct mtd_partition *partitions;
1147 int chip_delay;
1148 unsigned int options;
1149 unsigned int bbt_options;
1150 const char **part_probe_types;
1151 };
1152
1153 /* Keep gcc happy */
1154 struct platform_device;
1155
1156 /**
1157 * struct platform_nand_ctrl - controller level device structure
1158 * @probe: platform specific function to probe/setup hardware
1159 * @remove: platform specific function to remove/teardown hardware
1160 * @hwcontrol: platform specific hardware control structure
1161 * @dev_ready: platform specific function to read ready/busy pin
1162 * @select_chip: platform specific chip select function
1163 * @cmd_ctrl: platform specific function for controlling
1164 * ALE/CLE/nCE. Also used to write command and address
1165 * @write_buf: platform specific function for write buffer
1166 * @read_buf: platform specific function for read buffer
1167 * @read_byte: platform specific function to read one byte from chip
1168 * @priv: private data to transport driver specific settings
1169 *
1170 * All fields are optional and depend on the hardware driver requirements
1171 */
1172 struct platform_nand_ctrl {
1173 int (*probe)(struct platform_device *pdev);
1174 void (*remove)(struct platform_device *pdev);
1175 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1176 int (*dev_ready)(struct mtd_info *mtd);
1177 void (*select_chip)(struct mtd_info *mtd, int chip);
1178 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1179 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1180 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1181 unsigned char (*read_byte)(struct mtd_info *mtd);
1182 void *priv;
1183 };
1184
1185 /**
1186 * struct platform_nand_data - container structure for platform-specific data
1187 * @chip: chip level chip structure
1188 * @ctrl: controller level device structure
1189 */
1190 struct platform_nand_data {
1191 struct platform_nand_chip chip;
1192 struct platform_nand_ctrl ctrl;
1193 };
1194
1195 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1196 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1197 static inline int onfi_feature(struct nand_chip *chip)
1198 {
1199 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1200 }
1201
1202 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1203 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1204 {
1205 if (!chip->onfi_version)
1206 return ONFI_TIMING_MODE_UNKNOWN;
1207 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1208 }
1209
1210 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1211 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1212 {
1213 if (!chip->onfi_version)
1214 return ONFI_TIMING_MODE_UNKNOWN;
1215 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1216 }
1217 #else
onfi_feature(struct nand_chip * chip)1218 static inline int onfi_feature(struct nand_chip *chip)
1219 {
1220 return 0;
1221 }
1222
onfi_get_async_timing_mode(struct nand_chip * chip)1223 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1224 {
1225 return ONFI_TIMING_MODE_UNKNOWN;
1226 }
1227
onfi_get_sync_timing_mode(struct nand_chip * chip)1228 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1229 {
1230 return ONFI_TIMING_MODE_UNKNOWN;
1231 }
1232 #endif
1233
1234 int onfi_init_data_interface(struct nand_chip *chip,
1235 struct nand_data_interface *iface,
1236 enum nand_data_interface_type type,
1237 int timing_mode);
1238
1239 /*
1240 * Check if it is a SLC nand.
1241 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1242 * We do not distinguish the MLC and TLC now.
1243 */
nand_is_slc(struct nand_chip * chip)1244 static inline bool nand_is_slc(struct nand_chip *chip)
1245 {
1246 return chip->bits_per_cell == 1;
1247 }
1248
1249 /**
1250 * Check if the opcode's address should be sent only on the lower 8 bits
1251 * @command: opcode to check
1252 */
nand_opcode_8bits(unsigned int command)1253 static inline int nand_opcode_8bits(unsigned int command)
1254 {
1255 switch (command) {
1256 case NAND_CMD_READID:
1257 case NAND_CMD_PARAM:
1258 case NAND_CMD_GET_FEATURES:
1259 case NAND_CMD_SET_FEATURES:
1260 return 1;
1261 default:
1262 break;
1263 }
1264 return 0;
1265 }
1266
1267 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1268 static inline int jedec_feature(struct nand_chip *chip)
1269 {
1270 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1271 : 0;
1272 }
1273
1274 /* Standard NAND functions from nand_base.c */
1275 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1276 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1277 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1278 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1279 uint8_t nand_read_byte(struct mtd_info *mtd);
1280
1281 /* get timing characteristics from ONFI timing mode. */
1282 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1283 /* get data interface from ONFI timing mode 0, used after reset. */
1284 const struct nand_data_interface *nand_get_default_data_interface(void);
1285
1286 int nand_check_erased_ecc_chunk(void *data, int datalen,
1287 void *ecc, int ecclen,
1288 void *extraoob, int extraooblen,
1289 int threshold);
1290
1291 int nand_check_ecc_caps(struct nand_chip *chip,
1292 const struct nand_ecc_caps *caps, int oobavail);
1293
1294 int nand_match_ecc_req(struct nand_chip *chip,
1295 const struct nand_ecc_caps *caps, int oobavail);
1296
1297 int nand_maximize_ecc(struct nand_chip *chip,
1298 const struct nand_ecc_caps *caps, int oobavail);
1299
1300 /* Reset and initialize a NAND device */
1301 int nand_reset(struct nand_chip *chip, int chipnr);
1302
1303 /* NAND operation helpers */
1304 int nand_reset_op(struct nand_chip *chip);
1305 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1306 unsigned int len);
1307 int nand_status_op(struct nand_chip *chip, u8 *status);
1308 int nand_exit_status_op(struct nand_chip *chip);
1309 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1310 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1311 unsigned int offset_in_page, void *buf, unsigned int len);
1312 int nand_change_read_column_op(struct nand_chip *chip,
1313 unsigned int offset_in_page, void *buf,
1314 unsigned int len, bool force_8bit);
1315 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1316 unsigned int offset_in_page, void *buf, unsigned int len);
1317 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1318 unsigned int offset_in_page, const void *buf,
1319 unsigned int len);
1320 int nand_prog_page_end_op(struct nand_chip *chip);
1321 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1322 unsigned int offset_in_page, const void *buf,
1323 unsigned int len);
1324 int nand_change_write_column_op(struct nand_chip *chip,
1325 unsigned int offset_in_page, const void *buf,
1326 unsigned int len, bool force_8bit);
1327 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1328 bool force_8bit);
1329 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1330 unsigned int len, bool force_8bit);
1331
1332 #endif /* __LINUX_MTD_RAWNAND_H */
1333