1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* ZynqMP power management enums and defines */ 8 9 #ifndef PM_DEFS_H 10 #define PM_DEFS_H 11 12 /********************************************************************* 13 * Macro definitions 14 ********************************************************************/ 15 16 /* 17 * Version number is a 32bit value, like: 18 * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR 19 */ 20 #define PM_VERSION_MAJOR 1 21 #define PM_VERSION_MINOR 0 22 23 #define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR) 24 25 /* Capabilities for RAM */ 26 #define PM_CAP_ACCESS 0x1U 27 #define PM_CAP_CONTEXT 0x2U 28 29 #define MAX_LATENCY (~0U) 30 #define MAX_QOS 100U 31 32 /* State arguments of the self suspend */ 33 #define PM_STATE_CPU_IDLE 0x0U 34 #define PM_STATE_SUSPEND_TO_RAM 0xFU 35 36 /********************************************************************* 37 * Enum definitions 38 ********************************************************************/ 39 40 enum pm_api_id { 41 /* Miscellaneous API functions: */ 42 PM_GET_API_VERSION = 1, /* Do not change or move */ 43 PM_SET_CONFIGURATION, 44 PM_GET_NODE_STATUS, 45 PM_GET_OP_CHARACTERISTIC, 46 PM_REGISTER_NOTIFIER, 47 /* API for suspending of PUs: */ 48 PM_REQ_SUSPEND, 49 PM_SELF_SUSPEND, 50 PM_FORCE_POWERDOWN, 51 PM_ABORT_SUSPEND, 52 PM_REQ_WAKEUP, 53 PM_SET_WAKEUP_SOURCE, 54 PM_SYSTEM_SHUTDOWN, 55 /* API for managing PM slaves: */ 56 PM_REQ_NODE, 57 PM_RELEASE_NODE, 58 PM_SET_REQUIREMENT, 59 PM_SET_MAX_LATENCY, 60 /* Direct control API functions: */ 61 PM_RESET_ASSERT, 62 PM_RESET_GET_STATUS, 63 PM_MMIO_WRITE, 64 PM_MMIO_READ, 65 PM_INIT_FINALIZE, 66 PM_FPGA_LOAD, 67 PM_FPGA_GET_STATUS, 68 PM_GET_CHIPID, 69 PM_SECURE_RSA_AES, 70 PM_SECURE_SHA, 71 PM_SECURE_RSA, 72 PM_PINCTRL_REQUEST, 73 PM_PINCTRL_RELEASE, 74 PM_PINCTRL_GET_FUNCTION, 75 PM_PINCTRL_SET_FUNCTION, 76 PM_PINCTRL_CONFIG_PARAM_GET, 77 PM_PINCTRL_CONFIG_PARAM_SET, 78 PM_IOCTL, 79 /* API to query information from firmware */ 80 PM_QUERY_DATA, 81 /* Clock control API functions */ 82 PM_CLOCK_ENABLE, 83 PM_CLOCK_DISABLE, 84 PM_CLOCK_GETSTATE, 85 PM_CLOCK_SETDIVIDER, 86 PM_CLOCK_GETDIVIDER, 87 PM_CLOCK_SETRATE, 88 PM_CLOCK_GETRATE, 89 PM_CLOCK_SETPARENT, 90 PM_CLOCK_GETPARENT, 91 PM_SECURE_IMAGE, 92 /* FPGA PL Readback */ 93 PM_FPGA_READ, 94 PM_SECURE_AES, 95 /* PLL control API functions */ 96 PM_PLL_SET_PARAMETER, 97 PM_PLL_GET_PARAMETER, 98 PM_PLL_SET_MODE, 99 PM_PLL_GET_MODE, 100 PM_API_MAX 101 }; 102 103 enum pm_node_id { 104 NODE_UNKNOWN = 0, 105 NODE_APU, 106 NODE_APU_0, 107 NODE_APU_1, 108 NODE_APU_2, 109 NODE_APU_3, 110 NODE_RPU, 111 NODE_RPU_0, 112 NODE_RPU_1, 113 NODE_PLD, 114 NODE_FPD, 115 NODE_OCM_BANK_0, 116 NODE_OCM_BANK_1, 117 NODE_OCM_BANK_2, 118 NODE_OCM_BANK_3, 119 NODE_TCM_0_A, 120 NODE_TCM_0_B, 121 NODE_TCM_1_A, 122 NODE_TCM_1_B, 123 NODE_L2, 124 NODE_GPU_PP_0, 125 NODE_GPU_PP_1, 126 NODE_USB_0, 127 NODE_USB_1, 128 NODE_TTC_0, 129 NODE_TTC_1, 130 NODE_TTC_2, 131 NODE_TTC_3, 132 NODE_SATA, 133 NODE_ETH_0, 134 NODE_ETH_1, 135 NODE_ETH_2, 136 NODE_ETH_3, 137 NODE_UART_0, 138 NODE_UART_1, 139 NODE_SPI_0, 140 NODE_SPI_1, 141 NODE_I2C_0, 142 NODE_I2C_1, 143 NODE_SD_0, 144 NODE_SD_1, 145 NODE_DP, 146 NODE_GDMA, 147 NODE_ADMA, 148 NODE_NAND, 149 NODE_QSPI, 150 NODE_GPIO, 151 NODE_CAN_0, 152 NODE_CAN_1, 153 NODE_EXTERN, 154 NODE_APLL, 155 NODE_VPLL, 156 NODE_DPLL, 157 NODE_RPLL, 158 NODE_IOPLL, 159 NODE_DDR, 160 NODE_IPI_APU, 161 NODE_IPI_RPU_0, 162 NODE_GPU, 163 NODE_PCIE, 164 NODE_PCAP, 165 NODE_RTC, 166 NODE_LPD, 167 NODE_VCU, 168 NODE_IPI_RPU_1, 169 NODE_IPI_PL_0, 170 NODE_IPI_PL_1, 171 NODE_IPI_PL_2, 172 NODE_IPI_PL_3, 173 NODE_PL, 174 NODE_GEM_TSU, 175 NODE_SWDT_0, 176 NODE_SWDT_1, 177 NODE_CSU, 178 NODE_PJTAG, 179 NODE_TRACE, 180 NODE_TESTSCAN, 181 NODE_PMU, 182 NODE_MAX, 183 }; 184 185 enum pm_request_ack { 186 REQ_ACK_NO = 1, 187 REQ_ACK_BLOCKING, 188 REQ_ACK_NON_BLOCKING, 189 }; 190 191 enum pm_abort_reason { 192 ABORT_REASON_WKUP_EVENT = 100, 193 ABORT_REASON_PU_BUSY, 194 ABORT_REASON_NO_PWRDN, 195 ABORT_REASON_UNKNOWN, 196 }; 197 198 enum pm_suspend_reason { 199 SUSPEND_REASON_PU_REQ = 201, 200 SUSPEND_REASON_ALERT, 201 SUSPEND_REASON_SYS_SHUTDOWN, 202 }; 203 204 enum pm_ram_state { 205 PM_RAM_STATE_OFF = 1, 206 PM_RAM_STATE_RETENTION, 207 PM_RAM_STATE_ON, 208 }; 209 210 enum pm_opchar_type { 211 PM_OPCHAR_TYPE_POWER = 1, 212 PM_OPCHAR_TYPE_TEMP, 213 PM_OPCHAR_TYPE_LATENCY, 214 }; 215 216 /** 217 * @PM_RET_SUCCESS: success 218 * @PM_RET_ERROR_ARGS: illegal arguments provided 219 * @PM_RET_ERROR_ACCESS: access rights violation 220 * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU 221 * @PM_RET_ERROR_NOTSUPPORTED: feature not supported 222 * @PM_RET_ERROR_PROC: node is not a processor node 223 * @PM_RET_ERROR_API_ID: illegal API ID 224 * @PM_RET_ERROR_OTHER: other error 225 */ 226 enum pm_ret_status { 227 PM_RET_SUCCESS, 228 PM_RET_ERROR_ARGS, 229 PM_RET_ERROR_ACCESS, 230 PM_RET_ERROR_TIMEOUT, 231 PM_RET_ERROR_NOTSUPPORTED, 232 PM_RET_ERROR_PROC, 233 PM_RET_ERROR_API_ID, 234 PM_RET_ERROR_FAILURE, 235 PM_RET_ERROR_COMMUNIC, 236 PM_RET_ERROR_DOUBLEREQ, 237 PM_RET_ERROR_OTHER, 238 }; 239 240 /** 241 * @PM_INITIAL_BOOT: boot is a fresh system startup 242 * @PM_RESUME: boot is a resume 243 * @PM_BOOT_ERROR: error, boot cause cannot be identified 244 */ 245 enum pm_boot_status { 246 PM_INITIAL_BOOT, 247 PM_RESUME, 248 PM_BOOT_ERROR, 249 }; 250 251 /** 252 * @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown 253 * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot 254 * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope 255 */ 256 enum pm_shutdown_type { 257 PMF_SHUTDOWN_TYPE_SHUTDOWN, 258 PMF_SHUTDOWN_TYPE_RESET, 259 PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY, 260 }; 261 262 /** 263 * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only 264 * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL) 265 * @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system 266 */ 267 enum pm_shutdown_subtype { 268 PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM, 269 PMF_SHUTDOWN_SUBTYPE_PS_ONLY, 270 PMF_SHUTDOWN_SUBTYPE_SYSTEM, 271 }; 272 273 /** 274 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL 275 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL 276 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL 277 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input 278 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode 279 * @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize 280 * @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting 281 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control 282 * @PM_PLL_PARAM_CP: PLL charge pump control 283 * @PM_PLL_PARAM_RES: PLL loop filter resistor control 284 */ 285 enum pm_pll_param { 286 PM_PLL_PARAM_DIV2, 287 PM_PLL_PARAM_FBDIV, 288 PM_PLL_PARAM_DATA, 289 PM_PLL_PARAM_PRE_SRC, 290 PM_PLL_PARAM_POST_SRC, 291 PM_PLL_PARAM_LOCK_DLY, 292 PM_PLL_PARAM_LOCK_CNT, 293 PM_PLL_PARAM_LFHF, 294 PM_PLL_PARAM_CP, 295 PM_PLL_PARAM_RES, 296 PM_PLL_PARAM_MAX, 297 }; 298 299 /** 300 * @PM_PLL_MODE_RESET: PLL is in reset (not locked) 301 * @PM_PLL_MODE_INTEGER: PLL is locked in integer mode 302 * @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode 303 */ 304 enum pm_pll_mode { 305 PM_PLL_MODE_RESET, 306 PM_PLL_MODE_INTEGER, 307 PM_PLL_MODE_FRACTIONAL, 308 PM_PLL_MODE_MAX, 309 }; 310 311 /** 312 * @PM_CLOCK_DIV0_ID: Clock divider 0 313 * @PM_CLOCK_DIV1_ID: Clock divider 1 314 */ 315 enum pm_clock_div_id { 316 PM_CLOCK_DIV0_ID, 317 PM_CLOCK_DIV1_ID, 318 }; 319 320 #endif /* PM_DEFS_H */ 321