| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.h | 56 const TargetRegisterClass *NewRC = nullptr; variable
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| D | CriticalAntiDepBreaker.cpp | 193 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
311 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
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| D | MachineRegisterInfo.cpp | 75 const TargetRegisterClass *NewRC = in constrainRegClass() local
133 const TargetRegisterClass *NewRC = in recomputeRegClass() local
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| D | TailDuplicator.cpp | 434 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
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| D | PeepholeOptimizer.cpp | 761 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI() local
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| D | RegisterCoalescer.cpp | 1181 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.h | 57 const TargetRegisterClass *NewRC; variable
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| D | CriticalAntiDepBreaker.cpp | 176 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction() local
294 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction() local
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| D | MachineRegisterInfo.cpp | 56 const TargetRegisterClass *NewRC = in constrainRegClass() local
70 const TargetRegisterClass *NewRC = in recomputeRegClass() local
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| D | TailDuplicator.cpp | 392 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction() local
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| D | PeepholeOptimizer.cpp | 719 const TargetRegisterClass *NewRC = MRI->getRegClass(SrcRegs[0].Reg); in insertPHI() local
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| D | RegisterCoalescer.cpp | 965 const TargetRegisterClass *NewRC = CP.getNewRC(); in reMaterializeTrivialDef() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.cpp | 250 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { in shouldCoalesce() argument
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| D | HexagonVLIWPacketizer.cpp | 351 const TargetRegisterClass *NewRC) { in isNewifiable()
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| D | HexagonBitSimplify.cpp | 2613 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
2681 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0() local
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| D | HexagonFrameLowering.cpp | 2010 const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { in optimizeSpillSlots()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 252 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 807 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 924 const TargetRegisterClass *NewRC) const in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 980 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /external/llvm/lib/Analysis/ |
| D | LazyCallGraph.cpp | 1502 RefSCC *NewRC = createRefSCC(*this); in getNextRefSCCInPostOrder() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | LazyCallGraph.cpp | 1712 RefSCC *NewRC = createRefSCC(*this); in buildRefSCCs() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 1516 const TargetRegisterClass *NewRC, in shouldCoalesce()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 3098 const TargetRegisterClass *NewRC = in transformToImmForm() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1904 -> const TargetRegisterClass* { in optimizeSpillSlots()
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