1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Based on Linux i.MX iomux-v3.h file: 4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, 5 * <armlinux@phytec.de> 6 * 7 * Copyright (C) 2011 Freescale Semiconductor, Inc. 8 */ 9 10 #ifndef __MACH_IOMUX_V3_H__ 11 #define __MACH_IOMUX_V3_H__ 12 13 #include <common.h> 14 15 /* 16 * build IOMUX_PAD structure 17 * 18 * This iomux scheme is based around pads, which are the physical balls 19 * on the processor. 20 * 21 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls 22 * things like driving strength and pullup/pulldown. 23 * - Each pad can have but not necessarily does have an output routing register 24 * (IOMUXC_SW_MUX_CTL_PAD_x). 25 * - Each pad can have but not necessarily does have an input routing register 26 * (IOMUXC_x_SELECT_INPUT) 27 * 28 * The three register sets do not have a fixed offset to each other, 29 * hence we order this table by pad control registers (which all pads 30 * have) and put the optional i/o routing registers into additional 31 * fields. 32 * 33 * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode> 34 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> 35 * 36 * IOMUX/PAD Bit field definitions 37 * 38 * MUX_CTRL_OFS: 0..11 (12) 39 * PAD_CTRL_OFS: 12..23 (12) 40 * SEL_INPUT_OFS: 24..35 (12) 41 * MUX_MODE + SION + LPSR: 36..41 (6) 42 * PAD_CTRL + NO_PAD_CTRL: 42..59 (18) 43 * SEL_INP: 60..63 (4) 44 */ 45 46 typedef u64 iomux_v3_cfg_t; 47 48 #define MUX_CTRL_OFS_SHIFT 0 49 #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) 50 #define MUX_PAD_CTRL_OFS_SHIFT 12 51 #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ 52 MUX_PAD_CTRL_OFS_SHIFT) 53 #define MUX_SEL_INPUT_OFS_SHIFT 24 54 #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \ 55 MUX_SEL_INPUT_OFS_SHIFT) 56 57 #define MUX_MODE_SHIFT 36 58 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT) 59 #define MUX_PAD_CTRL_SHIFT 42 60 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) 61 #define MUX_SEL_INPUT_SHIFT 60 62 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) 63 64 #define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ 65 MUX_MODE_SHIFT) 66 #define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) 67 68 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ 69 sel_input, pad_ctrl) \ 70 (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ 71 ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \ 72 ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ 73 ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ 74 ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \ 75 ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT)) 76 77 #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \ 78 MUX_PAD_CTRL(pad)) 79 80 #define __NA_ 0x000 81 #define NO_MUX_I 0 82 #define NO_PAD_I 0 83 84 #define NO_PAD_CTRL (1 << 17) 85 86 #define IOMUX_CONFIG_LPSR 0x20 87 #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ 88 MUX_MODE_SHIFT) 89 #ifdef CONFIG_IMX8M 90 #define PAD_CTL_DSE0 (0x0 << 0) 91 #define PAD_CTL_DSE1 (0x1 << 0) 92 #define PAD_CTL_DSE2 (0x2 << 0) 93 #define PAD_CTL_DSE3 (0x3 << 0) 94 #define PAD_CTL_DSE4 (0x4 << 0) 95 #define PAD_CTL_DSE5 (0x5 << 0) 96 #define PAD_CTL_DSE6 (0x6 << 0) 97 #define PAD_CTL_DSE7 (0x7 << 0) 98 99 #define PAD_CTL_FSEL0 (0x0 << 3) 100 #define PAD_CTL_FSEL1 (0x1 << 3) 101 #define PAD_CTL_FSEL2 (0x2 << 3) 102 #define PAD_CTL_FSEL3 (0x3 << 3) 103 104 #define PAD_CTL_ODE (0x1 << 5) 105 #define PAD_CTL_PUE (0x1 << 6) 106 #define PAD_CTL_HYS (0x1 << 7) 107 #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) 108 #define PAD_CTL_PE (0x1 << 8) 109 #else 110 #define PAD_CTL_LVTTL (0x1 << 8) 111 #endif 112 113 #elif defined CONFIG_MX7 114 115 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 116 117 #define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) 118 #define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) 119 #define PAD_CTL_DSE_1P8V_70OHM (0x2<<0) 120 #define PAD_CTL_DSE_1P8V_23OHM (0x3<<0) 121 122 #define PAD_CTL_DSE_3P3V_196OHM (0x0<<0) 123 #define PAD_CTL_DSE_3P3V_49OHM (0x1<<0) 124 #define PAD_CTL_DSE_3P3V_98OHM (0x2<<0) 125 #define PAD_CTL_DSE_3P3V_32OHM (0x3<<0) 126 127 #define PAD_CTL_SRE_FAST (0 << 2) 128 #define PAD_CTL_SRE_SLOW (0x1 << 2) 129 130 #define PAD_CTL_HYS (0x1 << 3) 131 #define PAD_CTL_PUE (0x1 << 4) 132 133 #define PAD_CTL_PUS_PD100KOHM ((0x0 << 5) | PAD_CTL_PUE) 134 #define PAD_CTL_PUS_PU5KOHM ((0x1 << 5) | PAD_CTL_PUE) 135 #define PAD_CTL_PUS_PU47KOHM ((0x2 << 5) | PAD_CTL_PUE) 136 #define PAD_CTL_PUS_PU100KOHM ((0x3 << 5) | PAD_CTL_PUE) 137 138 #else 139 140 #ifdef CONFIG_MX6 141 142 #define PAD_CTL_HYS (1 << 16) 143 144 #define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) 145 #define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) 146 #define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) 147 #define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) 148 #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) 149 #define PAD_CTL_PKE (1 << 12) 150 151 #define PAD_CTL_ODE (1 << 11) 152 153 #if defined(CONFIG_MX6SL) 154 #define PAD_CTL_SPEED_LOW (1 << 6) 155 #else 156 #define PAD_CTL_SPEED_LOW (0 << 6) 157 #endif 158 #define PAD_CTL_SPEED_MED (2 << 6) 159 #define PAD_CTL_SPEED_HIGH (3 << 6) 160 161 #define PAD_CTL_DSE_DISABLE (0 << 3) 162 #define PAD_CTL_DSE_240ohm (1 << 3) 163 #define PAD_CTL_DSE_120ohm (2 << 3) 164 #define PAD_CTL_DSE_80ohm (3 << 3) 165 #define PAD_CTL_DSE_60ohm (4 << 3) 166 #define PAD_CTL_DSE_48ohm (5 << 3) 167 #define PAD_CTL_DSE_40ohm (6 << 3) 168 #define PAD_CTL_DSE_34ohm (7 << 3) 169 170 #define PAD_CTL_DSE_260ohm (1 << 3) 171 #define PAD_CTL_DSE_130ohm (2 << 3) 172 #define PAD_CTL_DSE_88ohm (3 << 3) 173 #define PAD_CTL_DSE_65ohm (4 << 3) 174 #define PAD_CTL_DSE_52ohm (5 << 3) 175 #define PAD_CTL_DSE_43ohm (6 << 3) 176 #define PAD_CTL_DSE_37ohm (7 << 3) 177 178 /* i.MX6SL/SLL */ 179 #define PAD_CTL_LVE (1 << 1) 180 #define PAD_CTL_LVE_BIT (1 << 22) 181 182 /* i.MX6SLL */ 183 #define PAD_CTL_IPD_BIT (1 << 27) 184 185 #elif defined(CONFIG_VF610) 186 187 #define PAD_MUX_MODE_SHIFT 20 188 189 #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16) 190 191 #define PAD_CTL_SPEED_MED (1 << 12) 192 #define PAD_CTL_SPEED_HIGH (3 << 12) 193 194 #define PAD_CTL_SRE (1 << 11) 195 196 #define PAD_CTL_ODE (1 << 10) 197 198 #define PAD_CTL_DSE_150ohm (1 << 6) 199 #define PAD_CTL_DSE_75ohm (2 << 6) 200 #define PAD_CTL_DSE_50ohm (3 << 6) 201 #define PAD_CTL_DSE_37ohm (4 << 6) 202 #define PAD_CTL_DSE_30ohm (5 << 6) 203 #define PAD_CTL_DSE_25ohm (6 << 6) 204 #define PAD_CTL_DSE_20ohm (7 << 6) 205 206 #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) 207 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) 208 #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) 209 #define PAD_CTL_PKE (1 << 3) 210 #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) 211 212 #define PAD_CTL_OBE_IBE_ENABLE (3 << 0) 213 #define PAD_CTL_OBE_ENABLE (1 << 1) 214 #define PAD_CTL_IBE_ENABLE (1 << 0) 215 216 #else 217 218 #define PAD_CTL_DVS (1 << 13) 219 #define PAD_CTL_INPUT_DDR (1 << 9) 220 #define PAD_CTL_HYS (1 << 8) 221 222 #define PAD_CTL_PKE (1 << 7) 223 #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) 224 #define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) 225 #define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) 226 #define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) 227 #define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) 228 229 #define PAD_CTL_ODE (1 << 3) 230 231 #define PAD_CTL_DSE_LOW (0 << 1) 232 #define PAD_CTL_DSE_MED (1 << 1) 233 #define PAD_CTL_DSE_HIGH (2 << 1) 234 #define PAD_CTL_DSE_MAX (3 << 1) 235 236 #endif 237 238 #define PAD_CTL_SRE_SLOW (0 << 0) 239 #define PAD_CTL_SRE_FAST (1 << 0) 240 241 #endif 242 243 #define IOMUX_CONFIG_SION 0x10 244 245 #define GPIO_PIN_MASK 0x1f 246 #define GPIO_PORT_SHIFT 5 247 #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) 248 #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) 249 #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) 250 #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) 251 #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) 252 #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) 253 #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) 254 255 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); 256 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, 257 unsigned count); 258 /* 259 * Set bits for general purpose registers 260 */ 261 void imx_iomux_set_gpr_register(int group, int start_bit, 262 int num_bits, int value); 263 #ifdef CONFIG_IOMUX_SHARE_CONF_REG 264 void imx_iomux_gpio_set_direction(unsigned int gpio, 265 unsigned int direction); 266 void imx_iomux_gpio_get_function(unsigned int gpio, 267 u32 *gpio_state); 268 #endif 269 270 /* macros for declaring and using pinmux array */ 271 #if defined(CONFIG_MX6QDL) 272 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x) 273 #define SETUP_IOMUX_PAD(def) \ 274 if (is_mx6dq() || is_mx6dqp()) { \ 275 imx_iomux_v3_setup_pad(MX6Q_##def); \ 276 } else { \ 277 imx_iomux_v3_setup_pad(MX6DL_##def); \ 278 } 279 #define SETUP_IOMUX_PADS(x) \ 280 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) 281 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) 282 #define IOMUX_PADS(x) MX6Q_##x 283 #define SETUP_IOMUX_PAD(def) \ 284 imx_iomux_v3_setup_pad(MX6Q_##def); 285 #define SETUP_IOMUX_PADS(x) \ 286 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) 287 #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) 288 #define IOMUX_PADS(x) MX6_##x 289 #define SETUP_IOMUX_PAD(def) \ 290 imx_iomux_v3_setup_pad(MX6_##def); 291 #define SETUP_IOMUX_PADS(x) \ 292 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) 293 #else 294 #define IOMUX_PADS(x) MX6DL_##x 295 #define SETUP_IOMUX_PAD(def) \ 296 imx_iomux_v3_setup_pad(MX6DL_##def); 297 #define SETUP_IOMUX_PADS(x) \ 298 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) 299 #endif 300 301 #endif /* __MACH_IOMUX_V3_H__*/ 302