1 // Copyright 2015, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
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12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
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15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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26
27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_
28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_
29
30 #include "../globals-vixl.h"
31
32 namespace vixl {
33 namespace aarch64 {
34
35 const unsigned kNumberOfRegisters = 32;
36 const unsigned kNumberOfVRegisters = 32;
37 // Callee saved registers are x21-x30(lr).
38 const int kNumberOfCalleeSavedRegisters = 10;
39 const int kFirstCalleeSavedRegisterIndex = 21;
40 // Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are
41 // still caller-saved.
42 const int kNumberOfCalleeSavedFPRegisters = 8;
43 const int kFirstCalleeSavedFPRegisterIndex = 8;
44
45 // clang-format off
46 #define AARCH64_REGISTER_CODE_LIST(R) \
47 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
48 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
49 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
50 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
51
52 #define INSTRUCTION_FIELDS_LIST(V_) \
53 /* Register fields */ \
54 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \
55 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \
56 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \
57 V_(RmLow16, 19, 16, ExtractBits) /* Second source register (code 0-15). */ \
58 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \
59 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \
60 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \
61 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \
62 \
63 /* Common bits */ \
64 V_(SixtyFourBits, 31, 31, ExtractBits) \
65 V_(FlagsUpdate, 29, 29, ExtractBits) \
66 \
67 /* PC relative addressing */ \
68 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \
69 V_(ImmPCRelLo, 30, 29, ExtractBits) \
70 \
71 /* Add/subtract/logical shift register */ \
72 V_(ShiftDP, 23, 22, ExtractBits) \
73 V_(ImmDPShift, 15, 10, ExtractBits) \
74 \
75 /* Add/subtract immediate */ \
76 V_(ImmAddSub, 21, 10, ExtractBits) \
77 V_(ShiftAddSub, 23, 22, ExtractBits) \
78 \
79 /* Add/substract extend */ \
80 V_(ImmExtendShift, 12, 10, ExtractBits) \
81 V_(ExtendMode, 15, 13, ExtractBits) \
82 \
83 /* Move wide */ \
84 V_(ImmMoveWide, 20, 5, ExtractBits) \
85 V_(ShiftMoveWide, 22, 21, ExtractBits) \
86 \
87 /* Logical immediate, bitfield and extract */ \
88 V_(BitN, 22, 22, ExtractBits) \
89 V_(ImmRotate, 21, 16, ExtractBits) \
90 V_(ImmSetBits, 15, 10, ExtractBits) \
91 V_(ImmR, 21, 16, ExtractBits) \
92 V_(ImmS, 15, 10, ExtractBits) \
93 \
94 /* Test and branch immediate */ \
95 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \
96 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \
97 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \
98 \
99 /* Conditionals */ \
100 V_(Condition, 15, 12, ExtractBits) \
101 V_(ConditionBranch, 3, 0, ExtractBits) \
102 V_(Nzcv, 3, 0, ExtractBits) \
103 V_(ImmCondCmp, 20, 16, ExtractBits) \
104 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \
105 \
106 /* Floating point */ \
107 V_(FPType, 23, 22, ExtractBits) \
108 V_(ImmFP, 20, 13, ExtractBits) \
109 V_(FPScale, 15, 10, ExtractBits) \
110 \
111 /* Load Store */ \
112 V_(ImmLS, 20, 12, ExtractSignedBits) \
113 V_(ImmLSUnsigned, 21, 10, ExtractBits) \
114 V_(ImmLSPair, 21, 15, ExtractSignedBits) \
115 V_(ImmShiftLS, 12, 12, ExtractBits) \
116 V_(LSOpc, 23, 22, ExtractBits) \
117 V_(LSVector, 26, 26, ExtractBits) \
118 V_(LSSize, 31, 30, ExtractBits) \
119 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \
120 V_(PrefetchHint, 4, 3, ExtractBits) \
121 V_(PrefetchTarget, 2, 1, ExtractBits) \
122 V_(PrefetchStream, 0, 0, ExtractBits) \
123 V_(ImmLSPACHi, 22, 22, ExtractSignedBits) \
124 V_(ImmLSPACLo, 20, 12, ExtractBits) \
125 \
126 /* Other immediates */ \
127 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \
128 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \
129 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \
130 V_(ImmException, 20, 5, ExtractBits) \
131 V_(ImmHint, 11, 5, ExtractBits) \
132 V_(ImmBarrierDomain, 11, 10, ExtractBits) \
133 V_(ImmBarrierType, 9, 8, ExtractBits) \
134 V_(ImmUdf, 15, 0, ExtractBits) \
135 \
136 /* System (MRS, MSR, SYS) */ \
137 V_(ImmSystemRegister, 20, 5, ExtractBits) \
138 V_(SysO0, 19, 19, ExtractBits) \
139 V_(SysOp, 18, 5, ExtractBits) \
140 V_(SysOp0, 20, 19, ExtractBits) \
141 V_(SysOp1, 18, 16, ExtractBits) \
142 V_(SysOp2, 7, 5, ExtractBits) \
143 V_(CRn, 15, 12, ExtractBits) \
144 V_(CRm, 11, 8, ExtractBits) \
145 V_(ImmRMIFRotation, 20, 15, ExtractBits) \
146 \
147 /* Load-/store-exclusive */ \
148 V_(LdStXLoad, 22, 22, ExtractBits) \
149 V_(LdStXNotExclusive, 23, 23, ExtractBits) \
150 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \
151 V_(LdStXSizeLog2, 31, 30, ExtractBits) \
152 V_(LdStXPair, 21, 21, ExtractBits) \
153 \
154 /* NEON generic fields */ \
155 V_(NEONQ, 30, 30, ExtractBits) \
156 V_(NEONSize, 23, 22, ExtractBits) \
157 V_(NEONLSSize, 11, 10, ExtractBits) \
158 V_(NEONS, 12, 12, ExtractBits) \
159 V_(NEONL, 21, 21, ExtractBits) \
160 V_(NEONM, 20, 20, ExtractBits) \
161 V_(NEONH, 11, 11, ExtractBits) \
162 V_(ImmNEONExt, 14, 11, ExtractBits) \
163 V_(ImmNEON5, 20, 16, ExtractBits) \
164 V_(ImmNEON4, 14, 11, ExtractBits) \
165 \
166 /* NEON extra fields */ \
167 V_(ImmRotFcadd, 12, 12, ExtractBits) \
168 V_(ImmRotFcmlaVec, 12, 11, ExtractBits) \
169 V_(ImmRotFcmlaSca, 14, 13, ExtractBits) \
170 \
171 /* NEON Modified Immediate fields */ \
172 V_(ImmNEONabc, 18, 16, ExtractBits) \
173 V_(ImmNEONdefgh, 9, 5, ExtractBits) \
174 V_(NEONModImmOp, 29, 29, ExtractBits) \
175 V_(NEONCmode, 15, 12, ExtractBits) \
176 \
177 /* NEON Shift Immediate fields */ \
178 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \
179 V_(ImmNEONImmh, 22, 19, ExtractBits) \
180 V_(ImmNEONImmb, 18, 16, ExtractBits)
181 // clang-format on
182
183 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
184 /* NZCV */ \
185 V_(Flags, 31, 28, ExtractBits) \
186 V_(N, 31, 31, ExtractBits) \
187 V_(Z, 30, 30, ExtractBits) \
188 V_(C, 29, 29, ExtractBits) \
189 V_(V, 28, 28, ExtractBits) \
190 M_(NZCV, Flags_mask) \
191 /* FPCR */ \
192 V_(AHP, 26, 26, ExtractBits) \
193 V_(DN, 25, 25, ExtractBits) \
194 V_(FZ, 24, 24, ExtractBits) \
195 V_(RMode, 23, 22, ExtractBits) \
196 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
197
198 // Fields offsets.
199 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
200 const int Name##_offset = LowBit; \
201 const int Name##_width = HighBit - LowBit + 1; \
202 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
203 #define NOTHING(A, B)
204 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
205 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
206 #undef NOTHING
207 #undef DECLARE_FIELDS_BITS
208
209 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
210 // from ImmPCRelLo and ImmPCRelHi.
211 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
212
213 // Disable `clang-format` for the `enum`s below. We care about the manual
214 // formatting that `clang-format` would destroy.
215 // clang-format off
216
217 // Condition codes.
218 enum Condition {
219 eq = 0, // Z set Equal.
220 ne = 1, // Z clear Not equal.
221 cs = 2, // C set Carry set.
222 cc = 3, // C clear Carry clear.
223 mi = 4, // N set Negative.
224 pl = 5, // N clear Positive or zero.
225 vs = 6, // V set Overflow.
226 vc = 7, // V clear No overflow.
227 hi = 8, // C set, Z clear Unsigned higher.
228 ls = 9, // C clear or Z set Unsigned lower or same.
229 ge = 10, // N == V Greater or equal.
230 lt = 11, // N != V Less than.
231 gt = 12, // Z clear, N == V Greater than.
232 le = 13, // Z set or N != V Less then or equal
233 al = 14, // Always.
234 nv = 15, // Behaves as always/al.
235
236 // Aliases.
237 hs = cs, // C set Unsigned higher or same.
238 lo = cc // C clear Unsigned lower.
239 };
240
InvertCondition(Condition cond)241 inline Condition InvertCondition(Condition cond) {
242 // Conditions al and nv behave identically, as "always true". They can't be
243 // inverted, because there is no "always false" condition.
244 VIXL_ASSERT((cond != al) && (cond != nv));
245 return static_cast<Condition>(cond ^ 1);
246 }
247
248 enum FPTrapFlags {
249 EnableTrap = 1,
250 DisableTrap = 0
251 };
252
253 enum FlagsUpdate {
254 SetFlags = 1,
255 LeaveFlags = 0
256 };
257
258 enum StatusFlags {
259 NoFlag = 0,
260
261 // Derive the flag combinations from the system register bit descriptions.
262 NFlag = N_mask,
263 ZFlag = Z_mask,
264 CFlag = C_mask,
265 VFlag = V_mask,
266 NZFlag = NFlag | ZFlag,
267 NCFlag = NFlag | CFlag,
268 NVFlag = NFlag | VFlag,
269 ZCFlag = ZFlag | CFlag,
270 ZVFlag = ZFlag | VFlag,
271 CVFlag = CFlag | VFlag,
272 NZCFlag = NFlag | ZFlag | CFlag,
273 NZVFlag = NFlag | ZFlag | VFlag,
274 NCVFlag = NFlag | CFlag | VFlag,
275 ZCVFlag = ZFlag | CFlag | VFlag,
276 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
277
278 // Floating-point comparison results.
279 FPEqualFlag = ZCFlag,
280 FPLessThanFlag = NFlag,
281 FPGreaterThanFlag = CFlag,
282 FPUnorderedFlag = CVFlag
283 };
284
285 enum Shift {
286 NO_SHIFT = -1,
287 LSL = 0x0,
288 LSR = 0x1,
289 ASR = 0x2,
290 ROR = 0x3,
291 MSL = 0x4
292 };
293
294 enum Extend {
295 NO_EXTEND = -1,
296 UXTB = 0,
297 UXTH = 1,
298 UXTW = 2,
299 UXTX = 3,
300 SXTB = 4,
301 SXTH = 5,
302 SXTW = 6,
303 SXTX = 7
304 };
305
306 enum SystemHint {
307 NOP = 0,
308 YIELD = 1,
309 WFE = 2,
310 WFI = 3,
311 SEV = 4,
312 SEVL = 5,
313 ESB = 16,
314 CSDB = 20,
315 BTI = 32,
316 BTI_c = 34,
317 BTI_j = 36,
318 BTI_jc = 38
319 };
320
321 enum BranchTargetIdentifier {
322 EmitBTI_none = NOP,
323 EmitBTI = BTI,
324 EmitBTI_c = BTI_c,
325 EmitBTI_j = BTI_j,
326 EmitBTI_jc = BTI_jc,
327
328 // These correspond to the values of the CRm:op2 fields in the equivalent HINT
329 // instruction.
330 EmitPACIASP = 25,
331 EmitPACIBSP = 27
332 };
333
334 enum BarrierDomain {
335 OuterShareable = 0,
336 NonShareable = 1,
337 InnerShareable = 2,
338 FullSystem = 3
339 };
340
341 enum BarrierType {
342 BarrierOther = 0,
343 BarrierReads = 1,
344 BarrierWrites = 2,
345 BarrierAll = 3
346 };
347
348 enum PrefetchOperation {
349 PLDL1KEEP = 0x00,
350 PLDL1STRM = 0x01,
351 PLDL2KEEP = 0x02,
352 PLDL2STRM = 0x03,
353 PLDL3KEEP = 0x04,
354 PLDL3STRM = 0x05,
355
356 PLIL1KEEP = 0x08,
357 PLIL1STRM = 0x09,
358 PLIL2KEEP = 0x0a,
359 PLIL2STRM = 0x0b,
360 PLIL3KEEP = 0x0c,
361 PLIL3STRM = 0x0d,
362
363 PSTL1KEEP = 0x10,
364 PSTL1STRM = 0x11,
365 PSTL2KEEP = 0x12,
366 PSTL2STRM = 0x13,
367 PSTL3KEEP = 0x14,
368 PSTL3STRM = 0x15
369 };
370
371 enum BType {
372 // Set when executing any instruction on a guarded page, except those cases
373 // listed below.
374 DefaultBType = 0,
375
376 // Set when an indirect branch is taken from an unguarded page to a guarded
377 // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0".
378 BranchFromUnguardedOrToIP = 1,
379
380 // Set when an indirect branch and link (call) is taken, eg. "blr x0".
381 BranchAndLink = 2,
382
383 // Set when an indirect branch is taken from a guarded page to a register
384 // that is not ip0 or ip1 (x16 or x17), eg, "br x0".
385 BranchFromGuardedNotToIP = 3
386 };
387
388 template<int op0, int op1, int crn, int crm, int op2>
389 class SystemRegisterEncoder {
390 public:
391 static const uint32_t value =
392 ((op0 << SysO0_offset) |
393 (op1 << SysOp1_offset) |
394 (crn << CRn_offset) |
395 (crm << CRm_offset) |
396 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset;
397 };
398
399 // System/special register names.
400 // This information is not encoded as one field but as the concatenation of
401 // multiple fields (Op0, Op1, Crn, Crm, Op2).
402 enum SystemRegister {
403 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
404 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value,
405 RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number.
406 RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value // Reseeded random number.
407 };
408
409 template<int op1, int crn, int crm, int op2>
410 class CacheOpEncoder {
411 public:
412 static const uint32_t value =
413 ((op1 << SysOp1_offset) |
414 (crn << CRn_offset) |
415 (crm << CRm_offset) |
416 (op2 << SysOp2_offset)) >> SysOp_offset;
417 };
418
419 enum InstructionCacheOp {
420 IVAU = CacheOpEncoder<3, 7, 5, 1>::value
421 };
422
423 enum DataCacheOp {
424 CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
425 CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
426 CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
427 CVADP = CacheOpEncoder<3, 7, 13, 1>::value,
428 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
429 ZVA = CacheOpEncoder<3, 7, 4, 1>::value
430 };
431
432 // Instruction enumerations.
433 //
434 // These are the masks that define a class of instructions, and the list of
435 // instructions within each class. Each enumeration has a Fixed, FMask and
436 // Mask value.
437 //
438 // Fixed: The fixed bits in this instruction class.
439 // FMask: The mask used to extract the fixed bits in the class.
440 // Mask: The mask used to identify the instructions within a class.
441 //
442 // The enumerations can be used like this:
443 //
444 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
445 // switch(instr->Mask(PCRelAddressingMask)) {
446 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
447 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
448 // default: printf("Unknown instruction\n");
449 // }
450
451
452 // Generic fields.
453 enum GenericInstrField {
454 SixtyFourBits = 0x80000000,
455 ThirtyTwoBits = 0x00000000,
456
457 FPTypeMask = 0x00C00000,
458 FP16 = 0x00C00000,
459 FP32 = 0x00000000,
460 FP64 = 0x00400000
461 };
462
463 enum NEONFormatField {
464 NEONFormatFieldMask = 0x40C00000,
465 NEON_Q = 0x40000000,
466 NEON_8B = 0x00000000,
467 NEON_16B = NEON_8B | NEON_Q,
468 NEON_4H = 0x00400000,
469 NEON_8H = NEON_4H | NEON_Q,
470 NEON_2S = 0x00800000,
471 NEON_4S = NEON_2S | NEON_Q,
472 NEON_1D = 0x00C00000,
473 NEON_2D = 0x00C00000 | NEON_Q
474 };
475
476 enum NEONFPFormatField {
477 NEONFPFormatFieldMask = 0x40400000,
478 NEON_FP_4H = FP16,
479 NEON_FP_2S = FP32,
480 NEON_FP_8H = FP16 | NEON_Q,
481 NEON_FP_4S = FP32 | NEON_Q,
482 NEON_FP_2D = FP64 | NEON_Q
483 };
484
485 enum NEONLSFormatField {
486 NEONLSFormatFieldMask = 0x40000C00,
487 LS_NEON_8B = 0x00000000,
488 LS_NEON_16B = LS_NEON_8B | NEON_Q,
489 LS_NEON_4H = 0x00000400,
490 LS_NEON_8H = LS_NEON_4H | NEON_Q,
491 LS_NEON_2S = 0x00000800,
492 LS_NEON_4S = LS_NEON_2S | NEON_Q,
493 LS_NEON_1D = 0x00000C00,
494 LS_NEON_2D = LS_NEON_1D | NEON_Q
495 };
496
497 enum NEONScalarFormatField {
498 NEONScalarFormatFieldMask = 0x00C00000,
499 NEONScalar = 0x10000000,
500 NEON_B = 0x00000000,
501 NEON_H = 0x00400000,
502 NEON_S = 0x00800000,
503 NEON_D = 0x00C00000
504 };
505
506 // PC relative addressing.
507 enum PCRelAddressingOp {
508 PCRelAddressingFixed = 0x10000000,
509 PCRelAddressingFMask = 0x1F000000,
510 PCRelAddressingMask = 0x9F000000,
511 ADR = PCRelAddressingFixed | 0x00000000,
512 ADRP = PCRelAddressingFixed | 0x80000000
513 };
514
515 // Add/sub (immediate, shifted and extended.)
516 const int kSFOffset = 31;
517 enum AddSubOp {
518 AddSubOpMask = 0x60000000,
519 AddSubSetFlagsBit = 0x20000000,
520 ADD = 0x00000000,
521 ADDS = ADD | AddSubSetFlagsBit,
522 SUB = 0x40000000,
523 SUBS = SUB | AddSubSetFlagsBit
524 };
525
526 #define ADD_SUB_OP_LIST(V) \
527 V(ADD), \
528 V(ADDS), \
529 V(SUB), \
530 V(SUBS)
531
532 enum AddSubImmediateOp {
533 AddSubImmediateFixed = 0x11000000,
534 AddSubImmediateFMask = 0x1F000000,
535 AddSubImmediateMask = 0xFF000000,
536 #define ADD_SUB_IMMEDIATE(A) \
537 A##_w_imm = AddSubImmediateFixed | A, \
538 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
539 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
540 #undef ADD_SUB_IMMEDIATE
541 };
542
543 enum AddSubShiftedOp {
544 AddSubShiftedFixed = 0x0B000000,
545 AddSubShiftedFMask = 0x1F200000,
546 AddSubShiftedMask = 0xFF200000,
547 #define ADD_SUB_SHIFTED(A) \
548 A##_w_shift = AddSubShiftedFixed | A, \
549 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
550 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
551 #undef ADD_SUB_SHIFTED
552 };
553
554 enum AddSubExtendedOp {
555 AddSubExtendedFixed = 0x0B200000,
556 AddSubExtendedFMask = 0x1F200000,
557 AddSubExtendedMask = 0xFFE00000,
558 #define ADD_SUB_EXTENDED(A) \
559 A##_w_ext = AddSubExtendedFixed | A, \
560 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
561 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
562 #undef ADD_SUB_EXTENDED
563 };
564
565 // Add/sub with carry.
566 enum AddSubWithCarryOp {
567 AddSubWithCarryFixed = 0x1A000000,
568 AddSubWithCarryFMask = 0x1FE00000,
569 AddSubWithCarryMask = 0xFFE0FC00,
570 ADC_w = AddSubWithCarryFixed | ADD,
571 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
572 ADC = ADC_w,
573 ADCS_w = AddSubWithCarryFixed | ADDS,
574 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
575 SBC_w = AddSubWithCarryFixed | SUB,
576 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
577 SBC = SBC_w,
578 SBCS_w = AddSubWithCarryFixed | SUBS,
579 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
580 };
581
582 // Rotate right into flags.
583 enum RotateRightIntoFlagsOp {
584 RotateRightIntoFlagsFixed = 0x1A000400,
585 RotateRightIntoFlagsFMask = 0x1FE07C00,
586 RotateRightIntoFlagsMask = 0xFFE07C10,
587 RMIF = RotateRightIntoFlagsFixed | 0xA0000000
588 };
589
590 // Evaluate into flags.
591 enum EvaluateIntoFlagsOp {
592 EvaluateIntoFlagsFixed = 0x1A000800,
593 EvaluateIntoFlagsFMask = 0x1FE03C00,
594 EvaluateIntoFlagsMask = 0xFFE07C1F,
595 SETF8 = EvaluateIntoFlagsFixed | 0x2000000D,
596 SETF16 = EvaluateIntoFlagsFixed | 0x2000400D
597 };
598
599
600 // Logical (immediate and shifted register).
601 enum LogicalOp {
602 LogicalOpMask = 0x60200000,
603 NOT = 0x00200000,
604 AND = 0x00000000,
605 BIC = AND | NOT,
606 ORR = 0x20000000,
607 ORN = ORR | NOT,
608 EOR = 0x40000000,
609 EON = EOR | NOT,
610 ANDS = 0x60000000,
611 BICS = ANDS | NOT
612 };
613
614 // Logical immediate.
615 enum LogicalImmediateOp {
616 LogicalImmediateFixed = 0x12000000,
617 LogicalImmediateFMask = 0x1F800000,
618 LogicalImmediateMask = 0xFF800000,
619 AND_w_imm = LogicalImmediateFixed | AND,
620 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
621 ORR_w_imm = LogicalImmediateFixed | ORR,
622 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
623 EOR_w_imm = LogicalImmediateFixed | EOR,
624 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
625 ANDS_w_imm = LogicalImmediateFixed | ANDS,
626 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
627 };
628
629 // Logical shifted register.
630 enum LogicalShiftedOp {
631 LogicalShiftedFixed = 0x0A000000,
632 LogicalShiftedFMask = 0x1F000000,
633 LogicalShiftedMask = 0xFF200000,
634 AND_w = LogicalShiftedFixed | AND,
635 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
636 AND_shift = AND_w,
637 BIC_w = LogicalShiftedFixed | BIC,
638 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
639 BIC_shift = BIC_w,
640 ORR_w = LogicalShiftedFixed | ORR,
641 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
642 ORR_shift = ORR_w,
643 ORN_w = LogicalShiftedFixed | ORN,
644 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
645 ORN_shift = ORN_w,
646 EOR_w = LogicalShiftedFixed | EOR,
647 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
648 EOR_shift = EOR_w,
649 EON_w = LogicalShiftedFixed | EON,
650 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
651 EON_shift = EON_w,
652 ANDS_w = LogicalShiftedFixed | ANDS,
653 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
654 ANDS_shift = ANDS_w,
655 BICS_w = LogicalShiftedFixed | BICS,
656 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
657 BICS_shift = BICS_w
658 };
659
660 // Move wide immediate.
661 enum MoveWideImmediateOp {
662 MoveWideImmediateFixed = 0x12800000,
663 MoveWideImmediateFMask = 0x1F800000,
664 MoveWideImmediateMask = 0xFF800000,
665 MOVN = 0x00000000,
666 MOVZ = 0x40000000,
667 MOVK = 0x60000000,
668 MOVN_w = MoveWideImmediateFixed | MOVN,
669 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
670 MOVZ_w = MoveWideImmediateFixed | MOVZ,
671 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
672 MOVK_w = MoveWideImmediateFixed | MOVK,
673 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
674 };
675
676 // Bitfield.
677 const int kBitfieldNOffset = 22;
678 enum BitfieldOp {
679 BitfieldFixed = 0x13000000,
680 BitfieldFMask = 0x1F800000,
681 BitfieldMask = 0xFF800000,
682 SBFM_w = BitfieldFixed | 0x00000000,
683 SBFM_x = BitfieldFixed | 0x80000000,
684 SBFM = SBFM_w,
685 BFM_w = BitfieldFixed | 0x20000000,
686 BFM_x = BitfieldFixed | 0xA0000000,
687 BFM = BFM_w,
688 UBFM_w = BitfieldFixed | 0x40000000,
689 UBFM_x = BitfieldFixed | 0xC0000000,
690 UBFM = UBFM_w
691 // Bitfield N field.
692 };
693
694 // Extract.
695 enum ExtractOp {
696 ExtractFixed = 0x13800000,
697 ExtractFMask = 0x1F800000,
698 ExtractMask = 0xFFA00000,
699 EXTR_w = ExtractFixed | 0x00000000,
700 EXTR_x = ExtractFixed | 0x80000000,
701 EXTR = EXTR_w
702 };
703
704 // Unconditional branch.
705 enum UnconditionalBranchOp {
706 UnconditionalBranchFixed = 0x14000000,
707 UnconditionalBranchFMask = 0x7C000000,
708 UnconditionalBranchMask = 0xFC000000,
709 B = UnconditionalBranchFixed | 0x00000000,
710 BL = UnconditionalBranchFixed | 0x80000000
711 };
712
713 // Unconditional branch to register.
714 enum UnconditionalBranchToRegisterOp {
715 UnconditionalBranchToRegisterFixed = 0xD6000000,
716 UnconditionalBranchToRegisterFMask = 0xFE000000,
717 UnconditionalBranchToRegisterMask = 0xFFFFFC00,
718 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
719 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
720 RET = UnconditionalBranchToRegisterFixed | 0x005F0000,
721
722 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800,
723 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00,
724 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800,
725 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00,
726 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800,
727 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00,
728 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800,
729 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00,
730 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800,
731 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00
732 };
733
734 // Compare and branch.
735 enum CompareBranchOp {
736 CompareBranchFixed = 0x34000000,
737 CompareBranchFMask = 0x7E000000,
738 CompareBranchMask = 0xFF000000,
739 CBZ_w = CompareBranchFixed | 0x00000000,
740 CBZ_x = CompareBranchFixed | 0x80000000,
741 CBZ = CBZ_w,
742 CBNZ_w = CompareBranchFixed | 0x01000000,
743 CBNZ_x = CompareBranchFixed | 0x81000000,
744 CBNZ = CBNZ_w
745 };
746
747 // Test and branch.
748 enum TestBranchOp {
749 TestBranchFixed = 0x36000000,
750 TestBranchFMask = 0x7E000000,
751 TestBranchMask = 0x7F000000,
752 TBZ = TestBranchFixed | 0x00000000,
753 TBNZ = TestBranchFixed | 0x01000000
754 };
755
756 // Conditional branch.
757 enum ConditionalBranchOp {
758 ConditionalBranchFixed = 0x54000000,
759 ConditionalBranchFMask = 0xFE000000,
760 ConditionalBranchMask = 0xFF000010,
761 B_cond = ConditionalBranchFixed | 0x00000000
762 };
763
764 // System.
765 // System instruction encoding is complicated because some instructions use op
766 // and CR fields to encode parameters. To handle this cleanly, the system
767 // instructions are split into more than one enum.
768
769 enum SystemOp {
770 SystemFixed = 0xD5000000,
771 SystemFMask = 0xFFC00000
772 };
773
774 enum SystemSysRegOp {
775 SystemSysRegFixed = 0xD5100000,
776 SystemSysRegFMask = 0xFFD00000,
777 SystemSysRegMask = 0xFFF00000,
778 MRS = SystemSysRegFixed | 0x00200000,
779 MSR = SystemSysRegFixed | 0x00000000
780 };
781
782 enum SystemPStateOp {
783 SystemPStateFixed = 0xD5004000,
784 SystemPStateFMask = 0xFFF8F000,
785 SystemPStateMask = 0xFFFFF0FF,
786 CFINV = SystemPStateFixed | 0x0000001F,
787 XAFLAG = SystemPStateFixed | 0x0000003F,
788 AXFLAG = SystemPStateFixed | 0x0000005F
789 };
790
791 enum SystemHintOp {
792 SystemHintFixed = 0xD503201F,
793 SystemHintFMask = 0xFFFFF01F,
794 SystemHintMask = 0xFFFFF01F,
795 HINT = SystemHintFixed | 0x00000000
796 };
797
798 enum SystemSysOp {
799 SystemSysFixed = 0xD5080000,
800 SystemSysFMask = 0xFFF80000,
801 SystemSysMask = 0xFFF80000,
802 SYS = SystemSysFixed | 0x00000000
803 };
804
805 // Exception.
806 enum ExceptionOp {
807 ExceptionFixed = 0xD4000000,
808 ExceptionFMask = 0xFF000000,
809 ExceptionMask = 0xFFE0001F,
810 HLT = ExceptionFixed | 0x00400000,
811 BRK = ExceptionFixed | 0x00200000,
812 SVC = ExceptionFixed | 0x00000001,
813 HVC = ExceptionFixed | 0x00000002,
814 SMC = ExceptionFixed | 0x00000003,
815 DCPS1 = ExceptionFixed | 0x00A00001,
816 DCPS2 = ExceptionFixed | 0x00A00002,
817 DCPS3 = ExceptionFixed | 0x00A00003
818 };
819
820 enum MemBarrierOp {
821 MemBarrierFixed = 0xD503309F,
822 MemBarrierFMask = 0xFFFFF09F,
823 MemBarrierMask = 0xFFFFF0FF,
824 DSB = MemBarrierFixed | 0x00000000,
825 DMB = MemBarrierFixed | 0x00000020,
826 ISB = MemBarrierFixed | 0x00000040
827 };
828
829 enum SystemExclusiveMonitorOp {
830 SystemExclusiveMonitorFixed = 0xD503305F,
831 SystemExclusiveMonitorFMask = 0xFFFFF0FF,
832 SystemExclusiveMonitorMask = 0xFFFFF0FF,
833 CLREX = SystemExclusiveMonitorFixed
834 };
835
836 enum SystemPAuthOp {
837 SystemPAuthFixed = 0xD503211F,
838 SystemPAuthFMask = 0xFFFFFD1F,
839 SystemPAuthMask = 0xFFFFFFFF,
840 PACIA1716 = SystemPAuthFixed | 0x00000100,
841 PACIB1716 = SystemPAuthFixed | 0x00000140,
842 AUTIA1716 = SystemPAuthFixed | 0x00000180,
843 AUTIB1716 = SystemPAuthFixed | 0x000001C0,
844 PACIAZ = SystemPAuthFixed | 0x00000300,
845 PACIASP = SystemPAuthFixed | 0x00000320,
846 PACIBZ = SystemPAuthFixed | 0x00000340,
847 PACIBSP = SystemPAuthFixed | 0x00000360,
848 AUTIAZ = SystemPAuthFixed | 0x00000380,
849 AUTIASP = SystemPAuthFixed | 0x000003A0,
850 AUTIBZ = SystemPAuthFixed | 0x000003C0,
851 AUTIBSP = SystemPAuthFixed | 0x000003E0,
852
853 // XPACLRI has the same fixed mask as System Hints and needs to be handled
854 // differently.
855 XPACLRI = 0xD50320FF
856 };
857
858 // Any load or store.
859 enum LoadStoreAnyOp {
860 LoadStoreAnyFMask = 0x0a000000,
861 LoadStoreAnyFixed = 0x08000000
862 };
863
864 // Any load pair or store pair.
865 enum LoadStorePairAnyOp {
866 LoadStorePairAnyFMask = 0x3a000000,
867 LoadStorePairAnyFixed = 0x28000000
868 };
869
870 #define LOAD_STORE_PAIR_OP_LIST(V) \
871 V(STP, w, 0x00000000), \
872 V(LDP, w, 0x00400000), \
873 V(LDPSW, x, 0x40400000), \
874 V(STP, x, 0x80000000), \
875 V(LDP, x, 0x80400000), \
876 V(STP, s, 0x04000000), \
877 V(LDP, s, 0x04400000), \
878 V(STP, d, 0x44000000), \
879 V(LDP, d, 0x44400000), \
880 V(STP, q, 0x84000000), \
881 V(LDP, q, 0x84400000)
882
883 // Load/store pair (post, pre and offset.)
884 enum LoadStorePairOp {
885 LoadStorePairMask = 0xC4400000,
886 LoadStorePairLBit = 1 << 22,
887 #define LOAD_STORE_PAIR(A, B, C) \
888 A##_##B = C
889 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
890 #undef LOAD_STORE_PAIR
891 };
892
893 enum LoadStorePairPostIndexOp {
894 LoadStorePairPostIndexFixed = 0x28800000,
895 LoadStorePairPostIndexFMask = 0x3B800000,
896 LoadStorePairPostIndexMask = 0xFFC00000,
897 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
898 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
899 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
900 #undef LOAD_STORE_PAIR_POST_INDEX
901 };
902
903 enum LoadStorePairPreIndexOp {
904 LoadStorePairPreIndexFixed = 0x29800000,
905 LoadStorePairPreIndexFMask = 0x3B800000,
906 LoadStorePairPreIndexMask = 0xFFC00000,
907 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
908 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
909 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
910 #undef LOAD_STORE_PAIR_PRE_INDEX
911 };
912
913 enum LoadStorePairOffsetOp {
914 LoadStorePairOffsetFixed = 0x29000000,
915 LoadStorePairOffsetFMask = 0x3B800000,
916 LoadStorePairOffsetMask = 0xFFC00000,
917 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
918 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
919 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
920 #undef LOAD_STORE_PAIR_OFFSET
921 };
922
923 enum LoadStorePairNonTemporalOp {
924 LoadStorePairNonTemporalFixed = 0x28000000,
925 LoadStorePairNonTemporalFMask = 0x3B800000,
926 LoadStorePairNonTemporalMask = 0xFFC00000,
927 LoadStorePairNonTemporalLBit = 1 << 22,
928 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
929 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
930 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
931 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
932 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
933 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
934 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
935 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
936 STNP_q = LoadStorePairNonTemporalFixed | STP_q,
937 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
938 };
939
940 // Load with pointer authentication.
941 enum LoadStorePACOp {
942 LoadStorePACFixed = 0xF8200400,
943 LoadStorePACFMask = 0xFF200400,
944 LoadStorePACMask = 0xFFA00C00,
945 LoadStorePACPreBit = 0x00000800,
946 LDRAA = LoadStorePACFixed | 0x00000000,
947 LDRAA_pre = LoadStorePACPreBit | LDRAA,
948 LDRAB = LoadStorePACFixed | 0x00800000,
949 LDRAB_pre = LoadStorePACPreBit | LDRAB
950 };
951
952 // Load literal.
953 enum LoadLiteralOp {
954 LoadLiteralFixed = 0x18000000,
955 LoadLiteralFMask = 0x3B000000,
956 LoadLiteralMask = 0xFF000000,
957 LDR_w_lit = LoadLiteralFixed | 0x00000000,
958 LDR_x_lit = LoadLiteralFixed | 0x40000000,
959 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
960 PRFM_lit = LoadLiteralFixed | 0xC0000000,
961 LDR_s_lit = LoadLiteralFixed | 0x04000000,
962 LDR_d_lit = LoadLiteralFixed | 0x44000000,
963 LDR_q_lit = LoadLiteralFixed | 0x84000000
964 };
965
966 #define LOAD_STORE_OP_LIST(V) \
967 V(ST, RB, w, 0x00000000), \
968 V(ST, RH, w, 0x40000000), \
969 V(ST, R, w, 0x80000000), \
970 V(ST, R, x, 0xC0000000), \
971 V(LD, RB, w, 0x00400000), \
972 V(LD, RH, w, 0x40400000), \
973 V(LD, R, w, 0x80400000), \
974 V(LD, R, x, 0xC0400000), \
975 V(LD, RSB, x, 0x00800000), \
976 V(LD, RSH, x, 0x40800000), \
977 V(LD, RSW, x, 0x80800000), \
978 V(LD, RSB, w, 0x00C00000), \
979 V(LD, RSH, w, 0x40C00000), \
980 V(ST, R, b, 0x04000000), \
981 V(ST, R, h, 0x44000000), \
982 V(ST, R, s, 0x84000000), \
983 V(ST, R, d, 0xC4000000), \
984 V(ST, R, q, 0x04800000), \
985 V(LD, R, b, 0x04400000), \
986 V(LD, R, h, 0x44400000), \
987 V(LD, R, s, 0x84400000), \
988 V(LD, R, d, 0xC4400000), \
989 V(LD, R, q, 0x04C00000)
990
991 // Load/store (post, pre, offset and unsigned.)
992 enum LoadStoreOp {
993 LoadStoreMask = 0xC4C00000,
994 LoadStoreVMask = 0x04000000,
995 #define LOAD_STORE(A, B, C, D) \
996 A##B##_##C = D
997 LOAD_STORE_OP_LIST(LOAD_STORE),
998 #undef LOAD_STORE
999 PRFM = 0xC0800000
1000 };
1001
1002 // Load/store unscaled offset.
1003 enum LoadStoreUnscaledOffsetOp {
1004 LoadStoreUnscaledOffsetFixed = 0x38000000,
1005 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
1006 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
1007 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM,
1008 #define LOAD_STORE_UNSCALED(A, B, C, D) \
1009 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
1010 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
1011 #undef LOAD_STORE_UNSCALED
1012 };
1013
1014 // Load/store post index.
1015 enum LoadStorePostIndex {
1016 LoadStorePostIndexFixed = 0x38000400,
1017 LoadStorePostIndexFMask = 0x3B200C00,
1018 LoadStorePostIndexMask = 0xFFE00C00,
1019 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
1020 A##B##_##C##_post = LoadStorePostIndexFixed | D
1021 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
1022 #undef LOAD_STORE_POST_INDEX
1023 };
1024
1025 // Load/store pre index.
1026 enum LoadStorePreIndex {
1027 LoadStorePreIndexFixed = 0x38000C00,
1028 LoadStorePreIndexFMask = 0x3B200C00,
1029 LoadStorePreIndexMask = 0xFFE00C00,
1030 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
1031 A##B##_##C##_pre = LoadStorePreIndexFixed | D
1032 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
1033 #undef LOAD_STORE_PRE_INDEX
1034 };
1035
1036 // Load/store unsigned offset.
1037 enum LoadStoreUnsignedOffset {
1038 LoadStoreUnsignedOffsetFixed = 0x39000000,
1039 LoadStoreUnsignedOffsetFMask = 0x3B000000,
1040 LoadStoreUnsignedOffsetMask = 0xFFC00000,
1041 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
1042 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
1043 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
1044 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
1045 #undef LOAD_STORE_UNSIGNED_OFFSET
1046 };
1047
1048 // Load/store register offset.
1049 enum LoadStoreRegisterOffset {
1050 LoadStoreRegisterOffsetFixed = 0x38200800,
1051 LoadStoreRegisterOffsetFMask = 0x3B200C00,
1052 LoadStoreRegisterOffsetMask = 0xFFE00C00,
1053 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
1054 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
1055 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
1056 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
1057 #undef LOAD_STORE_REGISTER_OFFSET
1058 };
1059
1060 enum LoadStoreExclusive {
1061 LoadStoreExclusiveFixed = 0x08000000,
1062 LoadStoreExclusiveFMask = 0x3F000000,
1063 LoadStoreExclusiveMask = 0xFFE08000,
1064 STXRB_w = LoadStoreExclusiveFixed | 0x00000000,
1065 STXRH_w = LoadStoreExclusiveFixed | 0x40000000,
1066 STXR_w = LoadStoreExclusiveFixed | 0x80000000,
1067 STXR_x = LoadStoreExclusiveFixed | 0xC0000000,
1068 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000,
1069 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000,
1070 LDXR_w = LoadStoreExclusiveFixed | 0x80400000,
1071 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000,
1072 STXP_w = LoadStoreExclusiveFixed | 0x80200000,
1073 STXP_x = LoadStoreExclusiveFixed | 0xC0200000,
1074 LDXP_w = LoadStoreExclusiveFixed | 0x80600000,
1075 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000,
1076 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
1077 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
1078 STLXR_w = LoadStoreExclusiveFixed | 0x80008000,
1079 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000,
1080 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
1081 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
1082 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000,
1083 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000,
1084 STLXP_w = LoadStoreExclusiveFixed | 0x80208000,
1085 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000,
1086 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000,
1087 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000,
1088 STLRB_w = LoadStoreExclusiveFixed | 0x00808000,
1089 STLRH_w = LoadStoreExclusiveFixed | 0x40808000,
1090 STLR_w = LoadStoreExclusiveFixed | 0x80808000,
1091 STLR_x = LoadStoreExclusiveFixed | 0xC0808000,
1092 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000,
1093 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000,
1094 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000,
1095 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000,
1096
1097 // v8.1 Load/store LORegion ops
1098 STLLRB = LoadStoreExclusiveFixed | 0x00800000,
1099 LDLARB = LoadStoreExclusiveFixed | 0x00C00000,
1100 STLLRH = LoadStoreExclusiveFixed | 0x40800000,
1101 LDLARH = LoadStoreExclusiveFixed | 0x40C00000,
1102 STLLR_w = LoadStoreExclusiveFixed | 0x80800000,
1103 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000,
1104 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000,
1105 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000,
1106
1107 // v8.1 Load/store exclusive ops
1108 LSEBit_l = 0x00400000,
1109 LSEBit_o0 = 0x00008000,
1110 LSEBit_sz = 0x40000000,
1111 CASFixed = LoadStoreExclusiveFixed | 0x80A00000,
1112 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000,
1113 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000,
1114 CASPFixed = LoadStoreExclusiveFixed | 0x00200000,
1115 CAS_w = CASFixed,
1116 CAS_x = CASFixed | LSEBit_sz,
1117 CASA_w = CASFixed | LSEBit_l,
1118 CASA_x = CASFixed | LSEBit_l | LSEBit_sz,
1119 CASL_w = CASFixed | LSEBit_o0,
1120 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz,
1121 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0,
1122 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz,
1123 CASB = CASBFixed,
1124 CASAB = CASBFixed | LSEBit_l,
1125 CASLB = CASBFixed | LSEBit_o0,
1126 CASALB = CASBFixed | LSEBit_l | LSEBit_o0,
1127 CASH = CASHFixed,
1128 CASAH = CASHFixed | LSEBit_l,
1129 CASLH = CASHFixed | LSEBit_o0,
1130 CASALH = CASHFixed | LSEBit_l | LSEBit_o0,
1131 CASP_w = CASPFixed,
1132 CASP_x = CASPFixed | LSEBit_sz,
1133 CASPA_w = CASPFixed | LSEBit_l,
1134 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz,
1135 CASPL_w = CASPFixed | LSEBit_o0,
1136 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz,
1137 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0,
1138 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz
1139 };
1140
1141 // Load/store RCpc unscaled offset.
1142 enum LoadStoreRCpcUnscaledOffsetOp {
1143 LoadStoreRCpcUnscaledOffsetFixed = 0x19000000,
1144 LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00,
1145 LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00,
1146 STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000,
1147 LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000,
1148 LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000,
1149 LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000,
1150 STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000,
1151 LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000,
1152 LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000,
1153 LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000,
1154 STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000,
1155 LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000,
1156 LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000,
1157 STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000,
1158 LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000
1159 };
1160
1161 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \
1162 V(LDADD, 0x00000000), \
1163 V(LDCLR, 0x00001000), \
1164 V(LDEOR, 0x00002000), \
1165 V(LDSET, 0x00003000), \
1166 V(LDSMAX, 0x00004000), \
1167 V(LDSMIN, 0x00005000), \
1168 V(LDUMAX, 0x00006000), \
1169 V(LDUMIN, 0x00007000)
1170
1171 // Atomic memory.
1172 enum AtomicMemoryOp {
1173 AtomicMemoryFixed = 0x38200000,
1174 AtomicMemoryFMask = 0x3B200C00,
1175 AtomicMemoryMask = 0xFFE0FC00,
1176 SWPB = AtomicMemoryFixed | 0x00008000,
1177 SWPAB = AtomicMemoryFixed | 0x00808000,
1178 SWPLB = AtomicMemoryFixed | 0x00408000,
1179 SWPALB = AtomicMemoryFixed | 0x00C08000,
1180 SWPH = AtomicMemoryFixed | 0x40008000,
1181 SWPAH = AtomicMemoryFixed | 0x40808000,
1182 SWPLH = AtomicMemoryFixed | 0x40408000,
1183 SWPALH = AtomicMemoryFixed | 0x40C08000,
1184 SWP_w = AtomicMemoryFixed | 0x80008000,
1185 SWPA_w = AtomicMemoryFixed | 0x80808000,
1186 SWPL_w = AtomicMemoryFixed | 0x80408000,
1187 SWPAL_w = AtomicMemoryFixed | 0x80C08000,
1188 SWP_x = AtomicMemoryFixed | 0xC0008000,
1189 SWPA_x = AtomicMemoryFixed | 0xC0808000,
1190 SWPL_x = AtomicMemoryFixed | 0xC0408000,
1191 SWPAL_x = AtomicMemoryFixed | 0xC0C08000,
1192 LDAPRB = AtomicMemoryFixed | 0x0080C000,
1193 LDAPRH = AtomicMemoryFixed | 0x4080C000,
1194 LDAPR_w = AtomicMemoryFixed | 0x8080C000,
1195 LDAPR_x = AtomicMemoryFixed | 0xC080C000,
1196
1197 AtomicMemorySimpleFMask = 0x3B208C00,
1198 AtomicMemorySimpleOpMask = 0x00007000,
1199 #define ATOMIC_MEMORY_SIMPLE(N, OP) \
1200 N##Op = OP, \
1201 N##B = AtomicMemoryFixed | OP, \
1202 N##AB = AtomicMemoryFixed | OP | 0x00800000, \
1203 N##LB = AtomicMemoryFixed | OP | 0x00400000, \
1204 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \
1205 N##H = AtomicMemoryFixed | OP | 0x40000000, \
1206 N##AH = AtomicMemoryFixed | OP | 0x40800000, \
1207 N##LH = AtomicMemoryFixed | OP | 0x40400000, \
1208 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \
1209 N##_w = AtomicMemoryFixed | OP | 0x80000000, \
1210 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \
1211 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \
1212 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \
1213 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \
1214 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \
1215 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \
1216 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000
1217
1218 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE)
1219 #undef ATOMIC_MEMORY_SIMPLE
1220 };
1221
1222 // Conditional compare.
1223 enum ConditionalCompareOp {
1224 ConditionalCompareMask = 0x60000000,
1225 CCMN = 0x20000000,
1226 CCMP = 0x60000000
1227 };
1228
1229 // Conditional compare register.
1230 enum ConditionalCompareRegisterOp {
1231 ConditionalCompareRegisterFixed = 0x1A400000,
1232 ConditionalCompareRegisterFMask = 0x1FE00800,
1233 ConditionalCompareRegisterMask = 0xFFE00C10,
1234 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1235 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1236 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1237 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1238 };
1239
1240 // Conditional compare immediate.
1241 enum ConditionalCompareImmediateOp {
1242 ConditionalCompareImmediateFixed = 0x1A400800,
1243 ConditionalCompareImmediateFMask = 0x1FE00800,
1244 ConditionalCompareImmediateMask = 0xFFE00C10,
1245 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1246 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1247 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1248 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1249 };
1250
1251 // Conditional select.
1252 enum ConditionalSelectOp {
1253 ConditionalSelectFixed = 0x1A800000,
1254 ConditionalSelectFMask = 0x1FE00000,
1255 ConditionalSelectMask = 0xFFE00C00,
1256 CSEL_w = ConditionalSelectFixed | 0x00000000,
1257 CSEL_x = ConditionalSelectFixed | 0x80000000,
1258 CSEL = CSEL_w,
1259 CSINC_w = ConditionalSelectFixed | 0x00000400,
1260 CSINC_x = ConditionalSelectFixed | 0x80000400,
1261 CSINC = CSINC_w,
1262 CSINV_w = ConditionalSelectFixed | 0x40000000,
1263 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1264 CSINV = CSINV_w,
1265 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1266 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1267 CSNEG = CSNEG_w
1268 };
1269
1270 // Data processing 1 source.
1271 enum DataProcessing1SourceOp {
1272 DataProcessing1SourceFixed = 0x5AC00000,
1273 DataProcessing1SourceFMask = 0x5FE00000,
1274 DataProcessing1SourceMask = 0xFFFFFC00,
1275 RBIT = DataProcessing1SourceFixed | 0x00000000,
1276 RBIT_w = RBIT,
1277 RBIT_x = RBIT | SixtyFourBits,
1278 REV16 = DataProcessing1SourceFixed | 0x00000400,
1279 REV16_w = REV16,
1280 REV16_x = REV16 | SixtyFourBits,
1281 REV = DataProcessing1SourceFixed | 0x00000800,
1282 REV_w = REV,
1283 REV32_x = REV | SixtyFourBits,
1284 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1285 CLZ = DataProcessing1SourceFixed | 0x00001000,
1286 CLZ_w = CLZ,
1287 CLZ_x = CLZ | SixtyFourBits,
1288 CLS = DataProcessing1SourceFixed | 0x00001400,
1289 CLS_w = CLS,
1290 CLS_x = CLS | SixtyFourBits,
1291
1292 // Pointer authentication instructions in Armv8.3.
1293 PACIA = DataProcessing1SourceFixed | 0x80010000,
1294 PACIB = DataProcessing1SourceFixed | 0x80010400,
1295 PACDA = DataProcessing1SourceFixed | 0x80010800,
1296 PACDB = DataProcessing1SourceFixed | 0x80010C00,
1297 AUTIA = DataProcessing1SourceFixed | 0x80011000,
1298 AUTIB = DataProcessing1SourceFixed | 0x80011400,
1299 AUTDA = DataProcessing1SourceFixed | 0x80011800,
1300 AUTDB = DataProcessing1SourceFixed | 0x80011C00,
1301 PACIZA = DataProcessing1SourceFixed | 0x80012000,
1302 PACIZB = DataProcessing1SourceFixed | 0x80012400,
1303 PACDZA = DataProcessing1SourceFixed | 0x80012800,
1304 PACDZB = DataProcessing1SourceFixed | 0x80012C00,
1305 AUTIZA = DataProcessing1SourceFixed | 0x80013000,
1306 AUTIZB = DataProcessing1SourceFixed | 0x80013400,
1307 AUTDZA = DataProcessing1SourceFixed | 0x80013800,
1308 AUTDZB = DataProcessing1SourceFixed | 0x80013C00,
1309 XPACI = DataProcessing1SourceFixed | 0x80014000,
1310 XPACD = DataProcessing1SourceFixed | 0x80014400
1311 };
1312
1313 // Data processing 2 source.
1314 enum DataProcessing2SourceOp {
1315 DataProcessing2SourceFixed = 0x1AC00000,
1316 DataProcessing2SourceFMask = 0x5FE00000,
1317 DataProcessing2SourceMask = 0xFFE0FC00,
1318 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1319 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1320 UDIV = UDIV_w,
1321 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1322 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1323 SDIV = SDIV_w,
1324 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1325 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1326 LSLV = LSLV_w,
1327 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1328 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1329 LSRV = LSRV_w,
1330 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1331 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1332 ASRV = ASRV_w,
1333 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1334 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1335 RORV = RORV_w,
1336 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000,
1337 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1338 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1339 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1340 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1341 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1342 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1343 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1344 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1345 };
1346
1347 // Data processing 3 source.
1348 enum DataProcessing3SourceOp {
1349 DataProcessing3SourceFixed = 0x1B000000,
1350 DataProcessing3SourceFMask = 0x1F000000,
1351 DataProcessing3SourceMask = 0xFFE08000,
1352 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1353 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1354 MADD = MADD_w,
1355 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1356 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1357 MSUB = MSUB_w,
1358 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1359 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1360 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1361 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1362 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1363 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1364 };
1365
1366 // Floating point compare.
1367 enum FPCompareOp {
1368 FPCompareFixed = 0x1E202000,
1369 FPCompareFMask = 0x5F203C00,
1370 FPCompareMask = 0xFFE0FC1F,
1371 FCMP_h = FPCompareFixed | FP16 | 0x00000000,
1372 FCMP_s = FPCompareFixed | 0x00000000,
1373 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1374 FCMP = FCMP_s,
1375 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008,
1376 FCMP_s_zero = FPCompareFixed | 0x00000008,
1377 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1378 FCMP_zero = FCMP_s_zero,
1379 FCMPE_h = FPCompareFixed | FP16 | 0x00000010,
1380 FCMPE_s = FPCompareFixed | 0x00000010,
1381 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1382 FCMPE = FCMPE_s,
1383 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018,
1384 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1385 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1386 FCMPE_zero = FCMPE_s_zero
1387 };
1388
1389 // Floating point conditional compare.
1390 enum FPConditionalCompareOp {
1391 FPConditionalCompareFixed = 0x1E200400,
1392 FPConditionalCompareFMask = 0x5F200C00,
1393 FPConditionalCompareMask = 0xFFE00C10,
1394 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000,
1395 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1396 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1397 FCCMP = FCCMP_s,
1398 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010,
1399 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1400 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1401 FCCMPE = FCCMPE_s
1402 };
1403
1404 // Floating point conditional select.
1405 enum FPConditionalSelectOp {
1406 FPConditionalSelectFixed = 0x1E200C00,
1407 FPConditionalSelectFMask = 0x5F200C00,
1408 FPConditionalSelectMask = 0xFFE00C00,
1409 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000,
1410 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1411 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1412 FCSEL = FCSEL_s
1413 };
1414
1415 // Floating point immediate.
1416 enum FPImmediateOp {
1417 FPImmediateFixed = 0x1E201000,
1418 FPImmediateFMask = 0x5F201C00,
1419 FPImmediateMask = 0xFFE01C00,
1420 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000,
1421 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1422 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1423 };
1424
1425 // Floating point data processing 1 source.
1426 enum FPDataProcessing1SourceOp {
1427 FPDataProcessing1SourceFixed = 0x1E204000,
1428 FPDataProcessing1SourceFMask = 0x5F207C00,
1429 FPDataProcessing1SourceMask = 0xFFFFFC00,
1430 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000,
1431 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1432 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1433 FMOV = FMOV_s,
1434 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000,
1435 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1436 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1437 FABS = FABS_s,
1438 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000,
1439 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1440 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1441 FNEG = FNEG_s,
1442 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000,
1443 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1444 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1445 FSQRT = FSQRT_s,
1446 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1447 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1448 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1449 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1450 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1451 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1452 FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000,
1453 FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000,
1454 FRINT32X = FRINT32X_s,
1455 FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000,
1456 FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000,
1457 FRINT32Z = FRINT32Z_s,
1458 FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000,
1459 FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000,
1460 FRINT64X = FRINT64X_s,
1461 FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000,
1462 FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000,
1463 FRINT64Z = FRINT64Z_s,
1464 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000,
1465 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1466 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1467 FRINTN = FRINTN_s,
1468 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000,
1469 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1470 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1471 FRINTP = FRINTP_s,
1472 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000,
1473 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1474 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1475 FRINTM = FRINTM_s,
1476 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000,
1477 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1478 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1479 FRINTZ = FRINTZ_s,
1480 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000,
1481 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1482 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1483 FRINTA = FRINTA_s,
1484 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000,
1485 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1486 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1487 FRINTX = FRINTX_s,
1488 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000,
1489 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1490 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1491 FRINTI = FRINTI_s
1492 };
1493
1494 // Floating point data processing 2 source.
1495 enum FPDataProcessing2SourceOp {
1496 FPDataProcessing2SourceFixed = 0x1E200800,
1497 FPDataProcessing2SourceFMask = 0x5F200C00,
1498 FPDataProcessing2SourceMask = 0xFFE0FC00,
1499 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1500 FMUL_h = FMUL | FP16,
1501 FMUL_s = FMUL,
1502 FMUL_d = FMUL | FP64,
1503 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1504 FDIV_h = FDIV | FP16,
1505 FDIV_s = FDIV,
1506 FDIV_d = FDIV | FP64,
1507 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1508 FADD_h = FADD | FP16,
1509 FADD_s = FADD,
1510 FADD_d = FADD | FP64,
1511 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1512 FSUB_h = FSUB | FP16,
1513 FSUB_s = FSUB,
1514 FSUB_d = FSUB | FP64,
1515 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1516 FMAX_h = FMAX | FP16,
1517 FMAX_s = FMAX,
1518 FMAX_d = FMAX | FP64,
1519 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1520 FMIN_h = FMIN | FP16,
1521 FMIN_s = FMIN,
1522 FMIN_d = FMIN | FP64,
1523 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1524 FMAXNM_h = FMAXNM | FP16,
1525 FMAXNM_s = FMAXNM,
1526 FMAXNM_d = FMAXNM | FP64,
1527 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1528 FMINNM_h = FMINNM | FP16,
1529 FMINNM_s = FMINNM,
1530 FMINNM_d = FMINNM | FP64,
1531 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1532 FNMUL_h = FNMUL | FP16,
1533 FNMUL_s = FNMUL,
1534 FNMUL_d = FNMUL | FP64
1535 };
1536
1537 // Floating point data processing 3 source.
1538 enum FPDataProcessing3SourceOp {
1539 FPDataProcessing3SourceFixed = 0x1F000000,
1540 FPDataProcessing3SourceFMask = 0x5F000000,
1541 FPDataProcessing3SourceMask = 0xFFE08000,
1542 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000,
1543 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000,
1544 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000,
1545 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000,
1546 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1547 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1548 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1549 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1550 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1551 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1552 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1553 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1554 };
1555
1556 // Conversion between floating point and integer.
1557 enum FPIntegerConvertOp {
1558 FPIntegerConvertFixed = 0x1E200000,
1559 FPIntegerConvertFMask = 0x5F20FC00,
1560 FPIntegerConvertMask = 0xFFFFFC00,
1561 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1562 FCVTNS_wh = FCVTNS | FP16,
1563 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16,
1564 FCVTNS_ws = FCVTNS,
1565 FCVTNS_xs = FCVTNS | SixtyFourBits,
1566 FCVTNS_wd = FCVTNS | FP64,
1567 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1568 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1569 FCVTNU_wh = FCVTNU | FP16,
1570 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16,
1571 FCVTNU_ws = FCVTNU,
1572 FCVTNU_xs = FCVTNU | SixtyFourBits,
1573 FCVTNU_wd = FCVTNU | FP64,
1574 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1575 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1576 FCVTPS_wh = FCVTPS | FP16,
1577 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16,
1578 FCVTPS_ws = FCVTPS,
1579 FCVTPS_xs = FCVTPS | SixtyFourBits,
1580 FCVTPS_wd = FCVTPS | FP64,
1581 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1582 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1583 FCVTPU_wh = FCVTPU | FP16,
1584 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16,
1585 FCVTPU_ws = FCVTPU,
1586 FCVTPU_xs = FCVTPU | SixtyFourBits,
1587 FCVTPU_wd = FCVTPU | FP64,
1588 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1589 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1590 FCVTMS_wh = FCVTMS | FP16,
1591 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16,
1592 FCVTMS_ws = FCVTMS,
1593 FCVTMS_xs = FCVTMS | SixtyFourBits,
1594 FCVTMS_wd = FCVTMS | FP64,
1595 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1596 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1597 FCVTMU_wh = FCVTMU | FP16,
1598 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16,
1599 FCVTMU_ws = FCVTMU,
1600 FCVTMU_xs = FCVTMU | SixtyFourBits,
1601 FCVTMU_wd = FCVTMU | FP64,
1602 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1603 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1604 FCVTZS_wh = FCVTZS | FP16,
1605 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16,
1606 FCVTZS_ws = FCVTZS,
1607 FCVTZS_xs = FCVTZS | SixtyFourBits,
1608 FCVTZS_wd = FCVTZS | FP64,
1609 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1610 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1611 FCVTZU_wh = FCVTZU | FP16,
1612 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16,
1613 FCVTZU_ws = FCVTZU,
1614 FCVTZU_xs = FCVTZU | SixtyFourBits,
1615 FCVTZU_wd = FCVTZU | FP64,
1616 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1617 SCVTF = FPIntegerConvertFixed | 0x00020000,
1618 SCVTF_hw = SCVTF | FP16,
1619 SCVTF_hx = SCVTF | SixtyFourBits | FP16,
1620 SCVTF_sw = SCVTF,
1621 SCVTF_sx = SCVTF | SixtyFourBits,
1622 SCVTF_dw = SCVTF | FP64,
1623 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1624 UCVTF = FPIntegerConvertFixed | 0x00030000,
1625 UCVTF_hw = UCVTF | FP16,
1626 UCVTF_hx = UCVTF | SixtyFourBits | FP16,
1627 UCVTF_sw = UCVTF,
1628 UCVTF_sx = UCVTF | SixtyFourBits,
1629 UCVTF_dw = UCVTF | FP64,
1630 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1631 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1632 FCVTAS_wh = FCVTAS | FP16,
1633 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16,
1634 FCVTAS_ws = FCVTAS,
1635 FCVTAS_xs = FCVTAS | SixtyFourBits,
1636 FCVTAS_wd = FCVTAS | FP64,
1637 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1638 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1639 FCVTAU_wh = FCVTAU | FP16,
1640 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16,
1641 FCVTAU_ws = FCVTAU,
1642 FCVTAU_xs = FCVTAU | SixtyFourBits,
1643 FCVTAU_wd = FCVTAU | FP64,
1644 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1645 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16,
1646 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16,
1647 FMOV_xh = FMOV_wh | SixtyFourBits,
1648 FMOV_hx = FMOV_hw | SixtyFourBits,
1649 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1650 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1651 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1652 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1653 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1654 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000,
1655 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000
1656 };
1657
1658 // Conversion between fixed point and floating point.
1659 enum FPFixedPointConvertOp {
1660 FPFixedPointConvertFixed = 0x1E000000,
1661 FPFixedPointConvertFMask = 0x5F200000,
1662 FPFixedPointConvertMask = 0xFFFF0000,
1663 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1664 FCVTZS_wh_fixed = FCVTZS_fixed | FP16,
1665 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16,
1666 FCVTZS_ws_fixed = FCVTZS_fixed,
1667 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1668 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1669 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1670 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1671 FCVTZU_wh_fixed = FCVTZU_fixed | FP16,
1672 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16,
1673 FCVTZU_ws_fixed = FCVTZU_fixed,
1674 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1675 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1676 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1677 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1678 SCVTF_hw_fixed = SCVTF_fixed | FP16,
1679 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16,
1680 SCVTF_sw_fixed = SCVTF_fixed,
1681 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1682 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1683 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1684 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1685 UCVTF_hw_fixed = UCVTF_fixed | FP16,
1686 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16,
1687 UCVTF_sw_fixed = UCVTF_fixed,
1688 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1689 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1690 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1691 };
1692
1693 // Crypto - two register SHA.
1694 enum Crypto2RegSHAOp {
1695 Crypto2RegSHAFixed = 0x5E280800,
1696 Crypto2RegSHAFMask = 0xFF3E0C00
1697 };
1698
1699 // Crypto - three register SHA.
1700 enum Crypto3RegSHAOp {
1701 Crypto3RegSHAFixed = 0x5E000000,
1702 Crypto3RegSHAFMask = 0xFF208C00
1703 };
1704
1705 // Crypto - AES.
1706 enum CryptoAESOp {
1707 CryptoAESFixed = 0x4E280800,
1708 CryptoAESFMask = 0xFF3E0C00
1709 };
1710
1711 // NEON instructions with two register operands.
1712 enum NEON2RegMiscOp {
1713 NEON2RegMiscFixed = 0x0E200800,
1714 NEON2RegMiscFMask = 0x9F3E0C00,
1715 NEON2RegMiscMask = 0xBF3FFC00,
1716 NEON2RegMiscUBit = 0x20000000,
1717 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1718 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1719 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1720 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1721 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1722 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1723 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1724 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1725 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1726 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1727 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1728 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1729 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1730 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1731 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1732 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1733 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1734 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1735 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1736 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1737 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1738 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1739 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1740 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1741 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1742 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1743 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1744
1745 NEON2RegMiscOpcode = 0x0001F000,
1746 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1747 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1748 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1749 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1750
1751 // These instructions use only one bit of the size field. The other bit is
1752 // used to distinguish between instructions.
1753 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1754 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1755 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1756 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1757 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1758 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1759 NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000,
1760 NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000,
1761 NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000,
1762 NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000,
1763 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1764 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1765 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1766 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1767 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1768 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1769 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1770 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1771 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1772 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1773 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1774 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1775 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1776 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1777 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1778 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1779 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1780 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1781 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1782 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1783 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1784 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1785 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1786 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1787 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1788 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1789 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1790 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1791 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1792
1793 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1794 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1795 };
1796
1797 // NEON instructions with two register operands (FP16).
1798 enum NEON2RegMiscFP16Op {
1799 NEON2RegMiscFP16Fixed = 0x0E780800,
1800 NEON2RegMiscFP16FMask = 0x9F7E0C00,
1801 NEON2RegMiscFP16Mask = 0xBFFFFC00,
1802 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000,
1803 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000,
1804 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000,
1805 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000,
1806 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000,
1807 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000,
1808 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000,
1809 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000,
1810 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000,
1811 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000,
1812 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000,
1813 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000,
1814 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000,
1815 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000,
1816 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000,
1817 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000,
1818 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000,
1819 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000,
1820 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000,
1821 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000,
1822 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000,
1823 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000,
1824 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000,
1825 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000,
1826 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000,
1827 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000,
1828 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000,
1829 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000,
1830 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000
1831 };
1832
1833 // NEON instructions with three same-type operands.
1834 enum NEON3SameOp {
1835 NEON3SameFixed = 0x0E200400,
1836 NEON3SameFMask = 0x9F200400,
1837 NEON3SameMask = 0xBF20FC00,
1838 NEON3SameUBit = 0x20000000,
1839 NEON_ADD = NEON3SameFixed | 0x00008000,
1840 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1841 NEON_SHADD = NEON3SameFixed | 0x00000000,
1842 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1843 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1844 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1845 NEON_CMGE = NEON3SameFixed | 0x00003800,
1846 NEON_CMGT = NEON3SameFixed | 0x00003000,
1847 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1848 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1849 NEON_CMTST = NEON3SameFixed | 0x00008800,
1850 NEON_MLA = NEON3SameFixed | 0x00009000,
1851 NEON_MLS = NEON3SameFixed | 0x20009000,
1852 NEON_MUL = NEON3SameFixed | 0x00009800,
1853 NEON_PMUL = NEON3SameFixed | 0x20009800,
1854 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1855 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1856 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1857 NEON_SSHL = NEON3SameFixed | 0x00004000,
1858 NEON_SMAX = NEON3SameFixed | 0x00006000,
1859 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1860 NEON_SMIN = NEON3SameFixed | 0x00006800,
1861 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1862 NEON_SABD = NEON3SameFixed | 0x00007000,
1863 NEON_SABA = NEON3SameFixed | 0x00007800,
1864 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1865 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1866 NEON_SQADD = NEON3SameFixed | 0x00000800,
1867 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1868 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1869 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1870 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1871 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1872 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1873 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1874 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1875 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1876 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1877 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1878 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1879 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1880 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1881 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1882 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1883 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1884
1885 // NEON floating point instructions with three same-type operands.
1886 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1887 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1888 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1889 NEON_FADD = NEON3SameFixed | 0x0000D000,
1890 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1891 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1892 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1893 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1894 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1895 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1896 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1897 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1898 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1899 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1900 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1901 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1902 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1903 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1904 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1905 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1906 NEON_FABD = NEON3SameFixed | 0x2080D000,
1907 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1908 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1909 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1910 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1911 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1912 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1913
1914 // NEON logical instructions with three same-type operands.
1915 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1916 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1917 NEON3SameLogicalMask = 0xBFE0FC00,
1918 NEON3SameLogicalFormatMask = NEON_Q,
1919 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1920 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1921 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1922 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1923 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1924 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1925 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1926 NEON_BSL = NEON3SameLogicalFixed | 0x20400000,
1927
1928 // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same.
1929 NEON3SameFHMMask = 0xBFE0FC00, // U size opcode
1930 NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101
1931 NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001
1932 NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101
1933 NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001
1934 };
1935
1936
1937 enum NEON3SameFP16 {
1938 NEON3SameFP16Fixed = 0x0E400400,
1939 NEON3SameFP16FMask = 0x9F60C400,
1940 NEON3SameFP16Mask = 0xBFE0FC00,
1941 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000,
1942 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800,
1943 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000,
1944 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800,
1945 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000,
1946 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000,
1947 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800,
1948 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000,
1949 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800,
1950 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000,
1951 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000,
1952 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800,
1953 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000,
1954 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000,
1955 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800,
1956 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000,
1957 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800,
1958 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000,
1959 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800,
1960 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000,
1961 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000,
1962 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000,
1963 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800,
1964 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000
1965 };
1966
1967
1968 // 'Extra' NEON instructions with three same-type operands.
1969 enum NEON3SameExtraOp {
1970 NEON3SameExtraFixed = 0x0E008400,
1971 NEON3SameExtraUBit = 0x20000000,
1972 NEON3SameExtraFMask = 0x9E208400,
1973 NEON3SameExtraMask = 0xBE20FC00,
1974 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit,
1975 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800,
1976 NEON_SDOT = NEON3SameExtraFixed | 0x00001000,
1977 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000,
1978
1979 /* v8.3 Complex Numbers */
1980 NEON3SameExtraFCFixed = 0x2E00C400,
1981 NEON3SameExtraFCFMask = 0xBF20C400,
1982 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>.
1983 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000,
1984 NEON_FCMLA = NEON3SameExtraFCFixed,
1985 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>.
1986 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800,
1987 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000
1988 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED.
1989 };
1990
1991 // NEON instructions with three different-type operands.
1992 enum NEON3DifferentOp {
1993 NEON3DifferentFixed = 0x0E200000,
1994 NEON3DifferentFMask = 0x9F200C00,
1995 NEON3DifferentMask = 0xFF20FC00,
1996 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1997 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1998 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1999 NEON_PMULL2 = NEON_PMULL | NEON_Q,
2000 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
2001 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
2002 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
2003 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
2004 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
2005 NEON_SABAL2 = NEON_SABAL | NEON_Q,
2006 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
2007 NEON_SABDL2 = NEON_SABDL | NEON_Q,
2008 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
2009 NEON_SADDL2 = NEON_SADDL | NEON_Q,
2010 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
2011 NEON_SADDW2 = NEON_SADDW | NEON_Q,
2012 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
2013 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
2014 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
2015 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
2016 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
2017 NEON_SMULL2 = NEON_SMULL | NEON_Q,
2018 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
2019 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
2020 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
2021 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
2022 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
2023 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
2024 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
2025 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
2026 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
2027 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
2028 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
2029 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
2030 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
2031 NEON_UABAL2 = NEON_UABAL | NEON_Q,
2032 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
2033 NEON_UABDL2 = NEON_UABDL | NEON_Q,
2034 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
2035 NEON_UADDL2 = NEON_UADDL | NEON_Q,
2036 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
2037 NEON_UADDW2 = NEON_UADDW | NEON_Q,
2038 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
2039 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
2040 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
2041 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
2042 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
2043 NEON_UMULL2 = NEON_UMULL | NEON_Q,
2044 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
2045 NEON_USUBL2 = NEON_USUBL | NEON_Q,
2046 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
2047 NEON_USUBW2 = NEON_USUBW | NEON_Q
2048 };
2049
2050 // NEON instructions operating across vectors.
2051 enum NEONAcrossLanesOp {
2052 NEONAcrossLanesFixed = 0x0E300800,
2053 NEONAcrossLanesFMask = 0x9F3E0C00,
2054 NEONAcrossLanesMask = 0xBF3FFC00,
2055 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
2056 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
2057 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
2058 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
2059 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
2060 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
2061 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
2062
2063 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000,
2064 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000,
2065 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000,
2066 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000,
2067 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000,
2068 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000,
2069 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000,
2070
2071 // NEON floating point across instructions.
2072 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000,
2073 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000,
2074 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000,
2075
2076 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
2077 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
2078 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
2079 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
2080 };
2081
2082 // NEON instructions with indexed element operand.
2083 enum NEONByIndexedElementOp {
2084 NEONByIndexedElementFixed = 0x0F000000,
2085 NEONByIndexedElementFMask = 0x9F000400,
2086 NEONByIndexedElementMask = 0xBF00F400,
2087 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
2088 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
2089 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
2090 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
2091 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
2092 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
2093 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
2094 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
2095 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
2096 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
2097 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
2098 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
2099 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
2100 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
2101 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000,
2102 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000,
2103 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000,
2104 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000,
2105
2106 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000,
2107 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000,
2108 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000,
2109 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000,
2110
2111 // Floating point instructions.
2112 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
2113 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
2114 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
2115 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
2116 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
2117 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000,
2118
2119 // FMLAL-like instructions.
2120 // For all cases: U = x, size = 10, opcode = xx00
2121 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000,
2122 NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000,
2123 NEONByIndexedElementFPLongMask = 0xBFC0F400,
2124 NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000,
2125 NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000,
2126 NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000,
2127 NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000,
2128
2129 // Complex instruction(s).
2130 // This is necessary because the 'rot' encoding moves into the
2131 // NEONByIndex..Mask space.
2132 NEONByIndexedElementFPComplexMask = 0xBF009400,
2133 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000
2134 };
2135
2136 // NEON register copy.
2137 enum NEONCopyOp {
2138 NEONCopyFixed = 0x0E000400,
2139 NEONCopyFMask = 0x9FE08400,
2140 NEONCopyMask = 0x3FE08400,
2141 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
2142 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
2143 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
2144 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
2145 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
2146 NEONCopySmovMask = NEONCopyMask | 0x20007800,
2147 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
2148 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
2149 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
2150 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
2151 NEON_SMOV = NEONCopyFixed | 0x00002800,
2152 NEON_UMOV = NEONCopyFixed | 0x00003800
2153 };
2154
2155 // NEON extract.
2156 enum NEONExtractOp {
2157 NEONExtractFixed = 0x2E000000,
2158 NEONExtractFMask = 0xBF208400,
2159 NEONExtractMask = 0xBFE08400,
2160 NEON_EXT = NEONExtractFixed | 0x00000000
2161 };
2162
2163 enum NEONLoadStoreMultiOp {
2164 NEONLoadStoreMultiL = 0x00400000,
2165 NEONLoadStoreMulti1_1v = 0x00007000,
2166 NEONLoadStoreMulti1_2v = 0x0000A000,
2167 NEONLoadStoreMulti1_3v = 0x00006000,
2168 NEONLoadStoreMulti1_4v = 0x00002000,
2169 NEONLoadStoreMulti2 = 0x00008000,
2170 NEONLoadStoreMulti3 = 0x00004000,
2171 NEONLoadStoreMulti4 = 0x00000000
2172 };
2173
2174 // NEON load/store multiple structures.
2175 enum NEONLoadStoreMultiStructOp {
2176 NEONLoadStoreMultiStructFixed = 0x0C000000,
2177 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
2178 NEONLoadStoreMultiStructMask = 0xBFFFF000,
2179 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
2180 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed |
2181 NEONLoadStoreMultiL,
2182 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
2183 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
2184 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
2185 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
2186 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
2187 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
2188 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
2189 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
2190 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
2191 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
2192 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
2193 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
2194 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
2195 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
2196 };
2197
2198 // NEON load/store multiple structures with post-index addressing.
2199 enum NEONLoadStoreMultiStructPostIndexOp {
2200 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
2201 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
2202 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
2203 NEONLoadStoreMultiStructPostIndex = 0x00800000,
2204 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
2205 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
2206 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
2207 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
2208 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
2209 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
2210 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
2211 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
2212 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
2213 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
2214 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
2215 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
2216 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
2217 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
2218 };
2219
2220 enum NEONLoadStoreSingleOp {
2221 NEONLoadStoreSingle1 = 0x00000000,
2222 NEONLoadStoreSingle2 = 0x00200000,
2223 NEONLoadStoreSingle3 = 0x00002000,
2224 NEONLoadStoreSingle4 = 0x00202000,
2225 NEONLoadStoreSingleL = 0x00400000,
2226 NEONLoadStoreSingle_b = 0x00000000,
2227 NEONLoadStoreSingle_h = 0x00004000,
2228 NEONLoadStoreSingle_s = 0x00008000,
2229 NEONLoadStoreSingle_d = 0x00008400,
2230 NEONLoadStoreSingleAllLanes = 0x0000C000,
2231 NEONLoadStoreSingleLenMask = 0x00202000
2232 };
2233
2234 // NEON load/store single structure.
2235 enum NEONLoadStoreSingleStructOp {
2236 NEONLoadStoreSingleStructFixed = 0x0D000000,
2237 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
2238 NEONLoadStoreSingleStructMask = 0xBFFFE000,
2239 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
2240 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed |
2241 NEONLoadStoreSingleL,
2242 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
2243 NEONLoadStoreSingleStructLoad,
2244 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
2245 NEONLoadStoreSingleStructLoad,
2246 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
2247 NEONLoadStoreSingleStructLoad,
2248 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
2249 NEONLoadStoreSingleStructLoad,
2250 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
2251 NEONLoadStoreSingleStructFixed,
2252 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
2253 NEONLoadStoreSingleStructFixed,
2254 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
2255 NEONLoadStoreSingleStructFixed,
2256 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
2257 NEONLoadStoreSingleStructFixed,
2258 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
2259 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
2260 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
2261 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
2262 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
2263 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
2264 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
2265 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
2266 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
2267
2268 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
2269 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
2270 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
2271 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
2272 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
2273 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
2274 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
2275 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
2276 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
2277
2278 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
2279 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
2280 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
2281 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
2282 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
2283 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
2284 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
2285 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
2286 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
2287
2288 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
2289 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
2290 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
2291 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
2292 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
2293 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
2294 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
2295 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
2296 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
2297 };
2298
2299 // NEON load/store single structure with post-index addressing.
2300 enum NEONLoadStoreSingleStructPostIndexOp {
2301 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
2302 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
2303 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
2304 NEONLoadStoreSingleStructPostIndex = 0x00800000,
2305 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
2306 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
2307 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
2308 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
2309 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
2310 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
2311 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
2312 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
2313 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
2314
2315 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
2316 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
2317 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
2318 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
2319 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
2320 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
2321 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
2322 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
2323 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
2324
2325 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
2326 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
2327 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
2328 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
2329 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
2330 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
2331 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
2332 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
2333 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
2334
2335 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
2336 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
2337 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
2338 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
2339 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
2340 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
2341 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
2342 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
2343 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
2344 };
2345
2346 // NEON modified immediate.
2347 enum NEONModifiedImmediateOp {
2348 NEONModifiedImmediateFixed = 0x0F000400,
2349 NEONModifiedImmediateFMask = 0x9FF80400,
2350 NEONModifiedImmediateOpBit = 0x20000000,
2351 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800,
2352 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
2353 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
2354 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
2355 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
2356 };
2357
2358 // NEON shift immediate.
2359 enum NEONShiftImmediateOp {
2360 NEONShiftImmediateFixed = 0x0F000400,
2361 NEONShiftImmediateFMask = 0x9F800400,
2362 NEONShiftImmediateMask = 0xBF80FC00,
2363 NEONShiftImmediateUBit = 0x20000000,
2364 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
2365 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
2366 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
2367 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
2368 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
2369 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
2370 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
2371 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
2372 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
2373 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
2374 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
2375 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
2376 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
2377 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
2378 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
2379 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
2380 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
2381 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
2382 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
2383 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
2384 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
2385 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
2386 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
2387 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
2388 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
2389 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
2390 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
2391 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
2392 };
2393
2394 // NEON table.
2395 enum NEONTableOp {
2396 NEONTableFixed = 0x0E000000,
2397 NEONTableFMask = 0xBF208C00,
2398 NEONTableExt = 0x00001000,
2399 NEONTableMask = 0xBF20FC00,
2400 NEON_TBL_1v = NEONTableFixed | 0x00000000,
2401 NEON_TBL_2v = NEONTableFixed | 0x00002000,
2402 NEON_TBL_3v = NEONTableFixed | 0x00004000,
2403 NEON_TBL_4v = NEONTableFixed | 0x00006000,
2404 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
2405 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
2406 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
2407 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
2408 };
2409
2410 // NEON perm.
2411 enum NEONPermOp {
2412 NEONPermFixed = 0x0E000800,
2413 NEONPermFMask = 0xBF208C00,
2414 NEONPermMask = 0x3F20FC00,
2415 NEON_UZP1 = NEONPermFixed | 0x00001000,
2416 NEON_TRN1 = NEONPermFixed | 0x00002000,
2417 NEON_ZIP1 = NEONPermFixed | 0x00003000,
2418 NEON_UZP2 = NEONPermFixed | 0x00005000,
2419 NEON_TRN2 = NEONPermFixed | 0x00006000,
2420 NEON_ZIP2 = NEONPermFixed | 0x00007000
2421 };
2422
2423 // NEON scalar instructions with two register operands.
2424 enum NEONScalar2RegMiscOp {
2425 NEONScalar2RegMiscFixed = 0x5E200800,
2426 NEONScalar2RegMiscFMask = 0xDF3E0C00,
2427 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
2428 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
2429 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
2430 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
2431 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
2432 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
2433 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
2434 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
2435 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
2436 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
2437 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2438 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2439 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2440 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2441 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2442
2443 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2444 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2445
2446 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2447 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2448 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2449 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2450 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2451 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2452 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2453 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2454 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2455 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2456 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2457 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2458 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2459 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2460 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2461 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2462 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2463 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2464 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2465 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2466 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2467 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2468 };
2469
2470 // NEON instructions with two register operands (FP16).
2471 enum NEONScalar2RegMiscFP16Op {
2472 NEONScalar2RegMiscFP16Fixed = 0x5E780800,
2473 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00,
2474 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00,
2475 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H,
2476 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H,
2477 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H,
2478 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H,
2479 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero,
2480 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero,
2481 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero,
2482 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H,
2483 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H,
2484 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H,
2485 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000,
2486 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H,
2487 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H,
2488 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H,
2489 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H,
2490 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero,
2491 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero,
2492 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H,
2493 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H,
2494 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H
2495 };
2496
2497 // NEON scalar instructions with three same-type operands.
2498 enum NEONScalar3SameOp {
2499 NEONScalar3SameFixed = 0x5E200400,
2500 NEONScalar3SameFMask = 0xDF200400,
2501 NEONScalar3SameMask = 0xFF20FC00,
2502 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2503 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2504 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2505 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2506 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2507 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2508 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2509 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2510 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2511 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2512 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2513 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2514 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2515 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2516 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2517 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2518 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2519 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2520 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2521 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2522 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2523 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2524
2525 // NEON floating point scalar instructions with three same-type operands.
2526 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2527 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2528 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2529 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2530 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2531 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2532 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2533 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2534 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2535 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2536 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2537 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2538 };
2539
2540 // NEON scalar FP16 instructions with three same-type operands.
2541 enum NEONScalar3SameFP16Op {
2542 NEONScalar3SameFP16Fixed = 0x5E400400,
2543 NEONScalar3SameFP16FMask = 0xDF60C400,
2544 NEONScalar3SameFP16Mask = 0xFFE0FC00,
2545 NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H,
2546 NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H,
2547 NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H,
2548 NEON_FCMGE_H_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H,
2549 NEON_FCMGT_H_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H,
2550 NEON_FACGE_H_scalar = NEON_Q | NEONScalar | NEON_FACGE_H,
2551 NEON_FACGT_H_scalar = NEON_Q | NEONScalar | NEON_FACGT_H,
2552 NEON_FRECPS_H_scalar = NEON_Q | NEONScalar | NEON_FRECPS_H,
2553 NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H
2554 };
2555
2556 // 'Extra' NEON scalar instructions with three same-type operands.
2557 enum NEONScalar3SameExtraOp {
2558 NEONScalar3SameExtraFixed = 0x5E008400,
2559 NEONScalar3SameExtraFMask = 0xDF208400,
2560 NEONScalar3SameExtraMask = 0xFF20FC00,
2561 NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH,
2562 NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH
2563 };
2564
2565 // NEON scalar instructions with three different-type operands.
2566 enum NEONScalar3DiffOp {
2567 NEONScalar3DiffFixed = 0x5E200000,
2568 NEONScalar3DiffFMask = 0xDF200C00,
2569 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2570 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2571 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2572 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2573 };
2574
2575 // NEON scalar instructions with indexed element operand.
2576 enum NEONScalarByIndexedElementOp {
2577 NEONScalarByIndexedElementFixed = 0x5F000000,
2578 NEONScalarByIndexedElementFMask = 0xDF000400,
2579 NEONScalarByIndexedElementMask = 0xFF00F400,
2580 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2581 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2582 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2583 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2584 NEON_SQRDMULH_byelement_scalar
2585 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2586 NEON_SQRDMLAH_byelement_scalar
2587 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement,
2588 NEON_SQRDMLSH_byelement_scalar
2589 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement,
2590 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement,
2591 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement,
2592 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement,
2593 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement,
2594
2595 // Floating point instructions.
2596 NEONScalarByIndexedElementFPFixed
2597 = NEONScalarByIndexedElementFixed | 0x00800000,
2598 NEONScalarByIndexedElementFPMask
2599 = NEONScalarByIndexedElementMask | 0x00800000,
2600 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2601 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2602 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2603 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2604 };
2605
2606 // NEON scalar register copy.
2607 enum NEONScalarCopyOp {
2608 NEONScalarCopyFixed = 0x5E000400,
2609 NEONScalarCopyFMask = 0xDFE08400,
2610 NEONScalarCopyMask = 0xFFE0FC00,
2611 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2612 };
2613
2614 // NEON scalar pairwise instructions.
2615 enum NEONScalarPairwiseOp {
2616 NEONScalarPairwiseFixed = 0x5E300800,
2617 NEONScalarPairwiseFMask = 0xDF3E0C00,
2618 NEONScalarPairwiseMask = 0xFFB1F800,
2619 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
2620 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000,
2621 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000,
2622 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000,
2623 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000,
2624 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000,
2625 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
2626 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
2627 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
2628 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
2629 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
2630 };
2631
2632 // NEON scalar shift immediate.
2633 enum NEONScalarShiftImmediateOp {
2634 NEONScalarShiftImmediateFixed = 0x5F000400,
2635 NEONScalarShiftImmediateFMask = 0xDF800400,
2636 NEONScalarShiftImmediateMask = 0xFF80FC00,
2637 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
2638 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
2639 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
2640 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
2641 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
2642 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
2643 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
2644 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
2645 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
2646 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
2647 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
2648 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
2649 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
2650 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
2651 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
2652 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
2653 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
2654 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
2655 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2656 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2657 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
2658 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
2659 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2660 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2661 };
2662
2663 enum ReservedOp {
2664 ReservedFixed = 0x00000000,
2665 ReservedFMask = 0x1E000000,
2666 ReservedMask = 0xFFFF0000,
2667
2668 UDF = ReservedFixed | 0x00000000
2669 };
2670
2671 // Unimplemented and unallocated instructions. These are defined to make fixed
2672 // bit assertion easier.
2673 enum UnimplementedOp {
2674 UnimplementedFixed = 0x00000000,
2675 UnimplementedFMask = 0x00000000
2676 };
2677
2678 enum UnallocatedOp {
2679 UnallocatedFixed = 0x00000000,
2680 UnallocatedFMask = 0x00000000
2681 };
2682
2683 // Re-enable `clang-format` after the `enum`s.
2684 // clang-format on
2685
2686 } // namespace aarch64
2687 } // namespace vixl
2688
2689 #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_
2690