1 // Copyright 2019 The Chromium OS Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // Common constants and types used for Split IRQ chip devices (e.g. PIC, PIT, IOAPIC). 6 7 use bit_field::*; 8 9 #[bitfield] 10 #[derive(Clone, Copy, Debug, PartialEq)] 11 pub enum DestinationMode { 12 Physical = 0, 13 Logical = 1, 14 } 15 16 #[bitfield] 17 #[derive(Clone, Copy, Debug, PartialEq)] 18 pub enum TriggerMode { 19 Edge = 0, 20 Level = 1, 21 } 22 23 #[bitfield] 24 #[derive(Debug, Clone, Copy, PartialEq)] 25 pub enum DeliveryMode { 26 Fixed = 0b000, 27 Lowest = 0b001, 28 SMI = 0b010, // System management interrupt 29 RemoteRead = 0b011, // This is no longer supported by intel. 30 NMI = 0b100, // Non maskable interrupt 31 Init = 0b101, 32 Startup = 0b110, 33 External = 0b111, 34 } 35 36 #[bitfield] 37 #[derive(Clone, Copy, PartialEq)] 38 pub struct MsiAddressMessage { 39 reserved: BitField2, 40 #[bits = 1] 41 destination_mode: DestinationMode, 42 redirection_hint: BitField1, 43 reserved_2: BitField8, 44 destination_id: BitField8, 45 // According to Intel's implementation of MSI, these bits must always be 0xfee. 46 always_0xfee: BitField12, 47 } 48 49 #[bitfield] 50 #[derive(Clone, Copy, PartialEq)] 51 struct MsiDataMessage { 52 vector: BitField8, 53 #[bits = 3] 54 delivery_mode: DeliveryMode, 55 reserved: BitField3, 56 level: BitField1, 57 #[bits = 1] 58 trigger: TriggerMode, 59 reserved2: BitField16, 60 } 61