| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 70 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
118 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
240 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
491 unsigned PredReg; in rewriteT2FrameIndex() local
679 unsigned &PredReg) { in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 485 unsigned PredReg) { in UpdateBaseRegUses()
625 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
824 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
892 unsigned PredReg = 0; in MergeOpsUpdate() local
1161 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1191 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1211 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
1245 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1387 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1494 unsigned PredReg; in MergeBaseUpdateLSDouble() local
[all …]
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| D | Thumb2SizeReduction.cpp | 471 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
679 unsigned PredReg = 0; in ReduceSpecial() local
782 unsigned PredReg = 0; in ReduceTo2Addr() local
875 unsigned PredReg = 0; in ReduceToNarrow() local
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| D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| D | Thumb2ITBlockPass.cpp | 206 unsigned PredReg = 0; in InsertITInstructions() local
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| D | ARMBaseRegisterInfo.cpp | 438 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
783 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| D | ARMFrameLowering.cpp | 171 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
185 unsigned PredReg = 0) { in emitSPUpdate()
2056 unsigned PredReg = TII.getFramePred(Old); in eliminateCallFramePseudoInstr() local
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
225 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
468 unsigned PredReg; in rewriteT2FrameIndex() local
638 unsigned &PredReg) { in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 460 unsigned PredReg) { in UpdateBaseRegUses()
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti()
793 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble()
860 unsigned PredReg = 0; in MergeOpsUpdate() local
1127 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement()
1157 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore()
1177 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter()
1211 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1353 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1450 unsigned PredReg; in MergeBaseUpdateLSDouble() local
[all …]
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| D | Thumb2SizeReduction.cpp | 441 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local
647 unsigned PredReg = 0; in ReduceSpecial() local
752 unsigned PredReg = 0; in ReduceTo2Addr() local
848 unsigned PredReg = 0; in ReduceToNarrow() local
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| D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| D | Thumb2ITBlockPass.cpp | 189 unsigned PredReg = 0; in InsertITInstructions() local
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| D | ARMFrameLowering.cpp | 126 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate()
140 unsigned PredReg = 0) { in emitSPUpdate()
1772 unsigned PredReg = Old.getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1777 unsigned PredReg = Old.getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
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| D | ARMBaseRegisterInfo.cpp | 414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| D | HexagonMCCompound.cpp | 182 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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| D | HexagonMCChecker.cpp | 58 unsigned PredReg = Hexagon::NoRegister; in init() local
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| D | HexagonMCChecker.h | 98 unsigned PredReg; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 68 void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, in initReg()
90 unsigned PredReg = Hexagon::NoRegister; in init() local
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| D | HexagonMCCompound.cpp | 178 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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| D | HexagonMCDuplexInfo.cpp | 186 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 302 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenPredicate.cpp | 320 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred()
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