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1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright (C) Marvell International Ltd. and its affiliates
4   */
5  
6  #ifndef _SYS_ENV_LIB_H
7  #define _SYS_ENV_LIB_H
8  
9  #include "../../../drivers/ddr/marvell/a38x/ddr3_init.h"
10  
11  /* Serdes definitions */
12  #define COMMON_PHY_BASE_ADDR		0x18300
13  
14  #define DEVICE_CONFIGURATION_REG0	0x18284
15  #define DEVICE_CONFIGURATION_REG1	0x18288
16  #define COMMON_PHY_CONFIGURATION1_REG	0x18300
17  #define COMMON_PHY_CONFIGURATION2_REG	0x18304
18  #define COMMON_PHY_CONFIGURATION4_REG	0x1830c
19  #define COMMON_PHY_STATUS1_REG		0x18318
20  #define COMMON_PHYS_SELECTORS_REG	0x183fc
21  #define SOC_CONTROL_REG1		0x18204
22  #define GENERAL_PURPOSE_RESERVED0_REG	0x182e0
23  #define GBE_CONFIGURATION_REG		0x18460
24  #define DEVICE_SAMPLE_AT_RESET1_REG	0x18600
25  #define DEVICE_SAMPLE_AT_RESET2_REG	0x18604
26  #define DEV_ID_REG			0x18238
27  
28  #define CORE_PLL_PARAMETERS_REG		0xe42e0
29  #define CORE_PLL_CONFIG_REG		0xe42e4
30  
31  #define QSGMII_CONTROL_REG1		0x18494
32  
33  #define DEV_ID_REG_DEVICE_ID_OFFS	16
34  #define DEV_ID_REG_DEVICE_ID_MASK	0xffff0000
35  
36  #define SAR_FREQ_OFFSET			10
37  #define SAR_FREQ_MASK			0x1f
38  #define SAR_DEV_ID_OFFS			27
39  #define SAR_DEV_ID_MASK			0x7
40  
41  #define POWER_AND_PLL_CTRL_REG		0xa0004
42  #define CALIBRATION_CTRL_REG		0xa0008
43  #define DFE_REG0			0xa001c
44  #define DFE_REG3			0xa0028
45  #define RESET_DFE_REG			0xa0148
46  #define LOOPBACK_REG			0xa008c
47  #define SYNC_PATTERN_REG		0xa0090
48  #define INTERFACE_REG			0xa0094
49  #define ISOLATE_REG			0xa0098
50  #define MISC_REG			0xa013c
51  #define GLUE_REG			0xa0140
52  #define GENERATION_DIVIDER_FORCE_REG	0xa0144
53  #define PCIE_REG0			0xa0120
54  #define LANE_ALIGN_REG0			0xa0124
55  #define SQUELCH_FFE_SETTING_REG		0xa0018
56  #define G1_SETTINGS_0_REG		0xa0034
57  #define G1_SETTINGS_1_REG		0xa0038
58  #define G1_SETTINGS_3_REG		0xa0440
59  #define G1_SETTINGS_4_REG		0xa0444
60  #define G2_SETTINGS_0_REG		0xa003c
61  #define G2_SETTINGS_1_REG		0xa0040
62  #define G2_SETTINGS_2_REG		0xa00f8
63  #define G2_SETTINGS_3_REG		0xa0448
64  #define G2_SETTINGS_4_REG		0xa044c
65  #define G3_SETTINGS_0_REG		0xa0044
66  #define G3_SETTINGS_1_REG		0xa0048
67  #define G3_SETTINGS_3_REG		0xa0450
68  #define G3_SETTINGS_4_REG		0xa0454
69  #define VTHIMPCAL_CTRL_REG		0xa0104
70  #define REF_REG0			0xa0134
71  #define CAL_REG6			0xa0168
72  #define RX_REG2				0xa0184
73  #define RX_REG3				0xa0188
74  #define PCIE_REG1			0xa0288
75  #define PCIE_REG3			0xa0290
76  #define LANE_CFG0_REG			0xa0600
77  #define LANE_CFG1_REG			0xa0604
78  #define LANE_CFG4_REG			0xa0620
79  #define LANE_CFG5_REG			0xa0624
80  #define GLOBAL_CLK_CTRL			0xa0704
81  #define GLOBAL_MISC_CTRL		0xa0718
82  #define GLOBAL_CLK_SRC_HI		0xa0710
83  
84  #define GLOBAL_CLK_CTRL			0xa0704
85  #define GLOBAL_MISC_CTRL		0xa0718
86  #define GLOBAL_PM_CTRL			0xa0740
87  
88  /* SATA registers */
89  #define SATA_CTRL_REG_IND_ADDR		0xa80a0
90  #define SATA_CTRL_REG_IND_DATA		0xa80a4
91  
92  #define SATA_VENDOR_PORT_0_REG_ADDR	0xa8178
93  #define SATA_VENDOR_PORT_1_REG_ADDR	0xa81f8
94  #define SATA_VENDOR_PORT_0_REG_DATA	0xa817c
95  #define SATA_VENDOR_PORT_1_REG_DATA	0xa81fc
96  
97  /* Reference clock values and mask */
98  #define POWER_AND_PLL_CTRL_REG_100MHZ_VAL	0x0
99  #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_1	0x1
100  #define POWER_AND_PLL_CTRL_REG_25MHZ_VAL_2	0x2
101  #define POWER_AND_PLL_CTRL_REG_40MHZ_VAL	0x3
102  #define GLOBAL_PM_CTRL_REG_25MHZ_VAL		0x7
103  #define GLOBAL_PM_CTRL_REG_40MHZ_VAL		0xc
104  #define LANE_CFG4_REG_25MHZ_VAL			0x200
105  #define LANE_CFG4_REG_40MHZ_VAL			0x300
106  
107  #define POWER_AND_PLL_CTRL_REG_MASK		(~(0x1f))
108  #define GLOBAL_PM_CTRL_REG_MASK			(~(0xff))
109  #define LANE_CFG4_REG_MASK			(~(0x1f00))
110  
111  #define REF_CLK_SELECTOR_VAL_PEX0(reg_val)	(reg_val >> 2) & 0x1
112  #define REF_CLK_SELECTOR_VAL_PEX1(reg_val)	(reg_val >> 3) & 0x1
113  #define REF_CLK_SELECTOR_VAL_PEX2(reg_val)	(reg_val >> 30) & 0x1
114  #define REF_CLK_SELECTOR_VAL_PEX3(reg_val)	(reg_val >> 31) & 0x1
115  #define REF_CLK_SELECTOR_VAL(reg_val)		(reg_val & 0x1)
116  
117  #define MAX_SELECTOR_VAL			10
118  
119  /* TWSI addresses */
120  /* starting from A38x A0, i2c address of EEPROM is 0x57 */
121  #ifdef CONFIG_ARMADA_39X
122  #define EEPROM_I2C_ADDR			0x50
123  #else
124  #define EEPROM_I2C_ADDR			(sys_env_device_rev_get() == \
125  					 MV_88F68XX_Z1_ID ? 0x50 : 0x57)
126  #endif
127  #define RD_GET_MODE_ADDR		0x4c
128  #define DB_GET_MODE_SLM1363_ADDR	0x25
129  #define DB_GET_MODE_SLM1364_ADDR	0x24
130  #define DB381_GET_MODE_SLM1426_1427_ADDR 0x56
131  
132  /* DB-BP Board 'SatR' mapping */
133  #define SATR_DB_LANE1_MAX_OPTIONS	7
134  #define SATR_DB_LANE1_CFG_MASK		0x7
135  #define SATR_DB_LANE1_CFG_OFFSET	0
136  #define SATR_DB_LANE2_MAX_OPTIONS	4
137  #define SATR_DB_LANE2_CFG_MASK		0x38
138  #define SATR_DB_LANE2_CFG_OFFSET	3
139  
140  /* GP Board 'SatR' mapping */
141  #define SATR_GP_LANE1_CFG_MASK		0x4
142  #define SATR_GP_LANE1_CFG_OFFSET	2
143  #define SATR_GP_LANE2_CFG_MASK		0x8
144  #define SATR_GP_LANE2_CFG_OFFSET	3
145  
146  /* For setting MPP2 and MPP3 to be TWSI mode and MPP 0,1 to UART mode */
147  #define MPP_CTRL_REG			0x18000
148  #define MPP_SET_MASK			(~(0xffff))
149  #define MPP_SET_DATA			(0x1111)
150  #define MPP_UART1_SET_MASK		(~(0xff000))
151  #define MPP_UART1_SET_DATA		(0x66000)
152  
153  #define AVS_DEBUG_CNTR_REG		0xe4124
154  #define AVS_DEBUG_CNTR_DEFAULT_VALUE	0x08008073
155  
156  #define AVS_ENABLED_CONTROL		0xe4130
157  #define AVS_LOW_VDD_LIMIT_OFFS		4
158  #define AVS_LOW_VDD_LIMIT_MASK		(0xff << AVS_LOW_VDD_LIMIT_OFFS)
159  #define AVS_LOW_VDD_LIMIT_VAL		(0x27 << AVS_LOW_VDD_LIMIT_OFFS)
160  #define AVS_LOW_VDD_SLOW_VAL		(0x23 << AVS_LOW_VDD_LIMIT_OFFS)
161  
162  #define AVS_HIGH_VDD_LIMIT_OFFS		12
163  #define AVS_HIGH_VDD_LIMIT_MASK		(0xff << AVS_HIGH_VDD_LIMIT_OFFS)
164  #define AVS_HIGH_VDD_LIMIT_VAL		(0x27 << AVS_HIGH_VDD_LIMIT_OFFS)
165  #define AVS_HIGH_VDD_SLOW_VAL		(0x23 << AVS_HIGH_VDD_LIMIT_OFFS)
166  
167  /* Board ID numbers */
168  #define MARVELL_BOARD_ID_MASK		0x10
169  /* Customer boards for A38x */
170  #define A38X_CUSTOMER_BOARD_ID_BASE	0x0
171  #define A38X_CUSTOMER_BOARD_ID0		(A38X_CUSTOMER_BOARD_ID_BASE + 0)
172  #define A38X_CUSTOMER_BOARD_ID1		(A38X_CUSTOMER_BOARD_ID_BASE + 1)
173  #define A38X_MV_MAX_CUSTOMER_BOARD_ID	(A38X_CUSTOMER_BOARD_ID_BASE + 2)
174  #define A38X_MV_CUSTOMER_BOARD_NUM	(A38X_MV_MAX_CUSTOMER_BOARD_ID - \
175  					 A38X_CUSTOMER_BOARD_ID_BASE)
176  
177  /* Marvell boards for A38x */
178  #define A38X_MARVELL_BOARD_ID_BASE	0x10
179  #define RD_NAS_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 0)
180  #define DB_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 1)
181  #define RD_AP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 2)
182  #define DB_AP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 3)
183  #define DB_GP_68XX_ID			(A38X_MARVELL_BOARD_ID_BASE + 4)
184  #define DB_BP_6821_ID			(A38X_MARVELL_BOARD_ID_BASE + 5)
185  #define DB_AMC_6820_ID			(A38X_MARVELL_BOARD_ID_BASE + 6)
186  #define A38X_MV_MAX_MARVELL_BOARD_ID	(A38X_MARVELL_BOARD_ID_BASE + 7)
187  #define A38X_MV_MARVELL_BOARD_NUM	(A38X_MV_MAX_MARVELL_BOARD_ID - \
188  					 A38X_MARVELL_BOARD_ID_BASE)
189  
190  /* Customer boards for A39x */
191  #define A39X_CUSTOMER_BOARD_ID_BASE	0x20
192  #define A39X_CUSTOMER_BOARD_ID0		(A39X_CUSTOMER_BOARD_ID_BASE + 0)
193  #define A39X_CUSTOMER_BOARD_ID1		(A39X_CUSTOMER_BOARD_ID_BASE + 1)
194  #define A39X_MV_MAX_CUSTOMER_BOARD_ID	(A39X_CUSTOMER_BOARD_ID_BASE + 2)
195  #define A39X_MV_CUSTOMER_BOARD_NUM	(A39X_MV_MAX_CUSTOMER_BOARD_ID - \
196  					 A39X_CUSTOMER_BOARD_ID_BASE)
197  
198  /* Marvell boards for A39x */
199  #define A39X_MARVELL_BOARD_ID_BASE	0x30
200  #define A39X_DB_69XX_ID			(A39X_MARVELL_BOARD_ID_BASE + 0)
201  #define A39X_RD_69XX_ID			(A39X_MARVELL_BOARD_ID_BASE + 1)
202  #define A39X_MV_MAX_MARVELL_BOARD_ID	(A39X_MARVELL_BOARD_ID_BASE + 2)
203  #define A39X_MV_MARVELL_BOARD_NUM	(A39X_MV_MAX_MARVELL_BOARD_ID - \
204  					 A39X_MARVELL_BOARD_ID_BASE)
205  
206  #ifdef CONFIG_ARMADA_38X
207  #define CUTOMER_BOARD_ID_BASE		A38X_CUSTOMER_BOARD_ID_BASE
208  #define CUSTOMER_BOARD_ID0		A38X_CUSTOMER_BOARD_ID0
209  #define CUSTOMER_BOARD_ID1		A38X_CUSTOMER_BOARD_ID1
210  #define MV_MAX_CUSTOMER_BOARD_ID	A38X_MV_MAX_CUSTOMER_BOARD_ID
211  #define MV_CUSTOMER_BOARD_NUM		A38X_MV_CUSTOMER_BOARD_NUM
212  #define MARVELL_BOARD_ID_BASE		A38X_MARVELL_BOARD_ID_BASE
213  #define MV_MAX_MARVELL_BOARD_ID		A38X_MV_MAX_MARVELL_BOARD_ID
214  #define MV_MARVELL_BOARD_NUM		A38X_MV_MARVELL_BOARD_NUM
215  #define MV_DEFAULT_BOARD_ID		DB_68XX_ID
216  #define MV_DEFAULT_DEVICE_ID		MV_6811
217  #elif defined(CONFIG_ARMADA_39X)
218  #define CUTOMER_BOARD_ID_BASE		A39X_CUSTOMER_BOARD_ID_BASE
219  #define CUSTOMER_BOARD_ID0		A39X_CUSTOMER_BOARD_ID0
220  #define CUSTOMER_BOARD_ID1		A39X_CUSTOMER_BOARD_ID1
221  #define MV_MAX_CUSTOMER_BOARD_ID	A39X_MV_MAX_CUSTOMER_BOARD_ID
222  #define MV_CUSTOMER_BOARD_NUM		A39X_MV_CUSTOMER_BOARD_NUM
223  #define MARVELL_BOARD_ID_BASE		A39X_MARVELL_BOARD_ID_BASE
224  #define MV_MAX_MARVELL_BOARD_ID		A39X_MV_MAX_MARVELL_BOARD_ID
225  #define MV_MARVELL_BOARD_NUM		A39X_MV_MARVELL_BOARD_NUM
226  #define MV_DEFAULT_BOARD_ID		A39X_DB_69XX_ID
227  #define MV_DEFAULT_DEVICE_ID		MV_6920
228  #endif
229  
230  #define MV_INVALID_BOARD_ID		0xffffffff
231  
232  /* device revesion */
233  #define DEV_VERSION_ID_REG		0x1823c
234  #define REVISON_ID_OFFS			8
235  #define REVISON_ID_MASK			0xf00
236  
237  /* A38x revisions */
238  #define MV_88F68XX_Z1_ID		0x0
239  #define MV_88F68XX_A0_ID		0x4
240  #define MV_88F68XX_B0_ID		0xa
241  /* A39x revisions */
242  #define MV_88F69XX_Z1_ID		0x2
243  
244  #define MPP_CONTROL_REG(id)		(0x18000 + (id * 4))
245  #define GPP_DATA_OUT_REG(grp)		(MV_GPP_REGS_BASE(grp) + 0x00)
246  #define GPP_DATA_OUT_EN_REG(grp)	(MV_GPP_REGS_BASE(grp) + 0x04)
247  #define GPP_DATA_IN_REG(grp)		(MV_GPP_REGS_BASE(grp) + 0x10)
248  #define MV_GPP_REGS_BASE(unit)		(0x18100 + ((unit) * 0x40))
249  
250  #define MPP_REG_NUM(GPIO_NUM)		(GPIO_NUM / 8)
251  #define MPP_MASK(GPIO_NUM)		(0xf << 4 * (GPIO_NUM - \
252  					(MPP_REG_NUM(GPIO_NUM) * 8)));
253  #define GPP_REG_NUM(GPIO_NUM)		(GPIO_NUM / 32)
254  #define GPP_MASK(GPIO_NUM)		(1 << GPIO_NUM % 32)
255  
256  /* device ID */
257  /* Armada 38x Family */
258  #define MV_6810_DEV_ID		0x6810
259  #define MV_6811_DEV_ID		0x6811
260  #define MV_6820_DEV_ID		0x6820
261  #define MV_6828_DEV_ID		0x6828
262  /* Armada 39x Family */
263  #define MV_6920_DEV_ID		0x6920
264  #define MV_6928_DEV_ID		0x6928
265  
266  enum {
267  	MV_6810,
268  	MV_6820,
269  	MV_6811,
270  	MV_6828,
271  	MV_NONE,
272  	MV_6920,
273  	MV_6928,
274  	MV_MAX_DEV_ID,
275  };
276  
277  #define MV_6820_INDEX			0
278  #define MV_6810_INDEX			1
279  #define MV_6811_INDEX			2
280  #define MV_6828_INDEX			3
281  
282  #define MV_6920_INDEX			0
283  #define MV_6928_INDEX			1
284  
285  #ifdef CONFIG_ARMADA_38X
286  #define MAX_DEV_ID_NUM			4
287  #else
288  #define MAX_DEV_ID_NUM			2
289  #endif
290  
291  #define MV_6820_INDEX			0
292  #define MV_6810_INDEX			1
293  #define MV_6811_INDEX			2
294  #define MV_6828_INDEX			3
295  #define MV_6920_INDEX			0
296  #define MV_6928_INDEX			1
297  
298  enum unit_id {
299  	PEX_UNIT_ID,
300  	ETH_GIG_UNIT_ID,
301  	USB3H_UNIT_ID,
302  	USB3D_UNIT_ID,
303  	SATA_UNIT_ID,
304  	QSGMII_UNIT_ID,
305  	XAUI_UNIT_ID,
306  	RXAUI_UNIT_ID,
307  	MAX_UNITS_ID
308  };
309  
310  struct board_wakeup_gpio {
311  	u32 board_id;
312  	int gpio_num;
313  };
314  
315  enum suspend_wakeup_status {
316  	SUSPEND_WAKEUP_DISABLED,
317  	SUSPEND_WAKEUP_ENABLED,
318  	SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED,
319  };
320  
321  /*
322   * GPIO status indication for Suspend Wakeup:
323   * If suspend to RAM is supported and GPIO inidcation is implemented,
324   * set the gpio number
325   * If suspend to RAM is supported but GPIO indication is not implemented
326   * set '-2'
327   * If suspend to RAM is not supported set '-1'
328   */
329  #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
330  #ifdef CONFIG_ARMADA_38X
331  #define MV_BOARD_WAKEUP_GPIO_INFO {		\
332  	{A38X_CUSTOMER_BOARD_ID0,	-1 },	\
333  	{A38X_CUSTOMER_BOARD_ID0,	-1 },	\
334  };
335  #else
336  #define MV_BOARD_WAKEUP_GPIO_INFO {		\
337  	{A39X_CUSTOMER_BOARD_ID0,	-1 },	\
338  	{A39X_CUSTOMER_BOARD_ID0,	-1 },	\
339  };
340  #endif /* CONFIG_ARMADA_38X */
341  
342  #else
343  
344  #ifdef CONFIG_ARMADA_38X
345  #define MV_BOARD_WAKEUP_GPIO_INFO {	\
346  	{RD_NAS_68XX_ID, -2 },		\
347  	{DB_68XX_ID,	 -1 },		\
348  	{RD_AP_68XX_ID,	 -2 },		\
349  	{DB_AP_68XX_ID,	 -2 },		\
350  	{DB_GP_68XX_ID,	 -2 },		\
351  	{DB_BP_6821_ID,	 -2 },		\
352  	{DB_AMC_6820_ID, -2 },		\
353  };
354  #else
355  #define MV_BOARD_WAKEUP_GPIO_INFO {	\
356  	{A39X_RD_69XX_ID, -1 },		\
357  	{A39X_DB_69XX_ID, -1 },		\
358  };
359  #endif /* CONFIG_ARMADA_38X */
360  #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */
361  
362  u32 mv_board_tclk_get(void);
363  u32 mv_board_id_get(void);
364  u32 mv_board_id_index_get(u32 board_id);
365  u32 sys_env_unit_max_num_get(enum unit_id unit);
366  enum suspend_wakeup_status sys_env_suspend_wakeup_check(void);
367  u8 sys_env_device_rev_get(void);
368  u32 sys_env_device_id_get(void);
369  u16 sys_env_model_get(void);
370  struct dlb_config *sys_env_dlb_config_ptr_get(void);
371  u32 sys_env_get_cs_ena_from_reg(void);
372  
373  #endif /* _SYS_ENV_LIB_H */
374