1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSS_DEF_H 8 #define CSS_DEF_H 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gic_common.h> 12 #include <drivers/arm/tzc400.h> 13 14 /************************************************************************* 15 * Definitions common to all ARM Compute SubSystems (CSS) 16 *************************************************************************/ 17 #define NSROM_BASE 0x1f000000 18 #define NSROM_SIZE 0x00001000 19 20 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 21 #define CSS_DEVICE_BASE 0x20000000 22 #define CSS_DEVICE_SIZE 0x0e000000 23 24 /* System Security Control Registers */ 25 #define SSC_REG_BASE 0x2a420000 26 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 27 28 /* System ID Registers Unit */ 29 #define SID_REG_BASE 0x2a4a0000 30 #define SID_SYSTEM_ID_OFFSET 0x40 31 #define SID_SYSTEM_CFG_OFFSET 0x70 32 33 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 34 #define CSS_NIC400_SLAVE_BOOTSECURE 8 35 36 /* Interrupt handling constants */ 37 #define CSS_IRQ_MHU 69 38 #define CSS_IRQ_GPU_SMMU_0 71 39 #define CSS_IRQ_TZC 80 40 #define CSS_IRQ_TZ_WDOG 86 41 #define CSS_IRQ_SEC_SYS_TIMER 91 42 43 /* MHU register offsets */ 44 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 45 46 /* 47 * Define a list of Group 1 Secure interrupt properties as per GICv3 48 * terminology. On a GICv2 system or mode, the interrupts will be treated as 49 * Group 0 interrupts. 50 */ 51 #define CSS_G1S_IRQ_PROPS(grp) \ 52 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 53 GIC_INTR_CFG_LEVEL), \ 54 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 55 GIC_INTR_CFG_LEVEL), \ 56 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 57 GIC_INTR_CFG_LEVEL), \ 58 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 59 GIC_INTR_CFG_LEVEL), \ 60 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 61 GIC_INTR_CFG_LEVEL) 62 63 #if CSS_USE_SCMI_SDS_DRIVER 64 /* Memory region for shared data storage */ 65 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 66 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 67 /* 68 * The SCMI Channel is placed right after the SDS region 69 */ 70 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 71 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 72 73 /* Trusted mailbox base address common to all CSS */ 74 /* If SDS is present, then mailbox is at top of SRAM */ 75 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 76 77 /* Number of retries for SCP_RAM_READY flag */ 78 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 79 80 #else 81 /* 82 * SCP <=> AP boot configuration 83 * 84 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 85 * the start of the Trusted SRAM. 86 * 87 * Note that the value stored at this address is only valid at boot time, before 88 * the SCP_BL2 image is transferred to SCP. 89 */ 90 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 91 92 /* Trusted mailbox base address common to all CSS */ 93 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 94 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 95 96 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 97 98 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 99 CSS_DEVICE_BASE, \ 100 CSS_DEVICE_SIZE, \ 101 MT_DEVICE | MT_RW | MT_SECURE) 102 103 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 104 NSRAM_BASE, \ 105 NSRAM_SIZE, \ 106 MT_DEVICE | MT_RW | MT_NS) 107 108 #if defined(IMAGE_BL2U) 109 #define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ 110 SCP_BL2U_BASE, \ 111 SCP_BL2U_LIMIT \ 112 - SCP_BL2U_BASE,\ 113 MT_RW_DATA | MT_SECURE) 114 #endif 115 116 /* Platform ID address */ 117 #define SSC_VERSION_OFFSET 0x040 118 119 #define SSC_VERSION_CONFIG_SHIFT 28 120 #define SSC_VERSION_MAJOR_REV_SHIFT 24 121 #define SSC_VERSION_MINOR_REV_SHIFT 20 122 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 123 #define SSC_VERSION_PART_NUM_SHIFT 0x0 124 #define SSC_VERSION_CONFIG_MASK 0xf 125 #define SSC_VERSION_MAJOR_REV_MASK 0xf 126 #define SSC_VERSION_MINOR_REV_MASK 0xf 127 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 128 #define SSC_VERSION_PART_NUM_MASK 0xfff 129 130 #define SID_SYSTEM_ID_PART_NUM_MASK 0xfff 131 132 /* SSC debug configuration registers */ 133 #define SSC_DBGCFG_SET 0x14 134 #define SSC_DBGCFG_CLR 0x18 135 136 #define SPIDEN_INT_CLR_SHIFT 6 137 #define SPIDEN_SEL_SET_SHIFT 7 138 139 #ifndef __ASSEMBLER__ 140 141 /* SSC_VERSION related accessors */ 142 143 /* Returns the part number of the platform */ 144 #define GET_SSC_VERSION_PART_NUM(val) \ 145 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 146 SSC_VERSION_PART_NUM_MASK) 147 148 /* Returns the configuration number of the platform */ 149 #define GET_SSC_VERSION_CONFIG(val) \ 150 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 151 SSC_VERSION_CONFIG_MASK) 152 153 #endif /* __ASSEMBLER__ */ 154 155 /************************************************************************* 156 * Required platform porting definitions common to all 157 * ARM Compute SubSystems (CSS) 158 ************************************************************************/ 159 160 /* 161 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 162 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 163 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 164 * an SCP_BL2/SCP_BL2U image. 165 */ 166 #if CSS_LOAD_SCP_IMAGES 167 168 #if ARM_BL31_IN_DRAM 169 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 170 #endif 171 172 /* 173 * Load address of SCP_BL2 in CSS platform ports 174 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 175 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 176 * BL31 is loaded over the top. 177 */ 178 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 179 #define SCP_BL2_LIMIT BL2_BASE 180 181 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 182 #define SCP_BL2U_LIMIT BL2_BASE 183 #endif /* CSS_LOAD_SCP_IMAGES */ 184 185 /* Load address of Non-Secure Image for CSS platform ports */ 186 #define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000) 187 188 /* TZC related constants */ 189 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 190 191 /* 192 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 193 * command 194 */ 195 #define CSS_CLUSTER_PWR_STATE_ON 0 196 #define CSS_CLUSTER_PWR_STATE_OFF 3 197 198 #define CSS_CPU_PWR_STATE_ON 1 199 #define CSS_CPU_PWR_STATE_OFF 0 200 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 201 202 #endif /* CSS_DEF_H */ 203