1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Synced from Linux v4.19
5 */
6
7 #ifndef __LINUX_MTD_SPI_NOR_H
8 #define __LINUX_MTD_SPI_NOR_H
9
10 #include <linux/bitops.h>
11 #include <linux/mtd/cfi.h>
12 #include <linux/mtd/mtd.h>
13
14 /*
15 * Manufacturer IDs
16 *
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
19 */
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
25 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
26 #define SNOR_MFR_SPANSION CFI_MFR_AMD
27 #define SNOR_MFR_SST CFI_MFR_SST
28 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
29
30 /*
31 * Note on opcode nomenclature: some opcodes have a format like
32 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
33 * of I/O lines used for the opcode, address, and data (respectively). The
34 * FUNCTION has an optional suffix of '4', to represent an opcode which
35 * requires a 4-byte (32-bit) address.
36 */
37
38 /* Flash opcodes. */
39 #define SPINOR_OP_WREN 0x06 /* Write enable */
40 #define SPINOR_OP_RDSR 0x05 /* Read status register */
41 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
42 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
43 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
44 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
45 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
46 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
47 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
48 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
49 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
50 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
51 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
52 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
53 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
54 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
55 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
56 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
57 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
58 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
59 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
60 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
61 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
62 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
63 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
64 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
65
66 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
67 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
68 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
69 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
70 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
71 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
72 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
73 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
74 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
75 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
76 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
77 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
78 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
79
80 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
81 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
82 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
83 #define SPINOR_OP_READ_1_4_4_DTR 0xed
84
85 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
86 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
87 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
88
89 /* Used for SST flashes only. */
90 #define SPINOR_OP_BP 0x02 /* Byte program */
91 #define SPINOR_OP_WRDI 0x04 /* Write disable */
92 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
93
94 /* Used for SST26* flashes only. */
95 #define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
96 #define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
97
98 /* Used for S3AN flashes only */
99 #define SPINOR_OP_XSE 0x50 /* Sector erase */
100 #define SPINOR_OP_XPP 0x82 /* Page program */
101 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
102
103 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
104 #define XSR_RDY BIT(7) /* Ready */
105
106 /* Used for Macronix and Winbond flashes. */
107 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
108 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
109
110 /* Used for Spansion flashes only. */
111 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
112 #define SPINOR_OP_BRRD 0x16 /* Bank register read */
113 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
114
115 /* Used for Micron flashes only. */
116 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
117 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
118
119 /* Status Register bits. */
120 #define SR_WIP BIT(0) /* Write in progress */
121 #define SR_WEL BIT(1) /* Write enable latch */
122 /* meaning of other SR_* bits may differ between vendors */
123 #define SR_BP0 BIT(2) /* Block protect 0 */
124 #define SR_BP1 BIT(3) /* Block protect 1 */
125 #define SR_BP2 BIT(4) /* Block protect 2 */
126 #define SR_TB BIT(5) /* Top/Bottom protect */
127 #define SR_SRWD BIT(7) /* SR write protect */
128 /* Spansion/Cypress specific status bits */
129 #define SR_E_ERR BIT(5)
130 #define SR_P_ERR BIT(6)
131
132 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
133
134 /* Enhanced Volatile Configuration Register bits */
135 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
136
137 /* Flag Status Register bits */
138 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
139 #define FSR_E_ERR BIT(5) /* Erase operation status */
140 #define FSR_P_ERR BIT(4) /* Program operation status */
141 #define FSR_PT_ERR BIT(1) /* Protection error bit */
142
143 /* Configuration Register bits. */
144 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
145
146 /* Status Register 2 bits. */
147 #define SR2_QUAD_EN_BIT7 BIT(7)
148
149 /* Supported SPI protocols */
150 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
151 #define SNOR_PROTO_INST_SHIFT 16
152 #define SNOR_PROTO_INST(_nbits) \
153 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
154 SNOR_PROTO_INST_MASK)
155
156 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
157 #define SNOR_PROTO_ADDR_SHIFT 8
158 #define SNOR_PROTO_ADDR(_nbits) \
159 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
160 SNOR_PROTO_ADDR_MASK)
161
162 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
163 #define SNOR_PROTO_DATA_SHIFT 0
164 #define SNOR_PROTO_DATA(_nbits) \
165 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
166 SNOR_PROTO_DATA_MASK)
167
168 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
169
170 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
171 (SNOR_PROTO_INST(_inst_nbits) | \
172 SNOR_PROTO_ADDR(_addr_nbits) | \
173 SNOR_PROTO_DATA(_data_nbits))
174 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
175 (SNOR_PROTO_IS_DTR | \
176 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
177
178 enum spi_nor_protocol {
179 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
180 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
181 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
182 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
183 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
184 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
185 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
186 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
187 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
188 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
189
190 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
191 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
192 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
193 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
194 };
195
spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)196 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
197 {
198 return !!(proto & SNOR_PROTO_IS_DTR);
199 }
200
spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)201 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
202 {
203 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
204 SNOR_PROTO_INST_SHIFT;
205 }
206
spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)207 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
208 {
209 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
210 SNOR_PROTO_ADDR_SHIFT;
211 }
212
spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)213 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
214 {
215 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
216 SNOR_PROTO_DATA_SHIFT;
217 }
218
spi_nor_get_protocol_width(enum spi_nor_protocol proto)219 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
220 {
221 return spi_nor_get_protocol_data_nbits(proto);
222 }
223
224 #define SPI_NOR_MAX_CMD_SIZE 8
225 enum spi_nor_ops {
226 SPI_NOR_OPS_READ = 0,
227 SPI_NOR_OPS_WRITE,
228 SPI_NOR_OPS_ERASE,
229 SPI_NOR_OPS_LOCK,
230 SPI_NOR_OPS_UNLOCK,
231 };
232
233 enum spi_nor_option_flags {
234 SNOR_F_USE_FSR = BIT(0),
235 SNOR_F_HAS_SR_TB = BIT(1),
236 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
237 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
238 SNOR_F_READY_XSR_RDY = BIT(4),
239 SNOR_F_USE_CLSR = BIT(5),
240 SNOR_F_BROKEN_RESET = BIT(6),
241 };
242
243 /**
244 * struct flash_info - Forward declaration of a structure used internally by
245 * spi_nor_scan()
246 */
247 struct flash_info;
248
249 /*
250 * TODO: Remove, once all users of spi_flash interface are moved to MTD
251 *
252 * struct spi_flash {
253 * Defined below (keep this text to enable searching for spi_flash decl)
254 * }
255 */
256 #define spi_flash spi_nor
257
258 /**
259 * struct spi_nor - Structure for defining a the SPI NOR layer
260 * @mtd: point to a mtd_info structure
261 * @lock: the lock for the read/write/erase/lock/unlock operations
262 * @dev: point to a spi device, or a spi nor controller device.
263 * @info: spi-nor part JDEC MFR id and other info
264 * @page_size: the page size of the SPI NOR
265 * @addr_width: number of address bytes
266 * @erase_opcode: the opcode for erasing a sector
267 * @read_opcode: the read opcode
268 * @read_dummy: the dummy needed by the read operation
269 * @program_opcode: the program opcode
270 * @bank_read_cmd: Bank read cmd
271 * @bank_write_cmd: Bank write cmd
272 * @bank_curr: Current flash bank
273 * @sst_write_second: used by the SST write operation
274 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
275 * @read_proto: the SPI protocol for read operations
276 * @write_proto: the SPI protocol for write operations
277 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
278 * @cmd_buf: used by the write_reg
279 * @prepare: [OPTIONAL] do some preparations for the
280 * read/write/erase/lock/unlock operations
281 * @unprepare: [OPTIONAL] do some post work after the
282 * read/write/erase/lock/unlock operations
283 * @read_reg: [DRIVER-SPECIFIC] read out the register
284 * @write_reg: [DRIVER-SPECIFIC] write data to the register
285 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
286 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
287 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
288 * at the offset @offs; if not provided by the driver,
289 * spi-nor will send the erase opcode via write_reg()
290 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
291 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
292 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
293 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
294 * completely locked
295 * @priv: the private data
296 */
297 struct spi_nor {
298 struct mtd_info mtd;
299 struct udevice *dev;
300 struct spi_slave *spi;
301 const struct flash_info *info;
302 u32 page_size;
303 u8 addr_width;
304 u8 erase_opcode;
305 u8 read_opcode;
306 u8 read_dummy;
307 u8 program_opcode;
308 #ifdef CONFIG_SPI_FLASH_BAR
309 u8 bank_read_cmd;
310 u8 bank_write_cmd;
311 u8 bank_curr;
312 #endif
313 enum spi_nor_protocol read_proto;
314 enum spi_nor_protocol write_proto;
315 enum spi_nor_protocol reg_proto;
316 bool sst_write_second;
317 u32 flags;
318 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
319
320 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
321 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
322 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
323 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
324
325 ssize_t (*read)(struct spi_nor *nor, loff_t from,
326 size_t len, u_char *read_buf);
327 ssize_t (*write)(struct spi_nor *nor, loff_t to,
328 size_t len, const u_char *write_buf);
329 int (*erase)(struct spi_nor *nor, loff_t offs);
330
331 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
332 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
333 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
334 int (*quad_enable)(struct spi_nor *nor);
335
336 void *priv;
337 /* Compatibility for spi_flash, remove once sf layer is merged with mtd */
338 const char *name;
339 u32 size;
340 u32 sector_size;
341 u32 erase_size;
342 };
343
spi_nor_set_flash_node(struct spi_nor * nor,const struct device_node * np)344 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
345 const struct device_node *np)
346 {
347 mtd_set_of_node(&nor->mtd, np);
348 }
349
350 static inline const struct
spi_nor_get_flash_node(struct spi_nor * nor)351 device_node *spi_nor_get_flash_node(struct spi_nor *nor)
352 {
353 return mtd_get_of_node(&nor->mtd);
354 }
355
356 /**
357 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
358 * supported by the SPI controller (bus master).
359 * @mask: the bitmask listing all the supported hw capabilies
360 */
361 struct spi_nor_hwcaps {
362 u32 mask;
363 };
364
365 /*
366 *(Fast) Read capabilities.
367 * MUST be ordered by priority: the higher bit position, the higher priority.
368 * As a matter of performances, it is relevant to use Octo SPI protocols first,
369 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
370 * (Slow) Read.
371 */
372 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
373 #define SNOR_HWCAPS_READ BIT(0)
374 #define SNOR_HWCAPS_READ_FAST BIT(1)
375 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
376
377 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
378 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
379 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
380 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
381 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
382
383 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
384 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
385 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
386 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
387 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
388
389 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
390 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
391 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
392 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
393 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
394
395 /*
396 * Page Program capabilities.
397 * MUST be ordered by priority: the higher bit position, the higher priority.
398 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
399 * legacy SPI 1-1-1 protocol.
400 * Note that Dual Page Programs are not supported because there is no existing
401 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
402 * implements such commands.
403 */
404 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
405 #define SNOR_HWCAPS_PP BIT(16)
406
407 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
408 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
409 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
410 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
411
412 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
413 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
414 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
415 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
416
417 /**
418 * spi_nor_scan() - scan the SPI NOR
419 * @nor: the spi_nor structure
420 *
421 * The drivers can use this function to scan the SPI NOR.
422 * In the scanning, it will try to get all the necessary information to
423 * fill the mtd_info{} and the spi_nor{}.
424 *
425 * Return: 0 for success, others for failure.
426 */
427 int spi_nor_scan(struct spi_nor *nor);
428
429 #endif
430