1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef __PMIC_STPMIC1_H_ 7 #define __PMIC_STPMIC1_H_ 8 9 #define STPMIC1_MAIN_CR 0x10 10 #define STPMIC1_BUCKS_MRST_CR 0x18 11 #define STPMIC1_LDOS_MRST_CR 0x1a 12 #define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck)) 13 #define STPMIC1_REFDDR_MAIN_CR 0x24 14 #define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo)) 15 #define STPMIC1_BST_SW_CR 0x40 16 #define STPMIC1_NVM_SR 0xb8 17 #define STPMIC1_NVM_CR 0xb9 18 19 /* Main PMIC Control Register (MAIN_CR) */ 20 #define STPMIC1_SWOFF BIT(0) 21 #define STPMIC1_RREQ_EN BIT(1) 22 23 /* BUCKS_MRST_CR */ 24 #define STPMIC1_MRST_BUCK(buck) BIT(buck) 25 #define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \ 26 STPMIC1_MRST_BUCK(STPMIC1_BUCK3)) 27 28 /* LDOS_MRST_CR */ 29 #define STPMIC1_MRST_LDO(ldo) BIT(ldo) 30 #define STPMIC1_MRST_LDO_DEBUG 0 31 32 /* BUCKx_MAIN_CR (x=1...4) */ 33 #define STPMIC1_BUCK_ENA BIT(0) 34 #define STPMIC1_BUCK_PREG_MODE BIT(1) 35 #define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2) 36 #define STPMIC1_BUCK_VOUT_SHIFT 2 37 #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT) 38 39 #define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24) 40 #define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30) 41 42 #define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39) 43 44 /* REFDDR_MAIN_CR */ 45 #define STPMIC1_VREF_ENA BIT(0) 46 47 /* LDOX_MAIN_CR */ 48 #define STPMIC1_LDO_ENA BIT(0) 49 #define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2) 50 #define STPMIC1_LDO12356_VOUT_SHIFT 2 51 #define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT) 52 53 #define STPMIC1_LDO3_MODE BIT(7) 54 #define STPMIC1_LDO3_DDR_SEL 31 55 #define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9) 56 57 #define STPMIC1_LDO4_UV 3300000 58 59 /* BST_SW_CR */ 60 #define STPMIC1_BST_ON BIT(0) 61 #define STPMIC1_VBUSOTG_ON BIT(1) 62 #define STPMIC1_SWOUT_ON BIT(2) 63 #define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON) 64 65 /* NVM_SR */ 66 #define STPMIC1_NVM_BUSY BIT(0) 67 68 /* NVM_CR */ 69 #define STPMIC1_NVM_CMD_PROGRAM 1 70 #define STPMIC1_NVM_CMD_READ 2 71 72 /* Timeout */ 73 #define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 74 #define STPMIC1_DEFAULT_STOP_DELAY_MS 5 75 #define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10 76 77 enum { 78 STPMIC1_BUCK1, 79 STPMIC1_BUCK2, 80 STPMIC1_BUCK3, 81 STPMIC1_BUCK4, 82 STPMIC1_MAX_BUCK, 83 }; 84 85 enum { 86 STPMIC1_PREG_MODE_HP, 87 STPMIC1_PREG_MODE_LP, 88 }; 89 90 enum { 91 STPMIC1_LDO1, 92 STPMIC1_LDO2, 93 STPMIC1_LDO3, 94 STPMIC1_LDO4, 95 STPMIC1_LDO5, 96 STPMIC1_LDO6, 97 STPMIC1_MAX_LDO, 98 }; 99 100 enum { 101 STPMIC1_LDO_MODE_NORMAL, 102 STPMIC1_LDO_MODE_BYPASS, 103 STPMIC1_LDO_MODE_SINK_SOURCE, 104 }; 105 106 enum { 107 STPMIC1_PWR_SW1, 108 STPMIC1_PWR_SW2, 109 STPMIC1_MAX_PWR_SW, 110 }; 111 #endif 112