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1 #include <stdint.h>
2 
3 #include <cpuinfo.h>
4 #include <x86/api.h>
5 
6 
7 /* Intel vendor string: "GenuineIntel" */
8 #define Genu UINT32_C(0x756E6547)
9 #define ineI UINT32_C(0x49656E69)
10 #define ntel UINT32_C(0x6C65746E)
11 
12 /* AMD vendor strings: "AuthenticAMD", "AMDisbetter!", "AMD ISBETTER" */
13 #define Auth UINT32_C(0x68747541)
14 #define enti UINT32_C(0x69746E65)
15 #define cAMD UINT32_C(0x444D4163)
16 #define AMDi UINT32_C(0x69444D41)
17 #define sbet UINT32_C(0x74656273)
18 #define ter  UINT32_C(0x21726574)
19 #define AMD  UINT32_C(0x20444D41)
20 #define ISBE UINT32_C(0x45425349)
21 #define TTER UINT32_C(0x52455454)
22 
23 /* VIA (Centaur) vendor strings: "CentaurHauls", "VIA VIA VIA " */
24 #define Cent UINT32_C(0x746E6543)
25 #define aurH UINT32_C(0x48727561)
26 #define auls UINT32_C(0x736C7561)
27 #define VIA  UINT32_C(0x20414956)
28 
29 /* Transmeta vendor strings: "GenuineTMx86", "TransmetaCPU" */
30 #define ineT UINT32_C(0x54656E69)
31 #define Mx86 UINT32_C(0x3638784D)
32 #define Tran UINT32_C(0x6E617254)
33 #define smet UINT32_C(0x74656D73)
34 #define aCPU UINT32_C(0x55504361)
35 
36 /* Cyrix vendor string: "CyrixInstead" */
37 #define Cyri UINT32_C(0x69727943)
38 #define xIns UINT32_C(0x736E4978)
39 #define tead UINT32_C(0x64616574)
40 
41 /* Rise vendor string: "RiseRiseRise" */
42 #define Rise UINT32_C(0x65736952)
43 
44 /* NSC vendor string: "Geode by NSC" */
45 #define Geod UINT32_C(0x646F6547)
46 #define e_by UINT32_C(0x79622065)
47 #define NSC  UINT32_C(0x43534E20)
48 
49 /* SiS vendor string: "SiS SiS SiS " */
50 #define SiS  UINT32_C(0x20536953)
51 
52 /* NexGen vendor string: "NexGenDriven" */
53 #define NexG UINT32_C(0x4778654E)
54 #define enDr UINT32_C(0x72446E65)
55 #define iven UINT32_C(0x6E657669)
56 
57 /* UMC vendor string: "UMC UMC UMC " */
58 #define UMC  UINT32_C(0x20434D55)
59 
60 /* RDC vendor string: "Genuine  RDC" */
61 #define ine  UINT32_C(0x20656E69)
62 #define RDC  UINT32_C(0x43445220)
63 
64 /* D&MP vendor string: "Vortex86 SoC" */
65 #define Vort UINT32_C(0x74726F56)
66 #define ex86 UINT32_C(0x36387865)
67 #define SoC  UINT32_C(0x436F5320)
68 
69 
cpuinfo_x86_decode_vendor(uint32_t ebx,uint32_t ecx,uint32_t edx)70 enum cpuinfo_vendor cpuinfo_x86_decode_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx) {
71 	switch (ebx) {
72 		case Genu:
73 			switch (edx) {
74 				case ineI:
75 					if (ecx == ntel) {
76 						/* "GenuineIntel" */
77 						return cpuinfo_vendor_intel;
78 					}
79 					break;
80 #if CPUINFO_ARCH_X86
81 				case ineT:
82 					if (ecx == Mx86) {
83 						/* "GenuineTMx86" */
84 						return cpuinfo_vendor_transmeta;
85 					}
86 					break;
87 				case ine:
88 					if (ecx == RDC) {
89 						/* "Genuine  RDC" */
90 						return cpuinfo_vendor_rdc;
91 					}
92 					break;
93 #endif
94 			}
95 			break;
96 		case Auth:
97 			if (edx == enti && ecx == cAMD) {
98 				/* "AuthenticAMD" */
99 				return cpuinfo_vendor_amd;
100 			}
101 			break;
102 		case Cent:
103 			if (edx == aurH && ecx == auls) {
104 				/* "CentaurHauls" */
105 				return cpuinfo_vendor_via;
106 			}
107 			break;
108 #if CPUINFO_ARCH_X86
109 		case AMDi:
110 			if (edx == sbet && ecx == ter) {
111 				/* "AMDisbetter!" */
112 				return cpuinfo_vendor_amd;
113 			}
114 			break;
115 		case AMD:
116 			if (edx == ISBE && ecx == TTER) {
117 				/* "AMD ISBETTER" */
118 				return cpuinfo_vendor_amd;
119 			}
120 			break;
121 		case VIA:
122 			if (edx == VIA && ecx == VIA) {
123 				/* "VIA VIA VIA " */
124 				return cpuinfo_vendor_via;
125 			}
126 			break;
127 		case Tran:
128 			if (edx == smet && ecx == aCPU) {
129 				/* "TransmetaCPU" */
130 				return cpuinfo_vendor_transmeta;
131 			}
132 			break;
133 		case Cyri:
134 			if (edx == xIns && ecx == tead) {
135 				/* "CyrixInstead" */
136 				return cpuinfo_vendor_cyrix;
137 			}
138 			break;
139 		case Rise:
140 			if (edx == Rise && ecx == Rise) {
141 				/* "RiseRiseRise" */
142 				return cpuinfo_vendor_rise;
143 			}
144 			break;
145 		case Geod:
146 			if (edx == e_by && ecx == NSC) {
147 				/* "Geode by NSC" */
148 				return cpuinfo_vendor_nsc;
149 			}
150 			break;
151 		case SiS:
152 			if (edx == SiS && ecx == SiS) {
153 				/* "SiS SiS SiS " */
154 				return cpuinfo_vendor_sis;
155 			}
156 			break;
157 		case NexG:
158 			if (edx == enDr && ecx == iven) {
159 				/* "NexGenDriven" */
160 				return cpuinfo_vendor_nexgen;
161 			}
162 			break;
163 		case UMC:
164 			if (edx == UMC && ecx == UMC) {
165 				/* "UMC UMC UMC " */
166 				return cpuinfo_vendor_umc;
167 			}
168 			break;
169 		case Vort:
170 			if (edx == ex86 && ecx == SoC) {
171 				/* "Vortex86 SoC" */
172 				return cpuinfo_vendor_dmp;
173 			}
174 			break;
175 #endif
176 	}
177 	return cpuinfo_vendor_unknown;
178 }
179