1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_DEF_H 8 #define TEGRA_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Power down state IDs 14 ******************************************************************************/ 15 #define PSTATE_ID_CORE_POWERDN U(7) 16 #define PSTATE_ID_CLUSTER_IDLE U(16) 17 #define PSTATE_ID_SOC_POWERDN U(27) 18 19 /******************************************************************************* 20 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` 21 * call as the `state-id` field in the 'power state' parameter. 22 ******************************************************************************/ 23 #define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN 24 25 /******************************************************************************* 26 * Platform power states (used by PSCI framework) 27 * 28 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 29 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 30 ******************************************************************************/ 31 #define PLAT_MAX_RET_STATE U(1) 32 #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) 33 34 /******************************************************************************* 35 * Chip specific page table and MMU setup constants 36 ******************************************************************************/ 37 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) 38 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) 39 40 /******************************************************************************* 41 * SC7 entry firmware's header size 42 ******************************************************************************/ 43 #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400) 44 45 /******************************************************************************* 46 * iRAM memory constants 47 ******************************************************************************/ 48 #define TEGRA_IRAM_BASE U(0x40000000) 49 #define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */ 50 #define TEGRA_IRAM_SIZE U(40000) /* 256KB */ 51 52 /******************************************************************************* 53 * GIC memory map 54 ******************************************************************************/ 55 #define TEGRA_GICD_BASE U(0x50041000) 56 #define TEGRA_GICC_BASE U(0x50042000) 57 58 /******************************************************************************* 59 * Secure IRQ definitions 60 ******************************************************************************/ 61 #define TEGRA210_WDT_CPU_LEGACY_FIQ U(28) 62 63 /******************************************************************************* 64 * Tegra Memory Select Switch Controller constants 65 ******************************************************************************/ 66 #define TEGRA_MSELECT_BASE U(0x50060000) 67 68 #define MSELECT_CONFIG U(0x0) 69 #define ENABLE_WRAP_INCR_MASTER2_BIT (U(1) << U(29)) 70 #define ENABLE_WRAP_INCR_MASTER1_BIT (U(1) << U(28)) 71 #define ENABLE_WRAP_INCR_MASTER0_BIT (U(1) << U(27)) 72 #define UNSUPPORTED_TX_ERR_MASTER2_BIT (U(1) << U(25)) 73 #define UNSUPPORTED_TX_ERR_MASTER1_BIT (U(1) << U(24)) 74 #define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ 75 UNSUPPORTED_TX_ERR_MASTER1_BIT) 76 #define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ 77 ENABLE_WRAP_INCR_MASTER1_BIT | \ 78 ENABLE_WRAP_INCR_MASTER0_BIT) 79 80 /******************************************************************************* 81 * Tegra Resource Semaphore constants 82 ******************************************************************************/ 83 #define TEGRA_RES_SEMA_BASE 0x60001000UL 84 #define STA_OFFSET 0UL 85 #define SET_OFFSET 4UL 86 #define CLR_OFFSET 8UL 87 88 /******************************************************************************* 89 * Tegra Primary Interrupt Controller constants 90 ******************************************************************************/ 91 #define TEGRA_PRI_ICTLR_BASE 0x60004000UL 92 #define CPU_IEP_FIR_SET 0x18UL 93 94 /******************************************************************************* 95 * Tegra micro-seconds timer constants 96 ******************************************************************************/ 97 #define TEGRA_TMRUS_BASE U(0x60005010) 98 #define TEGRA_TMRUS_SIZE U(0x1000) 99 100 /******************************************************************************* 101 * Tegra Clock and Reset Controller constants 102 ******************************************************************************/ 103 #define TEGRA_CAR_RESET_BASE U(0x60006000) 104 #define TEGRA_BOND_OUT_H U(0x74) 105 #define APB_DMA_LOCK_BIT (U(1) << 2) 106 #define AHB_DMA_LOCK_BIT (U(1) << 1) 107 #define TEGRA_BOND_OUT_U U(0x78) 108 #define IRAM_D_LOCK_BIT (U(1) << 23) 109 #define IRAM_C_LOCK_BIT (U(1) << 22) 110 #define IRAM_B_LOCK_BIT (U(1) << 21) 111 #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) 112 #define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290) 113 #define GPU_RESET_BIT (U(1) << 24) 114 #define GPU_SET_BIT (U(1) << 24) 115 #define TEGRA_RST_DEV_SET_Y U(0x2a8) 116 #define NVENC_RESET_BIT (U(1) << 27) 117 #define TSECB_RESET_BIT (U(1) << 14) 118 #define APE_RESET_BIT (U(1) << 6) 119 #define NVJPG_RESET_BIT (U(1) << 3) 120 #define NVDEC_RESET_BIT (U(1) << 2) 121 #define TEGRA_RST_DEV_SET_L U(0x300) 122 #define HOST1X_RESET_BIT (U(1) << 28) 123 #define ISP_RESET_BIT (U(1) << 23) 124 #define USBD_RESET_BIT (U(1) << 22) 125 #define VI_RESET_BIT (U(1) << 20) 126 #define SDMMC4_RESET_BIT (U(1) << 15) 127 #define SDMMC1_RESET_BIT (U(1) << 14) 128 #define SDMMC2_RESET_BIT (U(1) << 9) 129 #define TEGRA_RST_DEV_SET_H U(0x308) 130 #define USB2_RESET_BIT (U(1) << 26) 131 #define APBDMA_RESET_BIT (U(1) << 2) 132 #define AHBDMA_RESET_BIT (U(1) << 1) 133 #define TEGRA_RST_DEV_SET_U U(0x310) 134 #define XUSB_DEV_RESET_BIT (U(1) << 31) 135 #define XUSB_HOST_RESET_BIT (U(1) << 25) 136 #define TSEC_RESET_BIT (U(1) << 19) 137 #define PCIE_RESET_BIT (U(1) << 6) 138 #define SDMMC3_RESET_BIT (U(1) << 5) 139 #define TEGRA_RST_DEVICES_V U(0x358) 140 #define TEGRA_RST_DEVICES_W U(0x35C) 141 #define ENTROPY_CLK_ENB_BIT (U(1) << 21) 142 #define TEGRA_CLK_OUT_ENB_V U(0x360) 143 #define SE_CLK_ENB_BIT (U(1) << 31) 144 #define TEGRA_CLK_OUT_ENB_W U(0x364) 145 #define ENTROPY_RESET_BIT (U(1) << 21) 146 #define TEGRA_RST_DEV_SET_V U(0x430) 147 #define SE_RESET_BIT (U(1) << 31) 148 #define HDA_RESET_BIT (U(1) << 29) 149 #define SATA_RESET_BIT (U(1) << 28) 150 #define TEGRA_RST_DEV_CLR_V U(0x434) 151 #define TEGRA_CLK_ENB_V U(0x440) 152 153 /******************************************************************************* 154 * Tegra Flow Controller constants 155 ******************************************************************************/ 156 #define TEGRA_FLOWCTRL_BASE U(0x60007000) 157 158 /******************************************************************************* 159 * Tegra AHB arbitration controller 160 ******************************************************************************/ 161 #define TEGRA_AHB_ARB_BASE 0x6000C000UL 162 163 /******************************************************************************* 164 * Tegra Secure Boot Controller constants 165 ******************************************************************************/ 166 #define TEGRA_SB_BASE U(0x6000C200) 167 168 /******************************************************************************* 169 * Tegra Exception Vectors constants 170 ******************************************************************************/ 171 #define TEGRA_EVP_BASE U(0x6000F000) 172 173 /******************************************************************************* 174 * Tegra Miscellaneous register constants 175 ******************************************************************************/ 176 #define TEGRA_MISC_BASE U(0x70000000) 177 #define HARDWARE_REVISION_OFFSET U(0x804) 178 #define APB_SLAVE_SECURITY_ENABLE U(0xC00) 179 #define PMC_SECURITY_EN_BIT (U(1) << 13) 180 #define PINMUX_AUX_DVFS_PWM U(0x3184) 181 #define PINMUX_PWM_TRISTATE (U(1) << 4) 182 183 /******************************************************************************* 184 * Tegra UART controller base addresses 185 ******************************************************************************/ 186 #define TEGRA_UARTA_BASE U(0x70006000) 187 #define TEGRA_UARTB_BASE U(0x70006040) 188 #define TEGRA_UARTC_BASE U(0x70006200) 189 #define TEGRA_UARTD_BASE U(0x70006300) 190 #define TEGRA_UARTE_BASE U(0x70006400) 191 192 /******************************************************************************* 193 * Tegra Fuse Controller related constants 194 ******************************************************************************/ 195 #define TEGRA_FUSE_BASE 0x7000F800UL 196 #define FUSE_BOOT_SECURITY_INFO 0x268UL 197 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN (0x1U << 7) 198 #define FUSE_JTAG_SECUREID_VALID (0x104UL) 199 #define ECID_VALID (0x1UL) 200 201 202 /******************************************************************************* 203 * Tegra Power Mgmt Controller constants 204 ******************************************************************************/ 205 #define TEGRA_PMC_BASE U(0x7000E400) 206 #define TEGRA_PMC_SIZE U(0xC00) /* 3k */ 207 208 /******************************************************************************* 209 * Tegra Atomics constants 210 ******************************************************************************/ 211 #define TEGRA_ATOMICS_BASE 0x70016000UL 212 #define TRIGGER0_REG_OFFSET 0UL 213 #define TRIGGER_WIDTH_SHIFT 4UL 214 #define TRIGGER_ID_SHIFT 16UL 215 #define RESULT0_REG_OFFSET 0xC00UL 216 217 /******************************************************************************* 218 * Tegra Memory Controller constants 219 ******************************************************************************/ 220 #define TEGRA_MC_BASE U(0x70019000) 221 222 /* Memory Controller Interrupt Status */ 223 #define MC_INTSTATUS 0x00U 224 225 /* TZDRAM carveout configuration registers */ 226 #define MC_SECURITY_CFG0_0 U(0x70) 227 #define MC_SECURITY_CFG1_0 U(0x74) 228 #define MC_SECURITY_CFG3_0 U(0x9BC) 229 230 /* Video Memory carveout configuration registers */ 231 #define MC_VIDEO_PROTECT_BASE_HI U(0x978) 232 #define MC_VIDEO_PROTECT_BASE_LO U(0x648) 233 #define MC_VIDEO_PROTECT_SIZE_MB U(0x64c) 234 235 /* SMMU configuration registers*/ 236 #define MC_SMMU_PPCS_ASID_0 0x270U 237 #define PPCS_SMMU_ENABLE (0x1U << 31) 238 239 /******************************************************************************* 240 * Tegra CLDVFS constants 241 ******************************************************************************/ 242 #define TEGRA_CL_DVFS_BASE U(0x70110000) 243 #define DVFS_DFLL_CTRL U(0x00) 244 #define ENABLE_OPEN_LOOP U(1) 245 #define ENABLE_CLOSED_LOOP U(2) 246 #define DVFS_DFLL_OUTPUT_CFG U(0x20) 247 #define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30) 248 #define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6) 249 250 /******************************************************************************* 251 * Tegra SE constants 252 ******************************************************************************/ 253 #define TEGRA_SE1_BASE U(0x70012000) 254 #define TEGRA_SE2_BASE U(0x70412000) 255 #define TEGRA_PKA1_BASE U(0x70420000) 256 #define TEGRA_SE2_RANGE_SIZE U(0x2000) 257 #define SE_TZRAM_SECURITY U(0x4) 258 259 /******************************************************************************* 260 * Tegra TZRAM constants 261 ******************************************************************************/ 262 #define TEGRA_TZRAM_BASE U(0x7C010000) 263 #define TEGRA_TZRAM_SIZE U(0x10000) 264 265 /******************************************************************************* 266 * Tegra TZRAM carveout constants 267 ******************************************************************************/ 268 #define TEGRA_TZRAM_CARVEOUT_BASE U(0x7C04C000) 269 #define TEGRA_TZRAM_CARVEOUT_SIZE U(0x4000) 270 271 #endif /* TEGRA_DEF_H */ 272