1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <lib/utils_def.h> 12 13 #include <tegra_def.h> 14 15 /* 16 * Platform binary types for linking 17 */ 18 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19 #define PLATFORM_LINKER_ARCH aarch64 20 21 /******************************************************************************* 22 * Generic platform constants 23 ******************************************************************************/ 24 25 /* Size of cacheable stacks */ 26 #ifdef IMAGE_BL31 27 #define PLATFORM_STACK_SIZE U(0x400) 28 #endif 29 30 #define TEGRA_PRIMARY_CPU U(0x0) 31 32 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 33 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 34 PLATFORM_MAX_CPUS_PER_CLUSTER) 35 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 36 PLATFORM_CLUSTER_COUNT + 1) 37 38 /******************************************************************************* 39 * Platform console related constants 40 ******************************************************************************/ 41 #define TEGRA_CONSOLE_BAUDRATE U(115200) 42 #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 43 #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 44 45 /******************************************************************************* 46 * Platform memory map related constants 47 ******************************************************************************/ 48 /* Size of trusted dram */ 49 #define TZDRAM_SIZE U(0x00400000) 50 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 51 52 /******************************************************************************* 53 * BL31 specific defines. 54 ******************************************************************************/ 55 #define BL31_SIZE U(0x40000) 56 #define BL31_BASE TZDRAM_BASE 57 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 58 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 59 #define BL32_LIMIT TZDRAM_END 60 61 /******************************************************************************* 62 * Some data must be aligned on the biggest cache line size in the platform. 63 * This is known only to the platform as it might have a combination of 64 * integrated and external caches. 65 ******************************************************************************/ 66 #define CACHE_WRITEBACK_SHIFT 6 67 #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ 68 69 /******************************************************************************* 70 * Dummy macros to compile io_storage support 71 ******************************************************************************/ 72 #define MAX_IO_DEVICES U(0) 73 #define MAX_IO_HANDLES U(0) 74 75 #endif /* PLATFORM_DEF_H */ 76