1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef HI3660_H 7 #define HI3660_H 8 9 #include <hi3660_crg.h> 10 #include <hi3660_hkadc.h> 11 #include <hi3660_mem_map.h> 12 13 #define ASP_CFG_REG_BASE 0xE804E000 14 15 #define ASP_CFG_MMBUF_CTRL_REG (ASP_CFG_REG_BASE + 0x148) 16 17 #define LP_RAM_BASE 0xFFF50000 18 19 #define SCTRL_REG_BASE 0xFFF0A000 20 21 #define SCTRL_CONTROL_REG (SCTRL_REG_BASE + 0x000) 22 #define SCTRL_CONTROL_SYS_MODE(x) (((x) & 0xf) << 3) 23 #define SCTRL_CONTROL_SYS_MODE_NORMAL ((1 << 2) << 3) 24 #define SCTRL_CONTROL_SYS_MODE_SLOW ((1 << 1) << 3) 25 #define SCTRL_CONTROL_SYS_MODE_MASK (0xf << 3) 26 #define SCTRL_CONTROL_MODE_CTRL_NORMAL (1 << 2) 27 #define SCTRL_CONTROL_MODE_CTRL_SLOW (1 << 1) 28 #define SCTRL_CONTROL_MODE_CTRL_MASK 0x7 29 30 #define SCTRL_SCSYSSTAT_REG (SCTRL_REG_BASE + 0x004) 31 32 #define SCTRL_DEEPSLEEPED_REG (SCTRL_REG_BASE + 0x008) 33 #define SCTRL_EFUSE_USB_MASK (1 << 30) 34 #define SCTRL_EFUSE_USB_PLL (1 << 30) 35 #define SCTRL_EFUSE_USB_ABB (0 << 30) 36 #define SCTRL_EFUSE_UFS_MASK (3 << 6) 37 #define SCTRL_EFUSE_UFS_PLL (1 << 6) 38 #define SCTRL_EFUSE_UFS_ABB (0 << 6) 39 40 #define SCTRL_SCISOEN_REG (SCTRL_REG_BASE + 0x040) 41 #define SCTRL_SCISODIS_REG (SCTRL_REG_BASE + 0x044) 42 #define SCISO_MMBUFISO (1 << 3) 43 44 #define SCTRL_SCPWREN_REG (SCTRL_REG_BASE + 0x060) 45 #define SCPWREN_MMBUFPWREN (1 << 3) 46 47 #define SCTRL_PLL_CTRL0_REG (SCTRL_REG_BASE + 0x100) 48 #define SCTRL_PLL0_POSTDIV2(x) (((x) & 0x7) << 23) 49 #define SCTRL_PLL0_POSTDIV1(x) (((x) & 0x7) << 20) 50 #define SCTRL_PLL0_FBDIV(x) (((x) & 0xfff) << 8) 51 #define SCTRL_PLL0_REFDIV(x) (((x) & 0x3f) << 2) 52 #define SCTRL_PLL0_EN (1 << 0) 53 54 #define SCTRL_PLL_CTRL1_REG (SCTRL_REG_BASE + 0x104) 55 #define SCTRL_PLL0_CLK_NO_GATE (1 << 26) 56 #define SCTRL_PLL0_CFG_VLD (1 << 25) 57 #define SCTRL_PLL0_FRACDIV(x) ((x) & 0xFFFFFF) 58 59 #define SCTRL_PLL_STAT_REG (SCTRL_REG_BASE + 0x10C) 60 #define SCTRL_PLL0_STAT (1 << 0) 61 62 #define SCTRL_SCPEREN0_REG (SCTRL_REG_BASE + 0x160) 63 #define SCTRL_SCPERDIS0_REG (SCTRL_REG_BASE + 0x164) 64 #define SCTRL_SCPERSTAT0_REG (SCTRL_REG_BASE + 0x168) 65 66 #define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170) 67 #define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174) 68 #define SCTRL_SCPEREN1_REG (SCTRL_REG_BASE + 0x170) 69 #define SCTRL_SCPERDIS1_REG (SCTRL_REG_BASE + 0x174) 70 #define SCPEREN1_WAIT_DDR_SELFREFRESH_DONE_BYPASS (1u << 31) 71 #define SCPEREN_GT_PCLK_MMBUFCFG (1 << 25) 72 #define SCPEREN_GT_PCLK_MMBUF (1 << 23) 73 #define SCPEREN_GT_ACLK_MMBUF (1 << 22) 74 #define SCPEREN_GT_CLK_NOC_AOBUS2MMBUF (1 << 6) 75 76 #define SCTRL_SCPEREN2_REG (SCTRL_REG_BASE + 0x190) 77 #define SCTRL_SCPERDIS2_REG (SCTRL_REG_BASE + 0x194) 78 #define SCTRL_SCPERSTAT2_REG (SCTRL_REG_BASE + 0x198) 79 #define SCTRL_SCPERRSTEN0_REG (SCTRL_REG_BASE + 0x200) 80 #define SCTRL_SCPERRSTDIS0_REG (SCTRL_REG_BASE + 0x204) 81 #define SCTRL_SCPERRSTSTAT0_REG (SCTRL_REG_BASE + 0x208) 82 #define SCTRL_SCPERRSTEN1_REG (SCTRL_REG_BASE + 0x20C) 83 #define SCTRL_SCPERRSTDIS1_REG (SCTRL_REG_BASE + 0x210) 84 #define SCTRL_SCPERRSTSTAT1_REG (SCTRL_REG_BASE + 0x214) 85 #define IP_RST_MMBUFCFG (1 << 12) 86 #define IP_RST_MMBUF (1 << 11) 87 88 #define SCTRL_SCPERRSTEN2_REG (SCTRL_REG_BASE + 0x218) 89 #define SCTRL_SCPERRSTDIS2_REG (SCTRL_REG_BASE + 0x21C) 90 #define SCTRL_SCPERRSTSTAT2_REG (SCTRL_REG_BASE + 0x220) 91 92 #define SCTRL_SCCLKDIV2_REG (SCTRL_REG_BASE + 0x258) 93 #define SEL_CLK_MMBUF_MASK (0x3 << 8) 94 #define SEL_CLK_MMBUF_PLL0 (0x3 << 8) 95 #define SCCLKDIV2_GT_PCLK_MMBUF (1 << 7) 96 97 #define SCTRL_SCCLKDIV4_REG (SCTRL_REG_BASE + 0x260) 98 #define GT_MMBUF_SYS (1 << 13) 99 #define GT_MMBUF_FLL (1 << 12) 100 #define GT_PLL_CLK_MMBUF (1 << 11) 101 102 #define SCTRL_SCCLKDIV6_REG (SCTRL_REG_BASE + 0x268) 103 104 #define SCTRL_SCPERCTRL7_REG (SCTRL_REG_BASE + 0x31C) 105 #define SCTRL_SCPERSTAT6_REG (SCTRL_REG_BASE + 0x378) 106 107 #define SCTRL_SCINNERSTAT_REG (SCTRL_REG_BASE + 0x3A0) 108 #define EMMC_UFS_SEL (1 << 15) 109 110 #define SCTRL_BAK_DATA0_REG (SCTRL_REG_BASE + 0x40C) 111 #define SCTRL_BAK_DATA4_REG (SCTRL_REG_BASE + 0x41C) 112 113 #define SCTRL_LPMCU_CLKEN_REG (SCTRL_REG_BASE + 0x480) 114 #define SCTRL_LPMCU_CLKDIS_REG (SCTRL_REG_BASE + 0x484) 115 #define SCTRL_LPMCU_RSTEN_REG (SCTRL_REG_BASE + 0x500) 116 #define SCTRL_LPMCU_RSTDIS_REG (SCTRL_REG_BASE + 0x504) 117 #define DDRC_SOFT_BIT (1 << 6) 118 #define DDRC_CLK_BIT (1 << 5) 119 120 #define SCTRL_SCPEREN0_SEC_REG (SCTRL_REG_BASE + 0x900) 121 #define SCTRL_SCPERDIS0_SEC_REG (SCTRL_REG_BASE + 0x904) 122 #define MMBUF_SEC_CTRL_MASK (0xfff << 20) 123 #define MMBUF_SEC_CTRL(x) (((x) & 0xfff) << 20) 124 125 #define SCTRL_PERRSTEN1_SEC_REG (SCTRL_REG_BASE + 0xA50) 126 #define SCTRL_PERRSTDIS1_SEC_REG (SCTRL_REG_BASE + 0xA54) 127 #define SCTRL_PERRSTSTAT1_SEC_REG (SCTRL_REG_BASE + 0xA58) 128 #define RST_ASP_SUBSYS_BIT (1 << 0) 129 130 #define SCTRL_PERRSTEN2_SEC_REG (SCTRL_REG_BASE + 0xB50) 131 #define SCTRL_PERRSTDIS2_SEC_REG (SCTRL_REG_BASE + 0xB54) 132 #define SCTRL_PERRSTSTAT2_SEC_REG (SCTRL_REG_BASE + 0xB58) 133 134 #define SCTRL_HISEECLKDIV_REG (SCTRL_REG_BASE + 0xC28) 135 #define SC_SEL_HISEE_PLL_MASK (1 << 4) 136 #define SC_SEL_HISEE_PLL0 (1 << 4) 137 #define SC_SEL_HISEE_PLL2 (0 << 4) 138 #define SC_DIV_HISEE_PLL_MASK (7 << 16) 139 #define SC_DIV_HISEE_PLL(x) ((x) & 0x7) 140 141 #define SCTRL_SCSOCID0_REG (SCTRL_REG_BASE + 0xE00) 142 143 #define PMC_REG_BASE 0xFFF31000 144 #define PMC_PPLL1_CTRL0_REG (PMC_REG_BASE + 0x038) 145 #define PMC_PPLL1_CTRL1_REG (PMC_REG_BASE + 0x03C) 146 #define PMC_PPLL2_CTRL0_REG (PMC_REG_BASE + 0x040) 147 #define PMC_PPLL2_CTRL1_REG (PMC_REG_BASE + 0x044) 148 #define PMC_PPLL3_CTRL0_REG (PMC_REG_BASE + 0x048) 149 #define PMC_PPLL3_CTRL1_REG (PMC_REG_BASE + 0x04C) 150 #define PPLLx_LOCK (1 << 26) 151 #define PPLLx_WITHOUT_CLK_GATE (1 << 26) 152 #define PPLLx_CFG_VLD (1 << 25) 153 #define PPLLx_INT_MOD (1 << 24) 154 #define PPLLx_POSTDIV2_MASK (0x7 << 23) 155 #define PPLLx_POSTDIV2(x) (((x) & 0x7) << 23) 156 #define PPLLx_POSTDIV1_MASK (0x7 << 20) 157 #define PPLLx_POSTDIV1(x) (((x) & 0x7) << 20) 158 #define PPLLx_FRACDIV_MASK (0x00FFFFFF) 159 #define PPLLx_FRACDIV(x) ((x) & 0x00FFFFFF) 160 #define PPLLx_FBDIV_MASK (0xfff << 8) 161 #define PPLLx_FBDIV(x) (((x) & 0xfff) << 8) 162 #define PPLLx_REFDIV_MASK (0x3f << 2) 163 #define PPLLx_REFDIV(x) (((x) & 0x3f) << 2) 164 #define PPLLx_BP (1 << 1) 165 #define PPLLx_EN (1 << 0) 166 167 #define PMC_DDRLP_CTRL_REG (PMC_REG_BASE + 0x30C) 168 #define DDRC_CSYSREQ_CFG(x) ((x) & 0xF) 169 170 #define PMC_NOC_POWER_IDLEREQ_REG (PMC_REG_BASE + 0x380) 171 #define PMC_NOC_POWER_IDLEREQ_IVP (1 << 14) 172 #define PMC_NOC_POWER_IDLEREQ_DSS (1 << 13) 173 #define PMC_NOC_POWER_IDLEREQ_VENC (1 << 11) 174 #define PMC_NOC_POWER_IDLEREQ_VDEC (1 << 10) 175 #define PMC_NOC_POWER_IDLEREQ_ISP (1 << 5) 176 #define PMC_NOC_POWER_IDLEREQ_VCODEC (1 << 4) 177 #define DDRPHY_BYPASS_MODE (1 << 0) 178 179 #define PMC_NOC_POWER_IDLEACK_REG (PMC_REG_BASE + 0x384) 180 #define PMC_NOC_POWER_IDLE_REG (PMC_REG_BASE + 0x388) 181 182 #define PMU_SSI0_REG_BASE 0xFFF34000 183 184 #define PMU_SSI0_LDO8_CTRL0_REG (PMU_SSI0_REG_BASE + (0x68 << 2)) 185 #define LDO8_CTRL0_EN_1_8V 0x02 186 187 #define PMU_SSI0_CLK_TOP_CTRL7_REG (PMU_SSI0_REG_BASE + (0x10C << 2)) 188 #define NP_XO_ABB_DIG (1 << 1) 189 190 #define LP_CONFIG_REG_BASE 0xFFF3F000 191 192 #define DMAC_BASE 0xFDF30000 193 194 #define CCI400_REG_BASE 0xE8100000 195 #define CCI400_SL_IFACE3_CLUSTER_IX 0 196 #define CCI400_SL_IFACE4_CLUSTER_IX 1 197 198 #define GICD_REG_BASE 0xE82B1000 199 #define GICC_REG_BASE 0xE82B2000 200 /* 201 * GIC400 interrupt handling related constants 202 */ 203 #define IRQ_SEC_PHY_TIMER 29 204 #define IRQ_SEC_SGI_0 8 205 #define IRQ_SEC_SGI_1 9 206 #define IRQ_SEC_SGI_2 10 207 #define IRQ_SEC_SGI_3 11 208 #define IRQ_SEC_SGI_4 12 209 #define IRQ_SEC_SGI_5 13 210 #define IRQ_SEC_SGI_6 14 211 #define IRQ_SEC_SGI_7 15 212 #define IRQ_SEC_SGI_8 16 213 214 #define IPC_REG_BASE 0xE896A000 215 #define IPC_BASE (IPC_REG_BASE) 216 217 #define IOMG_REG_BASE 0xE896C000 218 219 /* GPIO46: HUB 3.3V enable. active low */ 220 #define IOMG_044_REG (IOMG_REG_BASE + 0x0B0) 221 #define IOMG_UART5_RX_REG (IOMG_REG_BASE + 0x0BC) 222 #define IOMG_UART5_TX_REG (IOMG_REG_BASE + 0x0C0) 223 224 #define IOCG_REG_BASE 0xE896C800 225 226 /* GPIO005: PMIC SSI. (2 << 4) */ 227 #define IOCG_006_REG (IOCG_REG_BASE + 0x018) 228 229 #define TIMER9_REG_BASE 0xE8A00000 230 231 #define WDT0_REG_BASE 0xE8A06000 232 #define WDT1_REG_BASE 0xE8A07000 233 #define WDT_CONTROL_OFFSET 0x008 234 #define WDT_LOCK_OFFSET 0xC00 235 236 #define WDT_UNLOCK 0x1ACCE551 237 #define WDT_LOCKED 1 238 239 #define PCTRL_REG_BASE 0xE8A09000 240 #define PCTRL_PERI_CTRL3_REG (PCTRL_REG_BASE + 0x010) 241 #define PCTRL_PERI_CTRL24_REG (PCTRL_REG_BASE + 0x064) 242 243 #define GPIO0_BASE UL(0xE8A0B000) 244 #define GPIO1_BASE UL(0xE8A0C000) 245 #define GPIO2_BASE UL(0xE8A0D000) 246 #define GPIO3_BASE UL(0xE8A0E000) 247 #define GPIO4_BASE UL(0xE8A0F000) 248 #define GPIO5_BASE UL(0xE8A10000) 249 #define GPIO6_BASE UL(0xE8A11000) 250 #define GPIO7_BASE UL(0xE8A12000) 251 #define GPIO8_BASE UL(0xE8A13000) 252 #define GPIO9_BASE UL(0xE8A14000) 253 #define GPIO10_BASE UL(0xE8A15000) 254 #define GPIO11_BASE UL(0xE8A16000) 255 #define GPIO12_BASE UL(0xE8A17000) 256 #define GPIO13_BASE UL(0xE8A18000) 257 #define GPIO14_BASE UL(0xE8A19000) 258 #define GPIO15_BASE UL(0xE8A1A000) 259 #define GPIO16_BASE UL(0xE8A1B000) 260 #define GPIO17_BASE UL(0xE8A1C000) 261 #define GPIO20_BASE UL(0xE8A1F000) 262 #define GPIO21_BASE UL(0xE8A20000) 263 264 #define TZC_REG_BASE 0xE8A21000 265 #define TZC_STAT0_REG (TZC_REG_BASE + 0x800) 266 #define TZC_EN0_REG (TZC_REG_BASE + 0x804) 267 #define TZC_DIS0_REG (TZC_REG_BASE + 0x808) 268 #define TZC_STAT1_REG (TZC_REG_BASE + 0x80C) 269 #define TZC_EN1_REG (TZC_REG_BASE + 0x810) 270 #define TZC_DIS1_REG (TZC_REG_BASE + 0x814) 271 #define TZC_STAT2_REG (TZC_REG_BASE + 0x818) 272 #define TZC_EN2_REG (TZC_REG_BASE + 0x81C) 273 #define TZC_DIS2_REG (TZC_REG_BASE + 0x820) 274 #define TZC_STAT3_REG (TZC_REG_BASE + 0x824) 275 #define TZC_EN3_REG (TZC_REG_BASE + 0x828) 276 #define TZC_DIS3_REG (TZC_REG_BASE + 0x82C) 277 #define TZC_STAT4_REG (TZC_REG_BASE + 0x830) 278 #define TZC_EN4_REG (TZC_REG_BASE + 0x834) 279 #define TZC_DIS4_REG (TZC_REG_BASE + 0x838) 280 #define TZC_STAT5_REG (TZC_REG_BASE + 0x83C) 281 #define TZC_EN5_REG (TZC_REG_BASE + 0x840) 282 #define TZC_DIS5_REG (TZC_REG_BASE + 0x844) 283 #define TZC_STAT6_REG (TZC_REG_BASE + 0x848) 284 #define TZC_EN6_REG (TZC_REG_BASE + 0x84C) 285 #define TZC_DIS6_REG (TZC_REG_BASE + 0x850) 286 #define TZC_STAT7_REG (TZC_REG_BASE + 0x854) 287 #define TZC_EN7_REG (TZC_REG_BASE + 0x858) 288 #define TZC_DIS7_REG (TZC_REG_BASE + 0x85C) 289 #define TZC_STAT8_REG (TZC_REG_BASE + 0x860) 290 #define TZC_EN8_REG (TZC_REG_BASE + 0x864) 291 #define TZC_DIS8_REG (TZC_REG_BASE + 0x868) 292 293 #define MMBUF_BASE 0xEA800000 294 295 #define ACPU_DMCPACK0_BASE 0xEA900000 296 297 #define ACPU_DMCPACK1_BASE 0xEA920000 298 299 #define ACPU_DMCPACK2_BASE 0xEA940000 300 301 #define ACPU_DMCPACK3_BASE 0xEA960000 302 303 #define UART5_REG_BASE 0xFDF05000 304 305 #define USB3OTG_REG_BASE 0xFF100000 306 307 #define UFS_REG_BASE 0xFF3B0000 308 309 #define UFS_SYS_REG_BASE 0xFF3B1000 310 311 #define UFS_SYS_PSW_POWER_CTRL_REG (UFS_SYS_REG_BASE + 0x004) 312 #define UFS_SYS_PHY_ISO_EN_REG (UFS_SYS_REG_BASE + 0x008) 313 #define UFS_SYS_HC_LP_CTRL_REG (UFS_SYS_REG_BASE + 0x00C) 314 #define UFS_SYS_PHY_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x010) 315 #define UFS_SYS_PSW_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x014) 316 #define UFS_SYS_CLOCK_GATE_BYPASS_REG (UFS_SYS_REG_BASE + 0x018) 317 #define UFS_SYS_RESET_CTRL_EN_REG (UFS_SYS_REG_BASE + 0x01C) 318 #define UFS_SYS_MONITOR_HH_REG (UFS_SYS_REG_BASE + 0x03C) 319 #define UFS_SYS_UFS_SYSCTRL_REG (UFS_SYS_REG_BASE + 0x05C) 320 #define UFS_SYS_UFS_DEVICE_RESET_CTRL_REG (UFS_SYS_REG_BASE + 0x060) 321 #define UFS_SYS_UFS_APB_ADDR_MASK_REG (UFS_SYS_REG_BASE + 0x064) 322 323 #define BIT_UFS_PSW_ISO_CTRL (1 << 16) 324 #define BIT_UFS_PSW_MTCMOS_EN (1 << 0) 325 #define BIT_UFS_REFCLK_ISO_EN (1 << 16) 326 #define BIT_UFS_PHY_ISO_CTRL (1 << 0) 327 #define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) 328 #define BIT_SYSCTRL_PWR_READY (1 << 8) 329 #define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) 330 #define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8) 331 #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) 332 #define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) 333 #define MASK_UFS_CLK_GATE_BYPASS (0x3F) 334 #define BIT_SYSCTRL_LP_RESET_N (1 << 0) 335 #define BIT_UFS_REFCLK_SRC_SE1 (1 << 0) 336 #define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16) 337 #define MASK_UFS_DEVICE_RESET (1 << 16) 338 #define BIT_UFS_DEVICE_RESET (1 << 0) 339 340 #define GPIO18_BASE UL(0xFF3B4000) 341 #define GPIO19_BASE UL(0xFF3B5000) 342 343 #define IOMG_FIX_REG_BASE 0xFF3B6000 344 345 /* GPIO150: LED */ 346 #define IOMG_FIX_006_REG (IOMG_FIX_REG_BASE + 0x018) 347 /* GPIO151: LED */ 348 #define IOMG_FIX_007_REG (IOMG_FIX_REG_BASE + 0x01C) 349 350 #define IOMG_AO_REG_BASE 0xFFF11000 351 352 /* GPIO189: LED */ 353 #define IOMG_AO_011_REG (IOMG_AO_REG_BASE + 0x02C) 354 /* GPIO190: LED */ 355 #define IOMG_AO_012_REG (IOMG_AO_REG_BASE + 0x030) 356 /* GPIO202: type C enable. active low */ 357 #define IOMG_AO_023_REG (IOMG_AO_REG_BASE + 0x05C) 358 /* GPIO206: USB switch. active low */ 359 #define IOMG_AO_026_REG (IOMG_AO_REG_BASE + 0x068) 360 /* GPIO219: PD interrupt. pull up */ 361 #define IOMG_AO_039_REG (IOMG_AO_REG_BASE + 0x09C) 362 /* GPIO213: PCIE_CLKREQ_N */ 363 #define IOMG_AO_033_REG (IOMG_AO_REG_BASE + 0x084) 364 365 #define IOCG_AO_REG_BASE 0xFFF1187C 366 /* GPIO219: PD interrupt. pull up */ 367 #define IOCG_AO_043_REG (IOCG_AO_REG_BASE + 0x030) 368 369 #define EDMAC_BASE 0xfdf30000 370 #define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694) 371 #define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6)) 372 #define EDMAC_SEC_CTRL_INTR_SEC (1 << 1) 373 #define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0) 374 #define EDMAC_CHANNEL_NUMS 16 375 376 #define IOMCU_DMAC_BASE 0xffd77000 377 #define IOMCU_DMAC_SEC_CTRL (IOMCU_DMAC_BASE + 0x694) 378 #define IOMCU_DMAC_AXI_CONF(x) (IOMCU_DMAC_BASE + 0x820 + ((x) << 6)) 379 #define IOMCU_DMAC_AXI_CONF_ARPROT_NS (1 << 6) 380 #define IOMCU_DMAC_AXI_CONF_AWPROT_NS (1 << 18) 381 #define IOMCU_DMAC_SEC_CTRL_INTR_SEC (1 << 1) 382 #define IOMCU_DMAC_SEC_CTRL_GLOBAL_SEC (1 << 0) 383 #define IOMCU_DMAC_CHANNEL_NUMS 8 384 385 #endif /* HI3660_H */ 386