1 /** @file 2 IA32 Local APIC Definitions. 3 4 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> 5 This program and the accompanying materials 6 are licensed and made available under the terms and conditions of the BSD License 7 which accompanies this distribution. The full text of the license may be found at 8 http://opensource.org/licenses/bsd-license.php 9 10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 13 **/ 14 15 #ifndef __LOCAL_APIC_H__ 16 #define __LOCAL_APIC_H__ 17 18 // 19 // Definition for Local APIC registers and related values 20 // 21 #define XAPIC_ID_OFFSET 0x20 22 #define XAPIC_VERSION_OFFSET 0x30 23 #define XAPIC_EOI_OFFSET 0x0b0 24 #define XAPIC_ICR_DFR_OFFSET 0x0e0 25 #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0 26 #define XAPIC_ICR_LOW_OFFSET 0x300 27 #define XAPIC_ICR_HIGH_OFFSET 0x310 28 #define XAPIC_LVT_TIMER_OFFSET 0x320 29 #define XAPIC_LVT_LINT0_OFFSET 0x350 30 #define XAPIC_LVT_LINT1_OFFSET 0x360 31 #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380 32 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390 33 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0 34 35 #define X2APIC_MSR_BASE_ADDRESS 0x800 36 #define X2APIC_MSR_ICR_ADDRESS 0x830 37 38 #define LOCAL_APIC_DELIVERY_MODE_FIXED 0 39 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1 40 #define LOCAL_APIC_DELIVERY_MODE_SMI 2 41 #define LOCAL_APIC_DELIVERY_MODE_NMI 4 42 #define LOCAL_APIC_DELIVERY_MODE_INIT 5 43 #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6 44 #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7 45 46 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0 47 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1 48 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2 49 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3 50 51 // 52 // Local APIC Version Register. 53 // 54 typedef union { 55 struct { 56 UINT32 Version:8; ///< The version numbers of the local APIC. 57 UINT32 Reserved0:8; ///< Reserved. 58 UINT32 MaxLvtEntry:8; ///< Number of LVT entries minus 1. 59 UINT32 EoiBroadcastSuppression:1; ///< 1 if EOI-broadcast suppression supported. 60 UINT32 Reserved1:7; ///< Reserved. 61 } Bits; 62 UINT32 Uint32; 63 } LOCAL_APIC_VERSION; 64 65 // 66 // Low half of Interrupt Command Register (ICR). 67 // 68 typedef union { 69 struct { 70 UINT32 Vector:8; ///< The vector number of the interrupt being sent. 71 UINT32 DeliveryMode:3; ///< Specifies the type of IPI to be sent. 72 UINT32 DestinationMode:1; ///< 0: physical destination mode, 1: logical destination mode. 73 UINT32 DeliveryStatus:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode. 74 UINT32 Reserved0:1; ///< Reserved. 75 UINT32 Level:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1. 76 UINT32 TriggerMode:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode. 77 UINT32 Reserved1:2; ///< Reserved. 78 UINT32 DestinationShorthand:2; ///< A shorthand notation to specify the destination of the interrupt. 79 UINT32 Reserved2:12; ///< Reserved. 80 } Bits; 81 UINT32 Uint32; 82 } LOCAL_APIC_ICR_LOW; 83 84 // 85 // High half of Interrupt Command Register (ICR) 86 // 87 typedef union { 88 struct { 89 UINT32 Reserved0:24; ///< Reserved. 90 UINT32 Destination:8; ///< Specifies the target processor or processors in xAPIC mode. 91 } Bits; 92 UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode. 93 } LOCAL_APIC_ICR_HIGH; 94 95 // 96 // Spurious-Interrupt Vector Register (SVR) 97 // 98 typedef union { 99 struct { 100 UINT32 SpuriousVector:8; ///< Spurious Vector. 101 UINT32 SoftwareEnable:1; ///< APIC Software Enable/Disable. 102 UINT32 FocusProcessorChecking:1; ///< Focus Processor Checking. 103 UINT32 Reserved0:2; ///< Reserved. 104 UINT32 EoiBroadcastSuppression:1; ///< EOI-Broadcast Suppression. 105 UINT32 Reserved1:19; ///< Reserved. 106 } Bits; 107 UINT32 Uint32; 108 } LOCAL_APIC_SVR; 109 110 // 111 // Divide Configuration Register (DCR) 112 // 113 typedef union { 114 struct { 115 UINT32 DivideValue1:2; ///< Low 2 bits of the divide value. 116 UINT32 Reserved0:1; ///< Always 0. 117 UINT32 DivideValue2:1; ///< Highest 1 bit of the divide value. 118 UINT32 Reserved1:28; ///< Reserved. 119 } Bits; 120 UINT32 Uint32; 121 } LOCAL_APIC_DCR; 122 123 // 124 // LVT Timer Register 125 // 126 typedef union { 127 struct { 128 UINT32 Vector:8; ///< The vector number of the interrupt being sent. 129 UINT32 Reserved0:4; ///< Reserved. 130 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. 131 UINT32 Reserved1:3; ///< Reserved. 132 UINT32 Mask:1; ///< 0: Not masked, 1: Masked. 133 UINT32 TimerMode:1; ///< 0: One-shot, 1: Periodic. 134 UINT32 Reserved2:14; ///< Reserved. 135 } Bits; 136 UINT32 Uint32; 137 } LOCAL_APIC_LVT_TIMER; 138 139 // 140 // LVT LINT0/LINT1 Register 141 // 142 typedef union { 143 struct { 144 UINT32 Vector:8; ///< The vector number of the interrupt being sent. 145 UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. 146 UINT32 Reserved0:1; ///< Reserved. 147 UINT32 DeliveryStatus:1; ///< 0: Idle, 1: send pending. 148 UINT32 InputPinPolarity:1; ///< Interrupt Input Pin Polarity. 149 UINT32 RemoteIrr:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received. 150 UINT32 TriggerMode:1; ///< 0:edge, 1:level. 151 UINT32 Mask:1; ///< 0: Not masked, 1: Masked. 152 UINT32 Reserved1:15; ///< Reserved. 153 } Bits; 154 UINT32 Uint32; 155 } LOCAL_APIC_LVT_LINT; 156 157 // 158 // MSI Address Register 159 // 160 typedef union { 161 struct { 162 UINT32 Reserved0:2; ///< Reserved 163 UINT32 DestinationMode:1; ///< Specifies the Destination Mode. 164 UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint. 165 UINT32 Reserved1:8; ///< Reserved. 166 UINT32 DestinationId:8; ///< Specifies the Destination ID. 167 UINT32 BaseAddress:12; ///< Must be 0FEEH 168 } Bits; 169 UINT32 Uint32; 170 } LOCAL_APIC_MSI_ADDRESS; 171 172 // 173 // MSI Address Register 174 // 175 typedef union { 176 struct { 177 UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH 178 UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent. 179 UINT32 Reserved0:3; ///< Reserved. 180 UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts. 181 UINT32 TriggerMode:1; ///< 0:Edge, 1:Level. 182 UINT32 Reserved1:16; ///< Reserved. 183 UINT32 Reserved2:32; ///< Reserved. 184 } Bits; 185 UINT64 Uint64; 186 } LOCAL_APIC_MSI_DATA; 187 188 #endif 189 190