1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_SYS_PROTO_H 8 #define _ASM_ARCH_SYS_PROTO_H 9 10 #define PAYLOAD_ARG_CNT 5 11 12 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF 13 #define KEY_PTR_LEN 32 14 15 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1 16 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2 17 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3 18 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4 19 #define ZYNQMP_FPGA_BIT_NS 5 20 21 #define ZYNQMP_FPGA_AUTH_DDR 1 22 23 enum { 24 IDCODE, 25 VERSION, 26 IDCODE2, 27 }; 28 29 enum { 30 ZYNQMP_SILICON_V1, 31 ZYNQMP_SILICON_V2, 32 ZYNQMP_SILICON_V3, 33 ZYNQMP_SILICON_V4, 34 }; 35 36 enum { 37 TCM_LOCK, 38 TCM_SPLIT, 39 }; 40 41 struct zynqmp_ipi_msg { 42 size_t len; 43 u32 *buf; 44 }; 45 46 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); 47 unsigned int zynqmp_get_silicon_version(void); 48 49 void handoff_setup(void); 50 51 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); 52 int zynqmp_mmio_read(const u32 address, u32 *value); 53 54 void initialize_tcm(bool mode); 55 void mem_map_fill(void); 56 int chip_id(unsigned char id); 57 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) 58 void tcm_init(u8 mode); 59 #endif 60 61 #endif /* _ASM_ARCH_SYS_PROTO_H */ 62