1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 12OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 13ENTRY(bl1_entrypoint) 14 15MEMORY { 16 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE 17 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE 18} 19 20SECTIONS 21{ 22 . = BL1_RO_BASE; 23 ASSERT(. == ALIGN(PAGE_SIZE), 24 "BL1_RO_BASE address is not aligned on a page boundary.") 25 26#if SEPARATE_CODE_AND_RODATA 27 .text . : { 28 __TEXT_START__ = .; 29 *bl1_entrypoint.o(.text*) 30 *(SORT_BY_ALIGNMENT(.text*)) 31 *(.vectors) 32 . = ALIGN(PAGE_SIZE); 33 __TEXT_END__ = .; 34 } >ROM 35 36 /* .ARM.extab and .ARM.exidx are only added because Clang need them */ 37 .ARM.extab . : { 38 *(.ARM.extab* .gnu.linkonce.armextab.*) 39 } >ROM 40 41 .ARM.exidx . : { 42 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 43 } >ROM 44 45 .rodata . : { 46 __RODATA_START__ = .; 47 *(SORT_BY_ALIGNMENT(.rodata*)) 48 49 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 50 . = ALIGN(8); 51 __PARSER_LIB_DESCS_START__ = .; 52 KEEP(*(.img_parser_lib_descs)) 53 __PARSER_LIB_DESCS_END__ = .; 54 55 /* 56 * Ensure 8-byte alignment for cpu_ops so that its fields are also 57 * aligned. Also ensure cpu_ops inclusion. 58 */ 59 . = ALIGN(8); 60 __CPU_OPS_START__ = .; 61 KEEP(*(cpu_ops)) 62 __CPU_OPS_END__ = .; 63 64 /* 65 * No need to pad out the .rodata section to a page boundary. Next is 66 * the .data section, which can mapped in ROM with the same memory 67 * attributes as the .rodata section. 68 */ 69 __RODATA_END__ = .; 70 } >ROM 71#else 72 ro . : { 73 __RO_START__ = .; 74 *bl1_entrypoint.o(.text*) 75 *(SORT_BY_ALIGNMENT(.text*)) 76 *(SORT_BY_ALIGNMENT(.rodata*)) 77 78 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 79 . = ALIGN(8); 80 __PARSER_LIB_DESCS_START__ = .; 81 KEEP(*(.img_parser_lib_descs)) 82 __PARSER_LIB_DESCS_END__ = .; 83 84 /* 85 * Ensure 8-byte alignment for cpu_ops so that its fields are also 86 * aligned. Also ensure cpu_ops inclusion. 87 */ 88 . = ALIGN(8); 89 __CPU_OPS_START__ = .; 90 KEEP(*(cpu_ops)) 91 __CPU_OPS_END__ = .; 92 93 *(.vectors) 94 __RO_END__ = .; 95 } >ROM 96#endif 97 98 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 99 "cpu_ops not defined for this platform.") 100 101 . = BL1_RW_BASE; 102 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), 103 "BL1_RW_BASE address is not aligned on a page boundary.") 104 105 /* 106 * The .data section gets copied from ROM to RAM at runtime. 107 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes 108 * aligned regions in it. 109 * Its VMA must be page-aligned as it marks the first read/write page. 110 * 111 * It must be placed at a lower address than the stacks if the stack 112 * protector is enabled. Alternatively, the .data.stack_protector_canary 113 * section can be placed independently of the main .data section. 114 */ 115 .data . : ALIGN(16) { 116 __DATA_RAM_START__ = .; 117 *(SORT_BY_ALIGNMENT(.data*)) 118 __DATA_RAM_END__ = .; 119 } >RAM AT>ROM 120 121 stacks . (NOLOAD) : { 122 __STACKS_START__ = .; 123 *(tzfw_normal_stacks) 124 __STACKS_END__ = .; 125 } >RAM 126 127 /* 128 * The .bss section gets initialised to 0 at runtime. 129 * Its base address should be 16-byte aligned for better performance of the 130 * zero-initialization code. 131 */ 132 .bss : ALIGN(16) { 133 __BSS_START__ = .; 134 *(SORT_BY_ALIGNMENT(.bss*)) 135 *(COMMON) 136 __BSS_END__ = .; 137 } >RAM 138 139 /* 140 * The xlat_table section is for full, aligned page tables (4K). 141 * Removing them from .bss avoids forcing 4K alignment on 142 * the .bss section. The tables are initialized to zero by the translation 143 * tables library. 144 */ 145 xlat_table (NOLOAD) : { 146 *(xlat_table) 147 } >RAM 148 149#if USE_COHERENT_MEM 150 /* 151 * The base address of the coherent memory section must be page-aligned (4K) 152 * to guarantee that the coherent data are stored on their own pages and 153 * are not mixed with normal data. This is required to set up the correct 154 * memory attributes for the coherent data page tables. 155 */ 156 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 157 __COHERENT_RAM_START__ = .; 158 *(tzfw_coherent_mem) 159 __COHERENT_RAM_END_UNALIGNED__ = .; 160 /* 161 * Memory page(s) mapped to this section will be marked 162 * as device memory. No other unexpected data must creep in. 163 * Ensure the rest of the current memory page is unused. 164 */ 165 . = ALIGN(PAGE_SIZE); 166 __COHERENT_RAM_END__ = .; 167 } >RAM 168#endif 169 170 __BL1_RAM_START__ = ADDR(.data); 171 __BL1_RAM_END__ = .; 172 173 __DATA_ROM_START__ = LOADADDR(.data); 174 __DATA_SIZE__ = SIZEOF(.data); 175 176 /* 177 * The .data section is the last PROGBITS section so its end marks the end 178 * of BL1's actual content in Trusted ROM. 179 */ 180 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; 181 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, 182 "BL1's ROM content has exceeded its limit.") 183 184 __BSS_SIZE__ = SIZEOF(.bss); 185 186#if USE_COHERENT_MEM 187 __COHERENT_RAM_UNALIGNED_SIZE__ = 188 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 189#endif 190 191 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") 192} 193