1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <acpi_s3.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <rtc.h> 11 #include <asm/cmos_layout.h> 12 #include <asm/early_cmos.h> 13 #include <asm/io.h> 14 #include <asm/mrccache.h> 15 #include <asm/post.h> 16 #include <asm/processor.h> 17 #include <asm/fsp1/fsp_support.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 arch_fsp_init(void)21int arch_fsp_init(void) 22 { 23 void *nvs; 24 int stack = CONFIG_FSP_TEMP_RAM_ADDR; 25 int boot_mode = BOOT_FULL_CONFIG; 26 #ifdef CONFIG_HAVE_ACPI_RESUME 27 int prev_sleep_state = chipset_prev_sleep_state(); 28 gd->arch.prev_sleep_state = prev_sleep_state; 29 #endif 30 31 if (!gd->arch.hob_list) { 32 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) 33 nvs = fsp_prepare_mrc_cache(); 34 else 35 nvs = NULL; 36 37 #ifdef CONFIG_HAVE_ACPI_RESUME 38 if (prev_sleep_state == ACPI_S3) { 39 if (nvs == NULL) { 40 /* If waking from S3 and no cache then */ 41 debug("No MRC cache found in S3 resume path\n"); 42 post_code(POST_RESUME_FAILURE); 43 /* Clear Sleep Type */ 44 chipset_clear_sleep_state(); 45 /* Reboot */ 46 debug("Rebooting..\n"); 47 outb(SYS_RST | RST_CPU, IO_PORT_RESET); 48 /* Should not reach here.. */ 49 panic("Reboot System"); 50 } 51 52 /* 53 * DM is not available yet at this point, hence call 54 * CMOS access library which does not depend on DM. 55 */ 56 stack = cmos_read32(CMOS_FSP_STACK_ADDR); 57 boot_mode = BOOT_ON_S3_RESUME; 58 } 59 #endif 60 /* 61 * The first time we enter here, call fsp_init(). 62 * Note the execution does not return to this function, 63 * instead it jumps to fsp_continue(). 64 */ 65 fsp_init(stack, boot_mode, nvs); 66 } else { 67 /* 68 * The second time we enter here, adjust the size of malloc() 69 * pool before relocation. Given gd->malloc_base was adjusted 70 * after the call to board_init_f_init_reserve() in arch/x86/ 71 * cpu/start.S, we should fix up gd->malloc_limit here. 72 */ 73 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; 74 } 75 76 return 0; 77 } 78