1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <lib/psci/psci.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 17 /* Allow ARM Standard platforms to override these functions */ 18 #pragma weak plat_arm_program_trusted_mailbox 19 20 #if !ARM_RECOM_STATE_ID_ENC 21 /******************************************************************************* 22 * ARM standard platform handler called to check the validity of the power state 23 * parameter. 24 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)25int arm_validate_power_state(unsigned int power_state, 26 psci_power_state_t *req_state) 27 { 28 unsigned int pstate = psci_get_pstate_type(power_state); 29 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 30 unsigned int i; 31 32 assert(req_state != NULL); 33 34 if (pwr_lvl > PLAT_MAX_PWR_LVL) 35 return PSCI_E_INVALID_PARAMS; 36 37 /* Sanity check the requested state */ 38 if (pstate == PSTATE_TYPE_STANDBY) { 39 /* 40 * It's possible to enter standby only on power level 0 41 * Ignore any other power level. 42 */ 43 if (pwr_lvl != ARM_PWR_LVL0) 44 return PSCI_E_INVALID_PARAMS; 45 46 req_state->pwr_domain_state[ARM_PWR_LVL0] = 47 ARM_LOCAL_STATE_RET; 48 } else { 49 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 50 req_state->pwr_domain_state[i] = 51 ARM_LOCAL_STATE_OFF; 52 } 53 54 /* 55 * We expect the 'state id' to be zero. 56 */ 57 if (psci_get_pstate_id(power_state) != 0U) 58 return PSCI_E_INVALID_PARAMS; 59 60 return PSCI_E_SUCCESS; 61 } 62 63 #else 64 /******************************************************************************* 65 * ARM standard platform handler called to check the validity of the power 66 * state parameter. The power state parameter has to be a composite power 67 * state. 68 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)69int arm_validate_power_state(unsigned int power_state, 70 psci_power_state_t *req_state) 71 { 72 unsigned int state_id; 73 int i; 74 75 assert(req_state != NULL); 76 77 /* 78 * Currently we are using a linear search for finding the matching 79 * entry in the idle power state array. This can be made a binary 80 * search if the number of entries justify the additional complexity. 81 */ 82 for (i = 0; !!arm_pm_idle_states[i]; i++) { 83 if (power_state == arm_pm_idle_states[i]) 84 break; 85 } 86 87 /* Return error if entry not found in the idle state array */ 88 if (!arm_pm_idle_states[i]) 89 return PSCI_E_INVALID_PARAMS; 90 91 i = 0; 92 state_id = psci_get_pstate_id(power_state); 93 94 /* Parse the State ID and populate the state info parameter */ 95 while (state_id) { 96 req_state->pwr_domain_state[i++] = state_id & 97 ARM_LOCAL_PSTATE_MASK; 98 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 99 } 100 101 return PSCI_E_SUCCESS; 102 } 103 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 104 105 /******************************************************************************* 106 * ARM standard platform handler called to check the validity of the non secure 107 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 108 ******************************************************************************/ arm_validate_ns_entrypoint(uintptr_t entrypoint)109int arm_validate_ns_entrypoint(uintptr_t entrypoint) 110 { 111 /* 112 * Check if the non secure entrypoint lies within the non 113 * secure DRAM. 114 */ 115 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 116 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 117 return 0; 118 } 119 #ifdef __aarch64__ 120 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 121 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 122 return 0; 123 } 124 #endif 125 126 return -1; 127 } 128 arm_validate_psci_entrypoint(uintptr_t entrypoint)129int arm_validate_psci_entrypoint(uintptr_t entrypoint) 130 { 131 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : 132 PSCI_E_INVALID_ADDRESS; 133 } 134 135 /****************************************************************************** 136 * Helper function to save the platform state before a system suspend. Save the 137 * state of the system components which are not in the Always ON power domain. 138 *****************************************************************************/ arm_system_pwr_domain_save(void)139void arm_system_pwr_domain_save(void) 140 { 141 /* Assert system power domain is available on the platform */ 142 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 143 144 plat_arm_gic_save(); 145 146 /* 147 * Unregister console now so that it is not registered for a second 148 * time during resume. 149 */ 150 arm_console_runtime_end(); 151 152 /* 153 * All the other peripheral which are configured by ARM TF are 154 * re-initialized on resume from system suspend. Hence we 155 * don't save their state here. 156 */ 157 } 158 159 /****************************************************************************** 160 * Helper function to resume the platform from system suspend. Reinitialize 161 * the system components which are not in the Always ON power domain. 162 * TODO: Unify the platform setup when waking up from cold boot and system 163 * resume in arm_bl31_platform_setup(). 164 *****************************************************************************/ arm_system_pwr_domain_resume(void)165void arm_system_pwr_domain_resume(void) 166 { 167 /* Initialize the console */ 168 arm_console_runtime_init(); 169 170 /* Assert system power domain is available on the platform */ 171 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 172 173 plat_arm_gic_resume(); 174 175 plat_arm_security_setup(); 176 arm_configure_sys_timer(); 177 } 178 179 /******************************************************************************* 180 * ARM platform function to program the mailbox for a cpu before it is released 181 * from reset. This function assumes that the Trusted mail box base is within 182 * the ARM_SHARED_RAM region 183 ******************************************************************************/ plat_arm_program_trusted_mailbox(uintptr_t address)184void plat_arm_program_trusted_mailbox(uintptr_t address) 185 { 186 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 187 188 *mailbox = address; 189 190 /* 191 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 192 * ARM_SHARED_RAM region. 193 */ 194 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 195 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 196 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 197 } 198 199 /******************************************************************************* 200 * The ARM Standard platform definition of platform porting API 201 * `plat_setup_psci_ops`. 202 ******************************************************************************/ plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)203int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 204 const plat_psci_ops_t **psci_ops) 205 { 206 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 207 208 /* Setup mailbox with entry point. */ 209 plat_arm_program_trusted_mailbox(sec_entrypoint); 210 return 0; 211 } 212