1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
4 *
5 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6 *
7 * Copyright (C) 2005 HP Labs
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <asm/io.h>
15 #include <linux/sizes.h>
16 #include <asm/gpio.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/at91_pio.h>
19
20 #define GPIO_PER_BANK 32
21
at91_pio_get_port(unsigned port)22 static struct at91_port *at91_pio_get_port(unsigned port)
23 {
24 switch (port) {
25 case AT91_PIO_PORTA:
26 return (struct at91_port *)ATMEL_BASE_PIOA;
27 case AT91_PIO_PORTB:
28 return (struct at91_port *)ATMEL_BASE_PIOB;
29 case AT91_PIO_PORTC:
30 return (struct at91_port *)ATMEL_BASE_PIOC;
31 #if (ATMEL_PIO_PORTS > 3)
32 case AT91_PIO_PORTD:
33 return (struct at91_port *)ATMEL_BASE_PIOD;
34 #if (ATMEL_PIO_PORTS > 4)
35 case AT91_PIO_PORTE:
36 return (struct at91_port *)ATMEL_BASE_PIOE;
37 #endif
38 #endif
39 default:
40 printf("Error: at91_gpio: Fail to get PIO base!\n");
41 return NULL;
42 }
43 }
44
at91_set_port_pullup(struct at91_port * at91_port,unsigned offset,int use_pullup)45 static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
46 int use_pullup)
47 {
48 u32 mask;
49
50 mask = 1 << offset;
51 if (use_pullup)
52 writel(mask, &at91_port->puer);
53 else
54 writel(mask, &at91_port->pudr);
55 writel(mask, &at91_port->per);
56 }
57
at91_set_pio_pullup(unsigned port,unsigned pin,int use_pullup)58 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
59 {
60 struct at91_port *at91_port = at91_pio_get_port(port);
61
62 if (at91_port && (pin < GPIO_PER_BANK))
63 at91_set_port_pullup(at91_port, pin, use_pullup);
64
65 return 0;
66 }
67
68 /*
69 * mux the pin to the "GPIO" peripheral role.
70 */
at91_set_pio_periph(unsigned port,unsigned pin,int use_pullup)71 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
72 {
73 struct at91_port *at91_port = at91_pio_get_port(port);
74 u32 mask;
75
76 if (at91_port && (pin < GPIO_PER_BANK)) {
77 mask = 1 << pin;
78 writel(mask, &at91_port->idr);
79 at91_set_pio_pullup(port, pin, use_pullup);
80 writel(mask, &at91_port->per);
81 }
82
83 return 0;
84 }
85
86 /*
87 * mux the pin to the "A" internal peripheral role.
88 */
at91_set_a_periph(unsigned port,unsigned pin,int use_pullup)89 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
90 {
91 struct at91_port *at91_port = at91_pio_get_port(port);
92 u32 mask;
93
94 if (at91_port && (pin < GPIO_PER_BANK)) {
95 mask = 1 << pin;
96 writel(mask, &at91_port->idr);
97 at91_set_pio_pullup(port, pin, use_pullup);
98 writel(mask, &at91_port->mux.pio2.asr);
99 writel(mask, &at91_port->pdr);
100 }
101
102 return 0;
103 }
104
105 /*
106 * mux the pin to the "B" internal peripheral role.
107 */
at91_set_b_periph(unsigned port,unsigned pin,int use_pullup)108 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
109 {
110 struct at91_port *at91_port = at91_pio_get_port(port);
111 u32 mask;
112
113 if (at91_port && (pin < GPIO_PER_BANK)) {
114 mask = 1 << pin;
115 writel(mask, &at91_port->idr);
116 at91_set_pio_pullup(port, pin, use_pullup);
117 writel(mask, &at91_port->mux.pio2.bsr);
118 writel(mask, &at91_port->pdr);
119 }
120
121 return 0;
122 }
123
124 /*
125 * mux the pin to the "A" internal peripheral role.
126 */
at91_pio3_set_a_periph(unsigned port,unsigned pin,int use_pullup)127 int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
128 {
129 struct at91_port *at91_port = at91_pio_get_port(port);
130 u32 mask;
131
132 if (at91_port && (pin < GPIO_PER_BANK)) {
133 mask = 1 << pin;
134 writel(mask, &at91_port->idr);
135 at91_set_pio_pullup(port, pin, use_pullup);
136 writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
137 &at91_port->mux.pio3.abcdsr1);
138 writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
139 &at91_port->mux.pio3.abcdsr2);
140
141 writel(mask, &at91_port->pdr);
142 }
143
144 return 0;
145 }
146
147 /*
148 * mux the pin to the "B" internal peripheral role.
149 */
at91_pio3_set_b_periph(unsigned port,unsigned pin,int use_pullup)150 int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
151 {
152 struct at91_port *at91_port = at91_pio_get_port(port);
153 u32 mask;
154
155 if (at91_port && (pin < GPIO_PER_BANK)) {
156 mask = 1 << pin;
157 writel(mask, &at91_port->idr);
158 at91_set_pio_pullup(port, pin, use_pullup);
159 writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
160 &at91_port->mux.pio3.abcdsr1);
161 writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
162 &at91_port->mux.pio3.abcdsr2);
163
164 writel(mask, &at91_port->pdr);
165 }
166
167 return 0;
168 }
169 /*
170 * mux the pin to the "C" internal peripheral role.
171 */
at91_pio3_set_c_periph(unsigned port,unsigned pin,int use_pullup)172 int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
173 {
174 struct at91_port *at91_port = at91_pio_get_port(port);
175 u32 mask;
176
177 if (at91_port && (pin < GPIO_PER_BANK)) {
178 mask = 1 << pin;
179 writel(mask, &at91_port->idr);
180 at91_set_pio_pullup(port, pin, use_pullup);
181 writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
182 &at91_port->mux.pio3.abcdsr1);
183 writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
184 &at91_port->mux.pio3.abcdsr2);
185 writel(mask, &at91_port->pdr);
186 }
187
188 return 0;
189 }
190
191 /*
192 * mux the pin to the "D" internal peripheral role.
193 */
at91_pio3_set_d_periph(unsigned port,unsigned pin,int use_pullup)194 int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
195 {
196 struct at91_port *at91_port = at91_pio_get_port(port);
197 u32 mask;
198
199 if (at91_port && (pin < GPIO_PER_BANK)) {
200 mask = 1 << pin;
201 writel(mask, &at91_port->idr);
202 at91_set_pio_pullup(port, pin, use_pullup);
203 writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
204 &at91_port->mux.pio3.abcdsr1);
205 writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
206 &at91_port->mux.pio3.abcdsr2);
207 writel(mask, &at91_port->pdr);
208 }
209
210 return 0;
211 }
212
213 #ifdef CONFIG_DM_GPIO
at91_get_port_output(struct at91_port * at91_port,int offset)214 static bool at91_get_port_output(struct at91_port *at91_port, int offset)
215 {
216 u32 mask, val;
217
218 mask = 1 << offset;
219 val = readl(&at91_port->osr);
220 return val & mask;
221 }
222 #endif
223
at91_set_port_input(struct at91_port * at91_port,int offset,int use_pullup)224 static void at91_set_port_input(struct at91_port *at91_port, int offset,
225 int use_pullup)
226 {
227 u32 mask;
228
229 mask = 1 << offset;
230 writel(mask, &at91_port->idr);
231 at91_set_port_pullup(at91_port, offset, use_pullup);
232 writel(mask, &at91_port->odr);
233 writel(mask, &at91_port->per);
234 }
235
236 /*
237 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
238 * configure it for an input.
239 */
at91_set_pio_input(unsigned port,u32 pin,int use_pullup)240 int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
241 {
242 struct at91_port *at91_port = at91_pio_get_port(port);
243
244 if (at91_port && (pin < GPIO_PER_BANK))
245 at91_set_port_input(at91_port, pin, use_pullup);
246
247 return 0;
248 }
249
at91_set_port_output(struct at91_port * at91_port,int offset,int value)250 static void at91_set_port_output(struct at91_port *at91_port, int offset,
251 int value)
252 {
253 u32 mask;
254
255 mask = 1 << offset;
256 writel(mask, &at91_port->idr);
257 writel(mask, &at91_port->pudr);
258 if (value)
259 writel(mask, &at91_port->sodr);
260 else
261 writel(mask, &at91_port->codr);
262 writel(mask, &at91_port->oer);
263 writel(mask, &at91_port->per);
264 }
265
266 /*
267 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
268 * and configure it for an output.
269 */
at91_set_pio_output(unsigned port,u32 pin,int value)270 int at91_set_pio_output(unsigned port, u32 pin, int value)
271 {
272 struct at91_port *at91_port = at91_pio_get_port(port);
273
274 if (at91_port && (pin < GPIO_PER_BANK))
275 at91_set_port_output(at91_port, pin, value);
276
277 return 0;
278 }
279
280 /*
281 * enable/disable the glitch filter. mostly used with IRQ handling.
282 */
at91_set_pio_deglitch(unsigned port,unsigned pin,int is_on)283 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
284 {
285 struct at91_port *at91_port = at91_pio_get_port(port);
286 u32 mask;
287
288 if (at91_port && (pin < GPIO_PER_BANK)) {
289 mask = 1 << pin;
290 if (is_on)
291 writel(mask, &at91_port->ifer);
292 else
293 writel(mask, &at91_port->ifdr);
294 }
295
296 return 0;
297 }
298
299 /*
300 * enable/disable the glitch filter. mostly used with IRQ handling.
301 */
at91_pio3_set_pio_deglitch(unsigned port,unsigned pin,int is_on)302 int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
303 {
304 struct at91_port *at91_port = at91_pio_get_port(port);
305 u32 mask;
306
307 if (at91_port && (pin < GPIO_PER_BANK)) {
308 mask = 1 << pin;
309 if (is_on) {
310 writel(mask, &at91_port->mux.pio3.ifscdr);
311 writel(mask, &at91_port->ifer);
312 } else {
313 writel(mask, &at91_port->ifdr);
314 }
315 }
316
317 return 0;
318 }
319
320 /*
321 * enable/disable the debounce filter.
322 */
at91_pio3_set_pio_debounce(unsigned port,unsigned pin,int is_on,int div)323 int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
324 {
325 struct at91_port *at91_port = at91_pio_get_port(port);
326 u32 mask;
327
328 if (at91_port && (pin < GPIO_PER_BANK)) {
329 mask = 1 << pin;
330 if (is_on) {
331 writel(mask, &at91_port->mux.pio3.ifscer);
332 writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
333 writel(mask, &at91_port->ifer);
334 } else {
335 writel(mask, &at91_port->ifdr);
336 }
337 }
338
339 return 0;
340 }
341
342 /*
343 * enable/disable the pull-down.
344 * If pull-up already enabled while calling the function, we disable it.
345 */
at91_pio3_set_pio_pulldown(unsigned port,unsigned pin,int is_on)346 int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
347 {
348 struct at91_port *at91_port = at91_pio_get_port(port);
349 u32 mask;
350
351 if (at91_port && (pin < GPIO_PER_BANK)) {
352 mask = 1 << pin;
353 if (is_on) {
354 at91_set_pio_pullup(port, pin, 0);
355 writel(mask, &at91_port->mux.pio3.ppder);
356 } else
357 writel(mask, &at91_port->mux.pio3.ppddr);
358 }
359
360 return 0;
361 }
362
at91_pio3_set_pio_pullup(unsigned port,unsigned pin,int use_pullup)363 int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
364 {
365 struct at91_port *at91_port = at91_pio_get_port(port);
366
367 if (use_pullup)
368 at91_pio3_set_pio_pulldown(port, pin, 0);
369
370 if (at91_port && (pin < GPIO_PER_BANK))
371 at91_set_port_pullup(at91_port, pin, use_pullup);
372
373 return 0;
374 }
375
376 /*
377 * disable Schmitt trigger
378 */
at91_pio3_set_pio_disable_schmitt_trig(unsigned port,unsigned pin)379 int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
380 {
381 struct at91_port *at91_port = at91_pio_get_port(port);
382 u32 mask;
383
384 if (at91_port && (pin < GPIO_PER_BANK)) {
385 mask = 1 << pin;
386 writel(readl(&at91_port->schmitt) | mask,
387 &at91_port->schmitt);
388 }
389
390 return 0;
391 }
392
393 /*
394 * enable/disable the multi-driver. This is only valid for output and
395 * allows the output pin to run as an open collector output.
396 */
at91_set_pio_multi_drive(unsigned port,unsigned pin,int is_on)397 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
398 {
399 struct at91_port *at91_port = at91_pio_get_port(port);
400 u32 mask;
401
402 if (at91_port && (pin < GPIO_PER_BANK)) {
403 mask = 1 << pin;
404 if (is_on)
405 writel(mask, &at91_port->mder);
406 else
407 writel(mask, &at91_port->mddr);
408 }
409
410 return 0;
411 }
412
at91_set_port_value(struct at91_port * at91_port,int offset,int value)413 static void at91_set_port_value(struct at91_port *at91_port, int offset,
414 int value)
415 {
416 u32 mask;
417
418 mask = 1 << offset;
419 if (value)
420 writel(mask, &at91_port->sodr);
421 else
422 writel(mask, &at91_port->codr);
423 }
424
425 /*
426 * assuming the pin is muxed as a gpio output, set its value.
427 */
at91_set_pio_value(unsigned port,unsigned pin,int value)428 int at91_set_pio_value(unsigned port, unsigned pin, int value)
429 {
430 struct at91_port *at91_port = at91_pio_get_port(port);
431
432 if (at91_port && (pin < GPIO_PER_BANK))
433 at91_set_port_value(at91_port, pin, value);
434
435 return 0;
436 }
437
at91_get_port_value(struct at91_port * at91_port,int offset)438 static int at91_get_port_value(struct at91_port *at91_port, int offset)
439 {
440 u32 pdsr = 0, mask;
441
442 mask = 1 << offset;
443 pdsr = readl(&at91_port->pdsr) & mask;
444
445 return pdsr != 0;
446 }
447 /*
448 * read the pin's value (works even if it's not muxed as a gpio).
449 */
at91_get_pio_value(unsigned port,unsigned pin)450 int at91_get_pio_value(unsigned port, unsigned pin)
451 {
452 struct at91_port *at91_port = at91_pio_get_port(port);
453
454 if (at91_port && (pin < GPIO_PER_BANK))
455 return at91_get_port_value(at91_port, pin);
456
457 return 0;
458 }
459
460 #ifndef CONFIG_DM_GPIO
461 /* Common GPIO API */
462
gpio_request(unsigned gpio,const char * label)463 int gpio_request(unsigned gpio, const char *label)
464 {
465 return 0;
466 }
467
gpio_free(unsigned gpio)468 int gpio_free(unsigned gpio)
469 {
470 return 0;
471 }
472
gpio_direction_input(unsigned gpio)473 int gpio_direction_input(unsigned gpio)
474 {
475 at91_set_pio_input(at91_gpio_to_port(gpio),
476 at91_gpio_to_pin(gpio), 0);
477 return 0;
478 }
479
gpio_direction_output(unsigned gpio,int value)480 int gpio_direction_output(unsigned gpio, int value)
481 {
482 at91_set_pio_output(at91_gpio_to_port(gpio),
483 at91_gpio_to_pin(gpio), value);
484 return 0;
485 }
486
gpio_get_value(unsigned gpio)487 int gpio_get_value(unsigned gpio)
488 {
489 return at91_get_pio_value(at91_gpio_to_port(gpio),
490 at91_gpio_to_pin(gpio));
491 }
492
gpio_set_value(unsigned gpio,int value)493 int gpio_set_value(unsigned gpio, int value)
494 {
495 at91_set_pio_value(at91_gpio_to_port(gpio),
496 at91_gpio_to_pin(gpio), value);
497
498 return 0;
499 }
500 #endif
501
502 #ifdef CONFIG_DM_GPIO
503
504 struct at91_port_priv {
505 struct at91_port *regs;
506 };
507
508 /* set GPIO pin 'gpio' as an input */
at91_gpio_direction_input(struct udevice * dev,unsigned offset)509 static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
510 {
511 struct at91_port_priv *port = dev_get_priv(dev);
512
513 at91_set_port_input(port->regs, offset, 0);
514
515 return 0;
516 }
517
518 /* set GPIO pin 'gpio' as an output, with polarity 'value' */
at91_gpio_direction_output(struct udevice * dev,unsigned offset,int value)519 static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
520 int value)
521 {
522 struct at91_port_priv *port = dev_get_priv(dev);
523
524 at91_set_port_output(port->regs, offset, value);
525
526 return 0;
527 }
528
529 /* read GPIO IN value of pin 'gpio' */
at91_gpio_get_value(struct udevice * dev,unsigned offset)530 static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
531 {
532 struct at91_port_priv *port = dev_get_priv(dev);
533
534 return at91_get_port_value(port->regs, offset);
535 }
536
537 /* write GPIO OUT value to pin 'gpio' */
at91_gpio_set_value(struct udevice * dev,unsigned offset,int value)538 static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
539 int value)
540 {
541 struct at91_port_priv *port = dev_get_priv(dev);
542
543 at91_set_port_value(port->regs, offset, value);
544
545 return 0;
546 }
547
at91_gpio_get_function(struct udevice * dev,unsigned offset)548 static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
549 {
550 struct at91_port_priv *port = dev_get_priv(dev);
551
552 /* GPIOF_FUNC is not implemented yet */
553 if (at91_get_port_output(port->regs, offset))
554 return GPIOF_OUTPUT;
555 else
556 return GPIOF_INPUT;
557 }
558
at91_get_bank_name(uint32_t base_addr)559 static const char *at91_get_bank_name(uint32_t base_addr)
560 {
561 switch (base_addr) {
562 case ATMEL_BASE_PIOA:
563 return "PIOA";
564 case ATMEL_BASE_PIOB:
565 return "PIOB";
566 case ATMEL_BASE_PIOC:
567 return "PIOC";
568 #if (ATMEL_PIO_PORTS > 3)
569 case ATMEL_BASE_PIOD:
570 return "PIOD";
571 #if (ATMEL_PIO_PORTS > 4)
572 case ATMEL_BASE_PIOE:
573 return "PIOE";
574 #endif
575 #endif
576 }
577
578 return "undefined";
579 }
580
581 static const struct dm_gpio_ops gpio_at91_ops = {
582 .direction_input = at91_gpio_direction_input,
583 .direction_output = at91_gpio_direction_output,
584 .get_value = at91_gpio_get_value,
585 .set_value = at91_gpio_set_value,
586 .get_function = at91_gpio_get_function,
587 };
588
at91_gpio_probe(struct udevice * dev)589 static int at91_gpio_probe(struct udevice *dev)
590 {
591 struct at91_port_priv *port = dev_get_priv(dev);
592 struct at91_port_platdata *plat = dev_get_platdata(dev);
593 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
594 struct clk clk;
595 int ret;
596
597 ret = clk_get_by_index(dev, 0, &clk);
598 if (ret)
599 return ret;
600
601 ret = clk_enable(&clk);
602 if (ret)
603 return ret;
604
605 clk_free(&clk);
606
607 #if CONFIG_IS_ENABLED(OF_CONTROL)
608 plat->base_addr = (uint32_t)devfdt_get_addr_ptr(dev);
609 #endif
610 plat->bank_name = at91_get_bank_name(plat->base_addr);
611 port->regs = (struct at91_port *)plat->base_addr;
612
613 uc_priv->bank_name = plat->bank_name;
614 uc_priv->gpio_count = GPIO_PER_BANK;
615
616 return 0;
617 }
618
619 #if CONFIG_IS_ENABLED(OF_CONTROL)
620 static const struct udevice_id at91_gpio_ids[] = {
621 { .compatible = "atmel,at91rm9200-gpio" },
622 { }
623 };
624 #endif
625
626 U_BOOT_DRIVER(gpio_at91) = {
627 .name = "gpio_at91",
628 .id = UCLASS_GPIO,
629 #if CONFIG_IS_ENABLED(OF_CONTROL)
630 .of_match = at91_gpio_ids,
631 .platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
632 #endif
633 .ops = &gpio_at91_ops,
634 .probe = at91_gpio_probe,
635 .priv_auto_alloc_size = sizeof(struct at91_port_priv),
636 };
637 #endif
638