1 /*
2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/auth/auth_mod.h>
18 #include <drivers/console.h>
19 #include <lib/cpus/errata_report.h>
20 #include <lib/utils.h>
21 #include <plat/common/platform.h>
22 #include <smccc_helpers.h>
23 #include <tools_share/uuid.h>
24
25 #include "bl1_private.h"
26
27 /* BL1 Service UUID */
28 DEFINE_SVC_UUID2(bl1_svc_uid,
29 0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75,
30 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
31
32 static void bl1_load_bl2(void);
33
34 #if ENABLE_PAUTH
35 uint64_t bl1_apiakey[2];
36 #endif
37
38 /*******************************************************************************
39 * Helper utility to calculate the BL2 memory layout taking into consideration
40 * the BL1 RW data assuming that it is at the top of the memory layout.
41 ******************************************************************************/
bl1_calc_bl2_mem_layout(const meminfo_t * bl1_mem_layout,meminfo_t * bl2_mem_layout)42 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
43 meminfo_t *bl2_mem_layout)
44 {
45 assert(bl1_mem_layout != NULL);
46 assert(bl2_mem_layout != NULL);
47
48 /*
49 * Remove BL1 RW data from the scope of memory visible to BL2.
50 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
51 */
52 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
53 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
54 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
55
56 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
57 }
58
59 /*******************************************************************************
60 * Setup function for BL1.
61 ******************************************************************************/
bl1_setup(void)62 void bl1_setup(void)
63 {
64 /* Perform early platform-specific setup */
65 bl1_early_platform_setup();
66
67 /* Perform late platform-specific setup */
68 bl1_plat_arch_setup();
69
70 #if CTX_INCLUDE_PAUTH_REGS
71 /*
72 * Assert that the ARMv8.3-PAuth registers are present or an access
73 * fault will be triggered when they are being saved or restored.
74 */
75 assert(is_armv8_3_pauth_present());
76 #endif /* CTX_INCLUDE_PAUTH_REGS */
77 }
78
79 /*******************************************************************************
80 * Function to perform late architectural and platform specific initialization.
81 * It also queries the platform to load and run next BL image. Only called
82 * by the primary cpu after a cold boot.
83 ******************************************************************************/
bl1_main(void)84 void bl1_main(void)
85 {
86 unsigned int image_id;
87
88 /* Announce our arrival */
89 NOTICE(FIRMWARE_WELCOME_STR);
90 NOTICE("BL1: %s\n", version_string);
91 NOTICE("BL1: %s\n", build_message);
92
93 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
94 (void *)BL1_RAM_LIMIT);
95
96 print_errata_status();
97
98 #if ENABLE_ASSERTIONS
99 u_register_t val;
100 /*
101 * Ensure that MMU/Caches and coherency are turned on
102 */
103 #ifdef __aarch64__
104 val = read_sctlr_el3();
105 #else
106 val = read_sctlr();
107 #endif
108 assert(val & SCTLR_M_BIT);
109 assert(val & SCTLR_C_BIT);
110 assert(val & SCTLR_I_BIT);
111 /*
112 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
113 * provided platform value
114 */
115 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
116 /*
117 * If CWG is zero, then no CWG information is available but we can
118 * at least check the platform value is less than the architectural
119 * maximum.
120 */
121 if (val != 0)
122 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
123 else
124 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
125 #endif /* ENABLE_ASSERTIONS */
126
127 /* Perform remaining generic architectural setup from EL3 */
128 bl1_arch_setup();
129
130 #if TRUSTED_BOARD_BOOT
131 /* Initialize authentication module */
132 auth_mod_init();
133 #endif /* TRUSTED_BOARD_BOOT */
134
135 /* Perform platform setup in BL1. */
136 bl1_platform_setup();
137
138 #if ENABLE_PAUTH
139 /* Store APIAKey_EL1 key */
140 bl1_apiakey[0] = read_apiakeylo_el1();
141 bl1_apiakey[1] = read_apiakeyhi_el1();
142 #endif /* ENABLE_PAUTH */
143
144 /* Get the image id of next image to load and run. */
145 image_id = bl1_plat_get_next_image_id();
146
147 /*
148 * We currently interpret any image id other than
149 * BL2_IMAGE_ID as the start of firmware update.
150 */
151 if (image_id == BL2_IMAGE_ID)
152 bl1_load_bl2();
153 else
154 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
155
156 bl1_prepare_next_image(image_id);
157
158 console_flush();
159 }
160
161 /*******************************************************************************
162 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
163 * Called by the primary cpu after a cold boot.
164 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
165 * loader etc.
166 ******************************************************************************/
bl1_load_bl2(void)167 static void bl1_load_bl2(void)
168 {
169 image_desc_t *image_desc;
170 image_info_t *image_info;
171 int err;
172
173 /* Get the image descriptor */
174 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
175 assert(image_desc);
176
177 /* Get the image info */
178 image_info = &image_desc->image_info;
179 INFO("BL1: Loading BL2\n");
180
181 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
182 if (err) {
183 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
184 plat_error_handler(err);
185 }
186
187 err = load_auth_image(BL2_IMAGE_ID, image_info);
188 if (err) {
189 ERROR("Failed to load BL2 firmware.\n");
190 plat_error_handler(err);
191 }
192
193 /* Allow platform to handle image information. */
194 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
195 if (err) {
196 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
197 plat_error_handler(err);
198 }
199
200 NOTICE("BL1: Booting BL2\n");
201 }
202
203 /*******************************************************************************
204 * Function called just before handing over to the next BL to inform the user
205 * about the boot progress. In debug mode, also print details about the BL
206 * image's execution context.
207 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)208 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
209 {
210 #ifdef __aarch64__
211 NOTICE("BL1: Booting BL31\n");
212 #else
213 NOTICE("BL1: Booting BL32\n");
214 #endif /* __aarch64__ */
215 print_entry_point_info(bl_ep_info);
216 }
217
218 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)219 void print_debug_loop_message(void)
220 {
221 NOTICE("BL1: Debug loop, spinning forever\n");
222 NOTICE("BL1: Please connect the debugger to continue\n");
223 }
224 #endif
225
226 /*******************************************************************************
227 * Top level handler for servicing BL1 SMCs.
228 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,register_t x1,register_t x2,register_t x3,register_t x4,void * cookie,void * handle,unsigned int flags)229 register_t bl1_smc_handler(unsigned int smc_fid,
230 register_t x1,
231 register_t x2,
232 register_t x3,
233 register_t x4,
234 void *cookie,
235 void *handle,
236 unsigned int flags)
237 {
238
239 #if TRUSTED_BOARD_BOOT
240 /*
241 * Dispatch FWU calls to FWU SMC handler and return its return
242 * value
243 */
244 if (is_fwu_fid(smc_fid)) {
245 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
246 handle, flags);
247 }
248 #endif
249
250 switch (smc_fid) {
251 case BL1_SMC_CALL_COUNT:
252 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
253
254 case BL1_SMC_UID:
255 SMC_UUID_RET(handle, bl1_svc_uid);
256
257 case BL1_SMC_VERSION:
258 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
259
260 default:
261 break;
262 }
263
264 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
265 SMC_RET1(handle, SMC_UNK);
266 }
267
268 /*******************************************************************************
269 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
270 * compliance when invoking bl1_smc_handler.
271 ******************************************************************************/
bl1_smc_wrapper(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)272 register_t bl1_smc_wrapper(uint32_t smc_fid,
273 void *cookie,
274 void *handle,
275 unsigned int flags)
276 {
277 register_t x1, x2, x3, x4;
278
279 assert(handle);
280
281 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
282 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
283 }
284