1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <ns16550.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
14 #include <asm/arch/clock.h>
15 #endif
16 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
17 #include <asm/arch/funcmux.h>
18 #endif
19 #if IS_ENABLED(CONFIG_TEGRA_MC)
20 #include <asm/arch/mc.h>
21 #endif
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/ap.h>
24 #include <asm/arch-tegra/board.h>
25 #include <asm/arch-tegra/cboot.h>
26 #include <asm/arch-tegra/pmc.h>
27 #include <asm/arch-tegra/sys_proto.h>
28 #include <asm/arch-tegra/warmboot.h>
29
30 void save_boot_params_ret(void);
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 enum {
35 /* UARTs which we can enable */
36 UARTA = 1 << 0,
37 UARTB = 1 << 1,
38 UARTC = 1 << 2,
39 UARTD = 1 << 3,
40 UARTE = 1 << 4,
41 UART_COUNT = 5,
42 };
43
44 static bool from_spl __attribute__ ((section(".data")));
45
46 #ifndef CONFIG_SPL_BUILD
save_boot_params(unsigned long r0,unsigned long r1,unsigned long r2,unsigned long r3)47 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
48 unsigned long r3)
49 {
50 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
51
52 /*
53 * The logic for this is somewhat indirect. The purpose of the marker
54 * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
55 * was loaded from a read-only instance of itself, which is something
56 * that can happen in secure boot setups. So basically the presence
57 * of the marker is an indication that U-Boot was loaded by one such
58 * special variant of U-Boot. Conversely, the absence of the marker
59 * indicates that this instance of U-Boot was loaded by something
60 * other than a special U-Boot. This could be SPL, but it could just
61 * as well be one of any number of other first stage bootloaders.
62 */
63 if (from_spl)
64 cboot_save_boot_params(r0, r1, r2, r3);
65
66 save_boot_params_ret();
67 }
68 #endif
69
spl_was_boot_source(void)70 bool spl_was_boot_source(void)
71 {
72 return from_spl;
73 }
74
75 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
76 #if !defined(CONFIG_TEGRA124)
77 #error tegra_cpu_is_non_secure has only been validated on Tegra124
78 #endif
tegra_cpu_is_non_secure(void)79 bool tegra_cpu_is_non_secure(void)
80 {
81 /*
82 * This register reads 0xffffffff in non-secure mode. This register
83 * only implements bits 31:20, so the lower bits will always read 0 in
84 * secure mode. Thus, the lower bits are an indicator for secure vs.
85 * non-secure mode.
86 */
87 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
88 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
89 return (mc_s_cfg0 & 1) == 1;
90 }
91 #endif
92
93 #if IS_ENABLED(CONFIG_TEGRA_MC)
94 /* Read the RAM size directly from the memory controller */
query_sdram_size(void)95 static phys_size_t query_sdram_size(void)
96 {
97 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
98 u32 emem_cfg;
99 phys_size_t size_bytes;
100
101 emem_cfg = readl(&mc->mc_emem_cfg);
102 #if defined(CONFIG_TEGRA20)
103 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
104 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
105 #else
106 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
107 #ifndef CONFIG_PHYS_64BIT
108 /*
109 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
110 * and will wrap. Clip the reported size to the maximum that a 32-bit
111 * variable can represent (rounded to a page).
112 */
113 if (emem_cfg >= 4096) {
114 size_bytes = U32_MAX & ~(0x1000 - 1);
115 } else
116 #endif
117 {
118 /* RAM size EMC is programmed to. */
119 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
120 #ifndef CONFIG_ARM64
121 /*
122 * If all RAM fits within 32-bits, it can be accessed without
123 * LPAE, so go test the RAM size. Otherwise, we can't access
124 * all the RAM, and get_ram_size() would get confused, so
125 * avoid using it. There's no reason we should need this
126 * validation step anyway.
127 */
128 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
129 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
130 size_bytes);
131 #endif
132 }
133 #endif
134
135 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
136 /* External memory limited to 2047 MB due to IROM/HI-VEC */
137 if (size_bytes == SZ_2G)
138 size_bytes -= SZ_1M;
139 #endif
140
141 return size_bytes;
142 }
143 #endif
144
dram_init(void)145 int dram_init(void)
146 {
147 int err;
148
149 /* try to initialize DRAM from cboot DTB first */
150 err = cboot_dram_init();
151 if (err == 0)
152 return 0;
153
154 #if IS_ENABLED(CONFIG_TEGRA_MC)
155 /* We do not initialise DRAM here. We just query the size */
156 gd->ram_size = query_sdram_size();
157 #endif
158
159 return 0;
160 }
161
162 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
163 static int uart_configs[] = {
164 #if defined(CONFIG_TEGRA20)
165 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
166 FUNCMUX_UART1_UAA_UAB,
167 #elif defined(CONFIG_TEGRA_UARTA_GPU)
168 FUNCMUX_UART1_GPU,
169 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
170 FUNCMUX_UART1_SDIO1,
171 #else
172 FUNCMUX_UART1_IRRX_IRTX,
173 #endif
174 FUNCMUX_UART2_UAD,
175 -1,
176 FUNCMUX_UART4_GMC,
177 -1,
178 #elif defined(CONFIG_TEGRA30)
179 FUNCMUX_UART1_ULPI, /* UARTA */
180 -1,
181 -1,
182 -1,
183 -1,
184 #elif defined(CONFIG_TEGRA114)
185 -1,
186 -1,
187 -1,
188 FUNCMUX_UART4_GMI, /* UARTD */
189 -1,
190 #elif defined(CONFIG_TEGRA124)
191 FUNCMUX_UART1_KBC, /* UARTA */
192 -1,
193 -1,
194 FUNCMUX_UART4_GPIO, /* UARTD */
195 -1,
196 #else /* Tegra210 */
197 FUNCMUX_UART1_UART1, /* UARTA */
198 -1,
199 -1,
200 FUNCMUX_UART4_UART4, /* UARTD */
201 -1,
202 #endif
203 };
204
205 /**
206 * Set up the specified uarts
207 *
208 * @param uarts_ids Mask containing UARTs to init (UARTx)
209 */
setup_uarts(int uart_ids)210 static void setup_uarts(int uart_ids)
211 {
212 static enum periph_id id_for_uart[] = {
213 PERIPH_ID_UART1,
214 PERIPH_ID_UART2,
215 PERIPH_ID_UART3,
216 PERIPH_ID_UART4,
217 PERIPH_ID_UART5,
218 };
219 size_t i;
220
221 for (i = 0; i < UART_COUNT; i++) {
222 if (uart_ids & (1 << i)) {
223 enum periph_id id = id_for_uart[i];
224
225 funcmux_select(id, uart_configs[i]);
226 clock_ll_start_uart(id);
227 }
228 }
229 }
230 #endif
231
board_init_uart_f(void)232 void board_init_uart_f(void)
233 {
234 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
235 int uart_ids = 0; /* bit mask of which UART ids to enable */
236
237 #ifdef CONFIG_TEGRA_ENABLE_UARTA
238 uart_ids |= UARTA;
239 #endif
240 #ifdef CONFIG_TEGRA_ENABLE_UARTB
241 uart_ids |= UARTB;
242 #endif
243 #ifdef CONFIG_TEGRA_ENABLE_UARTC
244 uart_ids |= UARTC;
245 #endif
246 #ifdef CONFIG_TEGRA_ENABLE_UARTD
247 uart_ids |= UARTD;
248 #endif
249 #ifdef CONFIG_TEGRA_ENABLE_UARTE
250 uart_ids |= UARTE;
251 #endif
252 setup_uarts(uart_ids);
253 #endif
254 }
255
256 #if !CONFIG_IS_ENABLED(OF_CONTROL)
257 static struct ns16550_platdata ns16550_com1_pdata = {
258 .base = CONFIG_SYS_NS16550_COM1,
259 .reg_shift = 2,
260 .clock = CONFIG_SYS_NS16550_CLK,
261 .fcr = UART_FCR_DEFVAL,
262 };
263
264 U_BOOT_DEVICE(ns16550_com1) = {
265 "ns16550_serial", &ns16550_com1_pdata
266 };
267 #endif
268
269 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
enable_caches(void)270 void enable_caches(void)
271 {
272 /* Enable D-cache. I-cache is already enabled in start.S */
273 dcache_enable();
274 }
275 #endif
276