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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5  * Copyright 2019 NXP
6  *
7  * Gated clock implementation
8  */
9 
10 #include <common.h>
11 #include <asm/io.h>
12 #include <malloc.h>
13 #include <clk-uclass.h>
14 #include <dm/device.h>
15 #include <linux/clk-provider.h>
16 #include <clk.h>
17 #include "clk.h"
18 
19 #define UBOOT_DM_CLK_GATE "clk_gate"
20 
21 /**
22  * DOC: basic gatable clock which can gate and ungate it's output
23  *
24  * Traits of this clock:
25  * prepare - clk_(un)prepare only ensures parent is (un)prepared
26  * enable - clk_enable and clk_disable are functional & control gating
27  * rate - inherits rate from parent.  No clk_set_rate support
28  * parent - fixed parent.  No clk_set_parent support
29  */
30 
31 /*
32  * It works on following logic:
33  *
34  * For enabling clock, enable = 1
35  *	set2dis = 1	-> clear bit	-> set = 0
36  *	set2dis = 0	-> set bit	-> set = 1
37  *
38  * For disabling clock, enable = 0
39  *	set2dis = 1	-> set bit	-> set = 1
40  *	set2dis = 0	-> clear bit	-> set = 0
41  *
42  * So, result is always: enable xor set2dis.
43  */
clk_gate_endisable(struct clk * clk,int enable)44 static void clk_gate_endisable(struct clk *clk, int enable)
45 {
46 	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
47 			dev_get_clk_ptr(clk->dev) : clk);
48 	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
49 	u32 reg;
50 
51 	set ^= enable;
52 
53 	if (gate->flags & CLK_GATE_HIWORD_MASK) {
54 		reg = BIT(gate->bit_idx + 16);
55 		if (set)
56 			reg |= BIT(gate->bit_idx);
57 	} else {
58 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
59 		reg = gate->io_gate_val;
60 #else
61 		reg = readl(gate->reg);
62 #endif
63 
64 		if (set)
65 			reg |= BIT(gate->bit_idx);
66 		else
67 			reg &= ~BIT(gate->bit_idx);
68 	}
69 
70 	writel(reg, gate->reg);
71 }
72 
clk_gate_enable(struct clk * clk)73 static int clk_gate_enable(struct clk *clk)
74 {
75 	clk_gate_endisable(clk, 1);
76 
77 	return 0;
78 }
79 
clk_gate_disable(struct clk * clk)80 static int clk_gate_disable(struct clk *clk)
81 {
82 	clk_gate_endisable(clk, 0);
83 
84 	return 0;
85 }
86 
clk_gate_is_enabled(struct clk * clk)87 int clk_gate_is_enabled(struct clk *clk)
88 {
89 	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
90 			dev_get_clk_ptr(clk->dev) : clk);
91 	u32 reg;
92 
93 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
94 	reg = gate->io_gate_val;
95 #else
96 	reg = readl(gate->reg);
97 #endif
98 
99 	/* if a set bit disables this clk, flip it before masking */
100 	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
101 		reg ^= BIT(gate->bit_idx);
102 
103 	reg &= BIT(gate->bit_idx);
104 
105 	return reg ? 1 : 0;
106 }
107 
108 const struct clk_ops clk_gate_ops = {
109 	.enable = clk_gate_enable,
110 	.disable = clk_gate_disable,
111 	.get_rate = clk_generic_get_rate,
112 };
113 
clk_register_gate(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,u8 clk_gate_flags,spinlock_t * lock)114 struct clk *clk_register_gate(struct device *dev, const char *name,
115 			      const char *parent_name, unsigned long flags,
116 			      void __iomem *reg, u8 bit_idx,
117 			      u8 clk_gate_flags, spinlock_t *lock)
118 {
119 	struct clk_gate *gate;
120 	struct clk *clk;
121 	int ret;
122 
123 	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
124 		if (bit_idx > 15) {
125 			pr_err("gate bit exceeds LOWORD field\n");
126 			return ERR_PTR(-EINVAL);
127 		}
128 	}
129 
130 	/* allocate the gate */
131 	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
132 	if (!gate)
133 		return ERR_PTR(-ENOMEM);
134 
135 	/* struct clk_gate assignments */
136 	gate->reg = reg;
137 	gate->bit_idx = bit_idx;
138 	gate->flags = clk_gate_flags;
139 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
140 	gate->io_gate_val = *(u32 *)reg;
141 #endif
142 
143 	clk = &gate->clk;
144 
145 	ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
146 	if (ret) {
147 		kfree(gate);
148 		return ERR_PTR(ret);
149 	}
150 
151 	return clk;
152 }
153 
154 U_BOOT_DRIVER(clk_gate) = {
155 	.name	= UBOOT_DM_CLK_GATE,
156 	.id	= UCLASS_CLK,
157 	.ops	= &clk_gate_ops,
158 	.flags = DM_FLAG_PRE_RELOC,
159 };
160