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1 #include <stdio.h>
2 #include <stdint.h>
3 #include <stdlib.h>
4 #include <string.h>
5 #include <alloca.h>
6 
7 #include <errno.h>
8 #include <sys/types.h>
9 #include <sys/sysctl.h>
10 #include <mach/machine.h>
11 
12 #include <cpuinfo.h>
13 #include <mach/api.h>
14 #include <cpuinfo/internal-api.h>
15 #include <cpuinfo/log.h>
16 
17 
18 struct cpuinfo_arm_isa cpuinfo_isa = {
19 #if CPUINFO_ARCH_ARM
20 	.thumb = true,
21 	.thumb2 = true,
22 	.thumbee = false,
23 	.jazelle = false,
24 	.armv5e = true,
25 	.armv6 = true,
26 	.armv6k = true,
27 	.armv7 = true,
28 	.vfpv2 = false,
29 	.vfpv3 = true,
30 	.d32 = true,
31 	.wmmx = false,
32 	.wmmx2 = false,
33 	.neon = true,
34 #endif
35 #if CPUINFO_ARCH_ARM64
36 	.aes = true,
37 	.sha1 = true,
38 	.sha2 = true,
39 	.pmull = true,
40 	.crc32 = true,
41 #endif
42 };
43 
get_sys_info(int type_specifier,const char * name)44 static uint32_t get_sys_info(int type_specifier, const char* name) {
45 	size_t size = 0;
46 	uint32_t result = 0;
47 	int mib[2] = { CTL_HW, type_specifier };
48 	if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) {
49 		cpuinfo_log_info("sysctl(\"%s\") failed: %s", name, strerror(errno));
50 	} else if (size == sizeof(uint32_t)) {
51 		sysctl(mib, 2, &result, &size, NULL, 0);
52 		cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", name, result, size);
53 	} else {
54 		cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", name);
55 	}
56 	return result;
57 }
58 
get_sys_info_by_name(const char * type_specifier)59 static uint32_t get_sys_info_by_name(const char* type_specifier) {
60 	size_t size = 0;
61 	uint32_t result = 0;
62 	if (sysctlbyname(type_specifier, NULL, &size, NULL, 0) != 0) {
63 		cpuinfo_log_info("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno));
64 	} else if (size == sizeof(uint32_t)) {
65 		sysctlbyname(type_specifier, &result, &size, NULL, 0);
66 		cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", type_specifier, result, size);
67 	} else {
68 		cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", type_specifier);
69 	}
70 	return result;
71 }
72 
decode_uarch(uint32_t cpu_family,uint32_t cpu_subtype,uint32_t core_index,uint32_t core_count)73 static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t cpu_subtype, uint32_t core_index, uint32_t core_count) {
74 	switch (cpu_family) {
75 		case CPUFAMILY_ARM_SWIFT:
76 			return cpuinfo_uarch_swift;
77 		case CPUFAMILY_ARM_CYCLONE:
78 			return cpuinfo_uarch_cyclone;
79 		case CPUFAMILY_ARM_TYPHOON:
80 			return cpuinfo_uarch_typhoon;
81 		case CPUFAMILY_ARM_TWISTER:
82 			return cpuinfo_uarch_twister;
83 		case CPUFAMILY_ARM_HURRICANE:
84 			return cpuinfo_uarch_hurricane;
85 #ifdef CPUFAMILY_ARM_MONSOON_MISTRAL
86 		case CPUFAMILY_ARM_MONSOON_MISTRAL:
87 #else
88 		case 0xe81e7ef6:
89 			/* Hard-coded value for older SDKs which do not define CPUFAMILY_ARM_MONSOON_MISTRAL */
90 #endif
91 			/* 2x Monsoon + 4x Mistral cores */
92 			return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral;
93 #ifdef CPUFAMILY_ARM_VORTEX_TEMPEST
94 		case CPUFAMILY_ARM_VORTEX_TEMPEST:
95 #else
96 		case 0x07d34b9f:
97 			/* Hard-coded value for older SDKs which do not define CPUFAMILY_ARM_VORTEX_TEMPEST */
98 #endif
99 			/* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x Cortex + 4x Tempest */
100 			return core_index + 4 < core_count ? cpuinfo_uarch_vortex : cpuinfo_uarch_tempest;
101 		default:
102 			/* Use hw.cpusubtype for detection */
103 			break;
104 	}
105 
106 	switch (cpu_subtype) {
107 		case CPU_SUBTYPE_ARM_V7:
108 			return cpuinfo_uarch_cortex_a8;
109 		case CPU_SUBTYPE_ARM_V7F:
110 			return cpuinfo_uarch_cortex_a9;
111 		case CPU_SUBTYPE_ARM_V7K:
112 			return cpuinfo_uarch_cortex_a7;
113 		default:
114 			return cpuinfo_uarch_unknown;
115 	}
116 }
117 
decode_package_name(char * package_name)118 static void decode_package_name(char* package_name) {
119 	size_t size;
120 	if (sysctlbyname("hw.machine", NULL, &size, NULL, 0) != 0) {
121 		cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
122 		return;
123 	}
124 
125 	char *machine_name = alloca(size);
126 	if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) {
127 		cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno));
128 		return;
129 	}
130 	cpuinfo_log_debug("hw.machine: %s", machine_name);
131 
132 	char name[10];
133 	uint32_t major = 0, minor = 0;
134 	if (sscanf(machine_name, "%9[^,0123456789]%"SCNu32",%"SCNu32, name, &major, &minor) != 3) {
135 		cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno));
136 		return;
137 	}
138 
139 	uint32_t chip_model = 0;
140 	char suffix = '\0';
141 	if (strcmp(name, "iPhone") == 0) {
142 		/*
143 		 * iPhone 4 and up are supported:
144 		 *  - iPhone 4       [A4]:  iPhone3,1, iPhone3,2, iPhone3,3
145 		 *  - iPhone 4S      [A5]:  iPhone4,1
146 		 *  - iPhone 5       [A6]:  iPhone5,1, iPhone5,2
147 		 *  - iPhone 5c      [A6]:  iPhone5,3, iPhone5,4
148 		 *  - iPhone 5s      [A7]:  iPhone6,1, iPhone6,2
149 		 *  - iPhone 6       [A8]:  iPhone7,2
150 		 *  - iPhone 6 Plus  [A8]:  iPhone7,1
151 		 *  - iPhone 6s      [A9]:  iPhone8,1
152 		 *  - iPhone 6s Plus [A9]:  iPhone8,2
153 		 *  - iPhone SE      [A9]:  iPhone8,4
154 		 *  - iPhone 7       [A10]: iPhone9,1, iPhone9,3
155 		 *  - iPhone 7 Plus  [A10]: iPhone9,2, iPhone9,4
156 		 *  - iPhone 8       [A11]: iPhone10,1, iPhone10,4
157 		 *  - iPhone 8 Plus  [A11]: iPhone10,2, iPhone10,5
158 		 *  - iPhone X       [A11]: iPhone10,3, iPhone10,6
159 		 *  - iPhone XS      [A12]: iPhone11,2,
160 		 *  - iPhone XS Max  [A12]: iPhone11,4, iPhone11,6
161 		 *  - iPhone XR      [A12]: iPhone11,8
162 		 */
163 		chip_model = major + 1;
164 	} else if (strcmp(name, "iPad") == 0) {
165 		switch (major) {
166 			/* iPad 2 and up are supported */
167 			case 2:
168 				/*
169 				 * iPad 2    [A5]: iPad2,1, iPad2,2, iPad2,3, iPad2,4
170 				 * iPad mini [A5]: iPad2,5, iPad2,6, iPad2,7
171 				 */
172 				chip_model = major + 3;
173 				break;
174 			case 3:
175 				/*
176 				 * iPad 3rd Gen [A5X]: iPad3,1, iPad3,2, iPad3,3
177 				 * iPad 4th Gen [A6X]: iPad3,4, iPad3,5, iPad3,6
178 				 */
179 				chip_model = (minor <= 3) ? 5 : 6;
180 				suffix = 'X';
181 				break;
182 			case 4:
183 				/*
184 				 * iPad Air         [A7]: iPad4,1, iPad4,2, iPad4,3
185 				 * iPad mini Retina [A7]: iPad4,4, iPad4,5, iPad4,6
186 				 * iPad mini 3      [A7]: iPad4,7, iPad4,8, iPad4,9
187 				 */
188 				chip_model = major + 3;
189 				break;
190 			case 5:
191 				/*
192 				 * iPad mini 4 [A8]:  iPad5,1, iPad5,2
193 				 * iPad Air 2  [A8X]: iPad5,3, iPad5,4
194 				 */
195 				chip_model = major + 3;
196 				suffix = (minor <= 2) ? '\0' : 'X';
197 				break;
198 			case 6:
199 				/*
200 				 * iPad Pro 9.7" [A9X]: iPad6,3, iPad6,4
201 				 * iPad Pro      [A9X]: iPad6,7, iPad6,8
202 				 * iPad 5th Gen  [A9]:  iPad6,11, iPad6,12
203 				 */
204 				chip_model = major + 3;
205 				suffix = minor <= 8 ? 'X' : '\0';
206 				break;
207 			case 7:
208 				/*
209 				 * iPad Pro 12.9" [A10X]: iPad7,1, iPad7,2
210 				 * iPad Pro 10.5" [A10X]: iPad7,3, iPad7,4
211 				 * iPad 6th Gen   [A10]:  iPad7,5, iPad7,6
212 				 */
213 				chip_model = major + 3;
214 				suffix = minor <= 4 ? 'X' : '\0';
215 				break;
216 			default:
217 				cpuinfo_log_info("unknown iPad: %s", machine_name);
218 				break;
219 		}
220 	} else if (strcmp(name, "iPod") == 0) {
221 		switch (major) {
222 			case 5:
223 				chip_model = 5;
224 				break;
225 				/* iPod touch (5th Gen) [A5]: iPod5,1 */
226 			case 7:
227 				/* iPod touch (6th Gen, 2015) [A8]: iPod7,1 */
228 				chip_model = 8;
229 				break;
230 			default:
231 				cpuinfo_log_info("unknown iPod: %s", machine_name);
232 				break;
233 		}
234 	} else {
235 		cpuinfo_log_info("unknown device: %s", machine_name);
236 	}
237 	if (chip_model != 0) {
238 		snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%"PRIu32"%c", chip_model, suffix);
239 	}
240 }
241 
cpuinfo_arm_mach_init(void)242 void cpuinfo_arm_mach_init(void) {
243 	struct cpuinfo_processor* processors = NULL;
244 	struct cpuinfo_core* cores = NULL;
245 	struct cpuinfo_cluster* clusters = NULL;
246 	struct cpuinfo_package* packages = NULL;
247 	struct cpuinfo_cache* l1i = NULL;
248 	struct cpuinfo_cache* l1d = NULL;
249 	struct cpuinfo_cache* l2 = NULL;
250 	struct cpuinfo_cache* l3 = NULL;
251 
252 	struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology();
253 	processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor));
254 	if (processors == NULL) {
255 		cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors",
256 			mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads);
257 		goto cleanup;
258 	}
259 	cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core));
260 	if (cores == NULL) {
261 		cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores",
262 			mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores);
263 		goto cleanup;
264 	}
265 	packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package));
266 	if (packages == NULL) {
267 		cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" packages",
268 			mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages);
269 		goto cleanup;
270 	}
271 
272 	const uint32_t threads_per_core = mach_topology.threads / mach_topology.cores;
273 	const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages;
274 	const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages;
275 
276 	for (uint32_t i = 0; i < mach_topology.packages; i++) {
277 		packages[i] = (struct cpuinfo_package) {
278 			.processor_start = i * threads_per_package,
279 			.processor_count = threads_per_package,
280 			.core_start = i * cores_per_package,
281 			.core_count = cores_per_package,
282 		};
283 		decode_package_name(packages[i].name);
284 	}
285 
286 
287 	const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily");
288 	const uint32_t cpu_type = get_sys_info_by_name("hw.cputype");
289 	const uint32_t cpu_subtype = get_sys_info_by_name("hw.cpusubtype");
290 	switch (cpu_type) {
291 		case CPU_TYPE_ARM64:
292 			cpuinfo_isa.aes = true;
293 			cpuinfo_isa.sha1 = true;
294 			cpuinfo_isa.sha2 = true;
295 			cpuinfo_isa.pmull = true;
296 			cpuinfo_isa.crc32 = true;
297 			break;
298 #if CPUINFO_ARCH_ARM
299 		case CPU_TYPE_ARM:
300 			switch (cpu_subtype) {
301 				case CPU_SUBTYPE_ARM_V8:
302 					cpuinfo_isa.aes = true;
303 					cpuinfo_isa.sha1 = true;
304 					cpuinfo_isa.sha2 = true;
305 					cpuinfo_isa.pmull = true;
306 					cpuinfo_isa.crc32 = true;
307 					/* Fall-through to add ARMv7S features */
308 				case CPU_SUBTYPE_ARM_V7S:
309 				case CPU_SUBTYPE_ARM_V7K:
310 					cpuinfo_isa.fma = true;
311 					/* Fall-through to add ARMv7F features */
312 				case CPU_SUBTYPE_ARM_V7F:
313 					cpuinfo_isa.armv7mp = true;
314 					cpuinfo_isa.fp16 = true;
315 					/* Fall-through to add ARMv7 features */
316 				case CPU_SUBTYPE_ARM_V7:
317 					break;
318 				default:
319 					break;
320 			}
321 			break;
322 #endif
323 	}
324 	/*
325 	 * Support for ARMv8.1 Atomics & FP16 arithmetic instructions is supposed to be detected via
326 	 * sysctlbyname calls with "hw.optional.armv8_1_atomics" and "hw.optional.neon_fp16" arguments
327 	 * (see https://devstreaming-cdn.apple.com/videos/wwdc/2018/409t8zw7rumablsh/409/409_whats_new_in_llvm.pdf),
328 	 * but on new iOS versions these calls just fail with EPERM.
329 	 *
330 	 * Thus, we whitelist CPUs known to support these instructions.
331 	 */
332 	switch (cpu_family) {
333 #ifdef CPUFAMILY_ARM_MONSOON_MISTRAL
334 		case CPUFAMILY_ARM_MONSOON_MISTRAL:
335 #else
336 		case 0xe81e7ef6:
337 			/* Hard-coded value for older SDKs which do not define CPUFAMILY_ARM_MONSOON_MISTRAL */
338 #endif
339 #ifdef CPUFAMILY_ARM_VORTEX_TEMPEST
340 		case CPUFAMILY_ARM_VORTEX_TEMPEST:
341 #else
342 		case 0x07d34b9f:
343 			/* Hard-coded value for older SDKs which do not define CPUFAMILY_ARM_VORTEX_TEMPEST */
344 #endif
345 #if CPUINFO_ARCH_ARM64
346 			cpuinfo_isa.atomics = true;
347 #endif
348 			cpuinfo_isa.fp16arith = true;
349 	}
350 
351 	uint32_t num_clusters = 1;
352 	for (uint32_t i = 0; i < mach_topology.cores; i++) {
353 		cores[i] = (struct cpuinfo_core) {
354 			.processor_start = i * threads_per_core,
355 			.processor_count = threads_per_core,
356 			.core_id = i % cores_per_package,
357 			.package = packages + i / cores_per_package,
358 			.vendor = cpuinfo_vendor_apple,
359 			.uarch = decode_uarch(cpu_family, cpu_subtype, i, mach_topology.cores),
360 		};
361 		if (i != 0 && cores[i].uarch != cores[i - 1].uarch) {
362 			num_clusters++;
363 		}
364 	}
365 	for (uint32_t i = 0; i < mach_topology.threads; i++) {
366 		const uint32_t smt_id = i % threads_per_core;
367 		const uint32_t core_id = i / threads_per_core;
368 		const uint32_t package_id = i / threads_per_package;
369 
370 		processors[i].smt_id = smt_id;
371 		processors[i].core = &cores[core_id];
372 		processors[i].package = &packages[package_id];
373 	}
374 
375 	clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster));
376 	if (clusters == NULL) {
377 		cpuinfo_log_error(
378 			"failed to allocate %zu bytes for descriptions of %"PRIu32" clusters",
379 			num_clusters * sizeof(struct cpuinfo_cluster), num_clusters);
380 		goto cleanup;
381 	}
382 	uint32_t cluster_idx = UINT32_MAX;
383 	for (uint32_t i = 0; i < mach_topology.cores; i++) {
384 		if (i == 0 || cores[i].uarch != cores[i - 1].uarch) {
385 			cluster_idx++;
386 			clusters[cluster_idx] = (struct cpuinfo_cluster) {
387 				.processor_start = i * threads_per_core,
388 				.processor_count = 1,
389 				.core_start = i,
390 				.core_count = 1,
391 				.cluster_id = cluster_idx,
392 				.package = cores[i].package,
393 				.vendor = cores[i].vendor,
394 				.uarch = cores[i].uarch,
395 			};
396 		} else {
397 			clusters[cluster_idx].processor_count++;
398 			clusters[cluster_idx].core_count++;
399 		}
400 		cores[i].cluster = &clusters[cluster_idx];
401 	}
402 
403 	for (uint32_t i = 0; i < mach_topology.threads; i++) {
404 		const uint32_t core_id = i / threads_per_core;
405 		processors[i].cluster = cores[core_id].cluster;
406 	}
407 
408 	for (uint32_t i = 0; i < mach_topology.packages; i++) {
409 		packages[i].cluster_start = 0;
410 		packages[i].cluster_count = num_clusters;
411 	}
412 
413 	const uint32_t cacheline_size = get_sys_info(HW_CACHELINE, "HW_CACHELINE");
414 	const uint32_t l1d_cache_size = get_sys_info(HW_L1DCACHESIZE, "HW_L1DCACHESIZE");
415 	const uint32_t l1i_cache_size = get_sys_info(HW_L1ICACHESIZE, "HW_L1ICACHESIZE");
416 	const uint32_t l2_cache_size = get_sys_info(HW_L2CACHESIZE, "HW_L2CACHESIZE");
417 	const uint32_t l3_cache_size = get_sys_info(HW_L3CACHESIZE, "HW_L3CACHESIZE");
418 	const uint32_t l1_cache_associativity = 4;
419 	const uint32_t l2_cache_associativity = 8;
420 	const uint32_t l3_cache_associativity = 16;
421 	const uint32_t cache_partitions = 1;
422 	const uint32_t cache_flags = 0;
423 
424 	uint32_t threads_per_l1 = 0, l1_count = 0;
425 	if (l1i_cache_size != 0 || l1d_cache_size != 0) {
426 		/* Assume L1 caches are private to each core */
427 		threads_per_l1 = 1;
428 		l1_count = mach_topology.threads / threads_per_l1;
429 		cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count);
430 	}
431 
432 	uint32_t threads_per_l2 = 0, l2_count = 0;
433 	if (l2_cache_size != 0) {
434 		/* Assume L2 cache is shared between all cores */
435 		threads_per_l2 = mach_topology.cores;
436 		l2_count = 1;
437 		cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count);
438 	}
439 
440 	uint32_t threads_per_l3 = 0, l3_count = 0;
441 	if (l3_cache_size != 0) {
442 		/* Assume L3 cache is shared between all cores */
443 		threads_per_l3 = mach_topology.cores;
444 		l3_count = 1;
445 		cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count);
446 	}
447 
448 	if (l1i_cache_size != 0) {
449 		l1i = calloc(l1_count, sizeof(struct cpuinfo_cache));
450 		if (l1i == NULL) {
451 			cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches",
452 				l1_count * sizeof(struct cpuinfo_cache), l1_count);
453 			goto cleanup;
454 		}
455 		for (uint32_t c = 0; c < l1_count; c++) {
456 			l1i[c] = (struct cpuinfo_cache) {
457 				.size            = l1i_cache_size,
458 				.associativity   = l1_cache_associativity,
459 				.sets            = l1i_cache_size / (l1_cache_associativity * cacheline_size),
460 				.partitions      = cache_partitions,
461 				.line_size       = cacheline_size,
462 				.flags           = cache_flags,
463 				.processor_start = c * threads_per_l1,
464 				.processor_count = threads_per_l1,
465 			};
466 		}
467 		for (uint32_t t = 0; t < mach_topology.threads; t++) {
468 			processors[t].cache.l1i = &l1i[t / threads_per_l1];
469 		}
470 	}
471 
472 	if (l1d_cache_size != 0) {
473 		l1d = calloc(l1_count, sizeof(struct cpuinfo_cache));
474 		if (l1d == NULL) {
475 			cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches",
476 				l1_count * sizeof(struct cpuinfo_cache), l1_count);
477 			goto cleanup;
478 		}
479 		for (uint32_t c = 0; c < l1_count; c++) {
480 			l1d[c] = (struct cpuinfo_cache) {
481 				.size            = l1d_cache_size,
482 				.associativity   = l1_cache_associativity,
483 				.sets            = l1d_cache_size / (l1_cache_associativity * cacheline_size),
484 				.partitions      = cache_partitions,
485 				.line_size       = cacheline_size,
486 				.flags           = cache_flags,
487 				.processor_start = c * threads_per_l1,
488 				.processor_count = threads_per_l1,
489 			};
490 		}
491 		for (uint32_t t = 0; t < mach_topology.threads; t++) {
492 			processors[t].cache.l1d = &l1d[t / threads_per_l1];
493 		}
494 	}
495 
496 	if (l2_count != 0) {
497 		l2 = calloc(l2_count, sizeof(struct cpuinfo_cache));
498 		if (l2 == NULL) {
499 			cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches",
500 				l2_count * sizeof(struct cpuinfo_cache), l2_count);
501 			goto cleanup;
502 		}
503 		for (uint32_t c = 0; c < l2_count; c++) {
504 			l2[c] = (struct cpuinfo_cache) {
505 				.size            = l2_cache_size,
506 				.associativity   = l2_cache_associativity,
507 				.sets            = l2_cache_size / (l2_cache_associativity * cacheline_size),
508 				.partitions      = cache_partitions,
509 				.line_size       = cacheline_size,
510 				.flags           = cache_flags,
511 				.processor_start = c * threads_per_l2,
512 				.processor_count = threads_per_l2,
513 			};
514 		}
515 		for (uint32_t t = 0; t < mach_topology.threads; t++) {
516 			processors[t].cache.l2 = &l2[0];
517 		}
518 	}
519 
520 	if (l3_count != 0) {
521 		l3 = calloc(l3_count, sizeof(struct cpuinfo_cache));
522 		if (l3 == NULL) {
523 			cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches",
524 												l3_count * sizeof(struct cpuinfo_cache), l3_count);
525 			goto cleanup;
526 		}
527 		for (uint32_t c = 0; c < l3_count; c++) {
528 			l3[c] = (struct cpuinfo_cache) {
529 				.size            = l3_cache_size,
530 				.associativity   = l3_cache_associativity,
531 				.sets            = l3_cache_size / (l3_cache_associativity * cacheline_size),
532 				.partitions      = cache_partitions,
533 				.line_size       = cacheline_size,
534 				.flags           = cache_flags,
535 				.processor_start = c * threads_per_l3,
536 				.processor_count = threads_per_l3,
537 			};
538 		}
539 		for (uint32_t t = 0; t < mach_topology.threads; t++) {
540 			processors[t].cache.l3 = &l3[0];
541 		}
542 	}
543 
544 	/* Commit changes */
545 	cpuinfo_cache[cpuinfo_cache_level_1i] = l1i;
546 	cpuinfo_cache[cpuinfo_cache_level_1d] = l1d;
547 	cpuinfo_cache[cpuinfo_cache_level_2]  = l2;
548 	cpuinfo_cache[cpuinfo_cache_level_3]  = l3;
549 
550 	cpuinfo_processors = processors;
551 	cpuinfo_cores = cores;
552 	cpuinfo_clusters = clusters;
553 	cpuinfo_packages = packages;
554 
555 	cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count;
556 	cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count;
557 	cpuinfo_cache_count[cpuinfo_cache_level_2]  = l2_count;
558 	cpuinfo_cache_count[cpuinfo_cache_level_3]  = l3_count;
559 
560 	cpuinfo_processors_count = mach_topology.threads;
561 	cpuinfo_cores_count = mach_topology.cores;
562 	cpuinfo_clusters_count = num_clusters;
563 	cpuinfo_packages_count = mach_topology.packages;
564 
565 	cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]);
566 
567 	__sync_synchronize();
568 
569 	cpuinfo_is_initialized = true;
570 
571 	processors = NULL;
572 	cores = NULL;
573 	clusters = NULL;
574 	packages = NULL;
575 	l1i = l1d = l2 = l3 = NULL;
576 
577 cleanup:
578 	free(processors);
579 	free(cores);
580 	free(clusters);
581 	free(packages);
582 	free(l1i);
583 	free(l1d);
584 	free(l2);
585 	free(l3);
586 }
587