1 /*
2 * \file trc_pkt_elem_etmv4i.cpp
3 * \brief OpenCSD :
4 *
5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34 #include <sstream>
35 #include <iomanip>
36
37 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h"
38
EtmV4ITrcPacket()39 EtmV4ITrcPacket::EtmV4ITrcPacket()
40 {
41 }
42
~EtmV4ITrcPacket()43 EtmV4ITrcPacket::~EtmV4ITrcPacket()
44 {
45 }
46
initStartState()47 void EtmV4ITrcPacket::initStartState()
48 {
49 // clear packet state to start of trace (first sync or post discontinuity)
50
51 // clear all valid bits
52 pkt_valid.val = 0;
53
54 // virtual address
55 v_addr.pkt_bits = 0;
56 v_addr.valid_bits = 0;
57 v_addr_ISA = 0;
58
59 // timestamp
60 ts.bits_changed = 0;
61 ts.timestamp = 0;
62
63 // per packet init
64 initNextPacket();
65 }
66
initNextPacket()67 void EtmV4ITrcPacket::initNextPacket()
68 {
69 // clear valid bits for elements that are only valid over a single packet.
70 pkt_valid.bits.cc_valid = 0;
71 pkt_valid.bits.commit_elem_valid = 0;
72 atom.num = 0;
73 context.updated = 0;
74 context.updated_v = 0;
75 context.updated_c = 0;
76 err_type = ETM4_PKT_I_NO_ERR_TYPE;
77 }
78
79 // printing
toString(std::string & str) const80 void EtmV4ITrcPacket::toString(std::string &str) const
81 {
82 const char *name;
83 const char *desc;
84 std::string valStr, ctxtStr = "";
85
86 name = packetTypeName(type, &desc);
87 str = name + (std::string)" : " + desc;
88
89 // extended descriptions
90 switch (type)
91 {
92 case ETM4_PKT_I_BAD_SEQUENCE:
93 case ETM4_PKT_I_INCOMPLETE_EOT:
94 case ETM4_PKT_I_RESERVED_CFG:
95 name = packetTypeName(err_type, 0);
96 str += "[" + (std::string)name + "]";
97 break;
98
99 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
100 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
101 contextStr(ctxtStr);
102 case ETM4_PKT_I_ADDR_L_32IS0:
103 case ETM4_PKT_I_ADDR_L_32IS1:
104 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 32) ? v_addr.pkt_bits : 0);
105 str += "; Addr=" + valStr + "; " + ctxtStr;
106 break;
107
108 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
109 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
110 contextStr(ctxtStr);
111 case ETM4_PKT_I_ADDR_L_64IS0:
112 case ETM4_PKT_I_ADDR_L_64IS1:
113 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, (v_addr.pkt_bits < 64) ? v_addr.pkt_bits : 0);
114 str += "; Addr=" + valStr + "; " + ctxtStr;
115 break;
116
117 case ETM4_PKT_I_CTXT:
118 contextStr(ctxtStr);
119 str += "; " + ctxtStr;
120 break;
121
122 case ETM4_PKT_I_ADDR_S_IS0:
123 case ETM4_PKT_I_ADDR_S_IS1:
124 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true, v_addr.pkt_bits);
125 str += "; Addr=" + valStr;
126 break;
127
128 case ETM4_PKT_I_ADDR_MATCH:
129 addrMatchIdx(valStr);
130 str += ", " + valStr;
131 trcPrintableElem::getValStr(valStr, (v_addr.size == VA_64BIT) ? 64 : 32, v_addr.valid_bits, v_addr.val, true);
132 str += "; Addr=" + valStr + "; " + ctxtStr;
133 break;
134
135 case ETM4_PKT_I_ATOM_F1:
136 case ETM4_PKT_I_ATOM_F2:
137 case ETM4_PKT_I_ATOM_F3:
138 case ETM4_PKT_I_ATOM_F4:
139 case ETM4_PKT_I_ATOM_F5:
140 case ETM4_PKT_I_ATOM_F6:
141 atomSeq(valStr);
142 str += "; " + valStr;
143 break;
144
145 case ETM4_PKT_I_EXCEPT:
146 exceptionInfo(valStr);
147 str += "; " + valStr;
148 break;
149
150 case ETM4_PKT_I_TIMESTAMP:
151 {
152 std::ostringstream oss;
153 oss << "; Updated val = " << std::hex << "0x" << ts.timestamp;
154 if (pkt_valid.bits.cc_valid)
155 oss << "; CC=" << std::hex << "0x" << cycle_count;
156 str += oss.str();
157 }
158 break;
159
160 case ETM4_PKT_I_TRACE_INFO:
161 {
162 std::ostringstream oss;
163 oss << "; INFO=" << std::hex << "0x" << trace_info.val;
164 oss << " { CC." << std::dec << trace_info.bits.cc_enabled << " }";
165 if (trace_info.bits.cc_enabled)
166 oss << "; CC_THRESHOLD=" << std::hex << "0x" << cc_threshold;
167 str += oss.str();
168 }
169 break;
170
171 case ETM4_PKT_I_CCNT_F1:
172 case ETM4_PKT_I_CCNT_F2:
173 case ETM4_PKT_I_CCNT_F3:
174 {
175 std::ostringstream oss;
176 oss << "; Count=" << std::hex << "0x" << cycle_count;
177 str += oss.str();
178 }
179 break;
180
181 case ETM4_PKT_I_CANCEL_F1:
182 {
183 std::ostringstream oss;
184 oss << "; Cancel(" << std::dec << cancel_elements << ")";
185 str += oss.str();
186 }
187 break;
188
189 case ETM4_PKT_I_CANCEL_F1_MISPRED:
190 {
191 std::ostringstream oss;
192 oss << "; Cancel(" << std::dec << cancel_elements << "), Mispredict";
193 str += oss.str();
194 }
195 break;
196
197 case ETM4_PKT_I_MISPREDICT:
198 {
199 std::ostringstream oss;
200 oss << "; ";
201 if (atom.num) {
202 atomSeq(valStr);
203 oss << "Atom: " << valStr << ", ";
204 }
205 oss << "Mispredict";
206 str += oss.str();
207 }
208 break;
209
210 case ETM4_PKT_I_CANCEL_F2:
211 {
212 std::ostringstream oss;
213 oss << "; ";
214 if (atom.num) {
215 atomSeq(valStr);
216 oss << "Atom: " << valStr << ", ";
217 }
218 oss << "Cancel(1), Mispredict";
219 str += oss.str();
220 }
221 break;
222
223 case ETM4_PKT_I_CANCEL_F3:
224 {
225 std::ostringstream oss;
226 oss << "; ";
227 if (atom.num) {
228 oss << "Atom: E, ";
229 }
230 oss << "Cancel(" << std::dec << cancel_elements << "), Mispredict";
231 str += oss.str();
232 }
233 break;
234
235 case ETM4_PKT_I_COMMIT:
236 {
237 std::ostringstream oss;
238 oss << "; Commit(" << std::dec << commit_elements << ")";
239 str += oss.str();
240 }
241 break;
242 }
243 }
244
toStringFmt(const uint32_t fmtFlags,std::string & str) const245 void EtmV4ITrcPacket::toStringFmt(const uint32_t fmtFlags, std::string &str) const
246 {
247 toString(str); // TBD add in formatted response.
248 }
249
packetTypeName(const ocsd_etmv4_i_pkt_type type,const char ** ppDesc) const250 const char *EtmV4ITrcPacket::packetTypeName(const ocsd_etmv4_i_pkt_type type, const char **ppDesc) const
251 {
252 const char *pName = "I_UNKNOWN";
253 const char *pDesc = "Unknown Packet Header";
254
255 switch(type)
256 {
257 case ETM4_PKT_I_NOTSYNC:
258 pName = "I_NOT_SYNC";
259 pDesc = "I Stream not synchronised";
260 break;
261
262 case ETM4_PKT_I_INCOMPLETE_EOT:
263 pName = "I_INCOMPLETE_EOT";
264 pDesc = "Incomplete packet at end of trace.";
265 break;
266
267 case ETM4_PKT_I_NO_ERR_TYPE:
268 pName = "I_NO_ERR_TYPE";
269 pDesc = "No Error Type.";
270 break;
271
272 case ETM4_PKT_I_BAD_SEQUENCE:
273 pName = "I_BAD_SEQUENCE";
274 pDesc = "Invalid Sequence in packet.";
275 break;
276
277 case ETM4_PKT_I_BAD_TRACEMODE:
278 pName = "I_BAD_TRACEMODE";
279 pDesc = "Invalid Packet for trace mode.";
280 break;
281
282 case ETM4_PKT_I_RESERVED:
283 pName = "I_RESERVED";
284 pDesc = "Reserved Packet Header";
285 break;
286
287 case ETM4_PKT_I_RESERVED_CFG:
288 pName = "I_RESERVED_CFG";
289 pDesc = "Reserved header for current configuration.";
290 break;
291
292 case ETM4_PKT_I_EXTENSION:
293 pName = "I_EXTENSION";
294 pDesc = "Extension packet header.";
295 break;
296
297 case ETM4_PKT_I_TRACE_INFO:
298 pName = "I_TRACE_INFO";
299 pDesc = "Trace Info.";
300 break;
301
302 case ETM4_PKT_I_TIMESTAMP:
303 pName = "I_TIMESTAMP";
304 pDesc = "Timestamp.";
305 break;
306
307 case ETM4_PKT_I_TRACE_ON:
308 pName = "I_TRACE_ON";
309 pDesc = "Trace On.";
310 break;
311
312 case ETM4_PKT_I_FUNC_RET:
313 pName = "I_FUNC_RET";
314 pDesc = "V8M - function return.";
315 break;
316
317 case ETM4_PKT_I_EXCEPT:
318 pName = "I_EXCEPT";
319 pDesc = "Exception.";
320 break;
321
322 case ETM4_PKT_I_EXCEPT_RTN:
323 pName = "I_EXCEPT_RTN";
324 pDesc = "Exception Return.";
325 break;
326
327 case ETM4_PKT_I_CCNT_F1:
328 pName = "I_CCNT_F1";
329 pDesc = "Cycle Count format 1.";
330 break;
331
332 case ETM4_PKT_I_CCNT_F2:
333 pName = "I_CCNT_F2";
334 pDesc = "Cycle Count format 2.";
335 break;
336
337 case ETM4_PKT_I_CCNT_F3:
338 pName = "I_CCNT_F3";
339 pDesc = "Cycle Count format 3.";
340 break;
341
342 case ETM4_PKT_I_NUM_DS_MKR:
343 pName = "I_NUM_DS_MKR";
344 pDesc = "Data Synchronisation Marker - Numbered.";
345 break;
346
347 case ETM4_PKT_I_UNNUM_DS_MKR:
348 pName = "I_UNNUM_DS_MKR";
349 pDesc = "Data Synchronisation Marker - Unnumbered.";
350 break;
351
352 case ETM4_PKT_I_COMMIT:
353 pName = "I_COMMIT";
354 pDesc = "Commit";
355 break;
356
357 case ETM4_PKT_I_CANCEL_F1:
358 pName = "I_CANCEL_F1";
359 pDesc = "Cancel Format 1.";
360 break;
361
362 case ETM4_PKT_I_CANCEL_F1_MISPRED:
363 pName = "I_CANCEL_F1_MISPRED";
364 pDesc = "Cancel Format 1 + Mispredict.";
365 break;
366
367
368 case ETM4_PKT_I_MISPREDICT:
369 pName = "I_MISPREDICT";
370 pDesc = "Mispredict.";
371 break;
372
373 case ETM4_PKT_I_CANCEL_F2:
374 pName = "I_CANCEL_F2";
375 pDesc = "Cancel Format 2.";
376 break;
377
378 case ETM4_PKT_I_CANCEL_F3:
379 pName = "I_CANCEL_F3";
380 pDesc = "Cancel Format 3.";
381 break;
382
383 case ETM4_PKT_I_COND_I_F2:
384 pName = "I_COND_I_F2";
385 pDesc = "Conditional Instruction, format 2.";
386 break;
387
388 case ETM4_PKT_I_COND_FLUSH:
389 pName = "I_COND_FLUSH";
390 pDesc = "Conditional Flush.";
391 break;
392
393 case ETM4_PKT_I_COND_RES_F4:
394 pName = "I_COND_RES_F4";
395 pDesc = "Conditional Result, format 4.";
396 break;
397
398 case ETM4_PKT_I_COND_RES_F2:
399 pName = "I_COND_RES_F2";
400 pDesc = "Conditional Result, format 2.";
401 break;
402
403 case ETM4_PKT_I_COND_RES_F3:
404 pName = "I_COND_RES_F3";
405 pDesc = "Conditional Result, format 3.";
406 break;
407
408 case ETM4_PKT_I_COND_RES_F1:
409 pName = "I_COND_RES_F1";
410 pDesc = "Conditional Result, format 1.";
411 break;
412
413 case ETM4_PKT_I_COND_I_F1:
414 pName = "I_COND_I_F1";
415 pDesc = "Conditional Instruction, format 1.";
416 break;
417
418 case ETM4_PKT_I_COND_I_F3:
419 pName = "I_COND_I_F3";
420 pDesc = "Conditional Instruction, format 3.";
421 break;
422
423 case ETM4_PKT_I_IGNORE:
424 pName = "I_IGNORE";
425 pDesc = "Ignore.";
426 break;
427
428 case ETM4_PKT_I_EVENT:
429 pName = "I_EVENT";
430 pDesc = "Trace Event.";
431 break;
432
433 case ETM4_PKT_I_CTXT:
434 pName = "I_CTXT";
435 pDesc = "Context Packet.";
436 break;
437
438 case ETM4_PKT_I_ADDR_CTXT_L_32IS0:
439 pName = "I_ADDR_CTXT_L_32IS0";
440 pDesc = "Address & Context, Long, 32 bit, IS0.";
441 break;
442
443 case ETM4_PKT_I_ADDR_CTXT_L_32IS1:
444 pName = "I_ADDR_CTXT_L_32IS1";
445 pDesc = "Address & Context, Long, 32 bit, IS0.";
446 break;
447
448 case ETM4_PKT_I_ADDR_CTXT_L_64IS0:
449 pName = "I_ADDR_CTXT_L_64IS0";
450 pDesc = "Address & Context, Long, 64 bit, IS0.";
451 break;
452
453 case ETM4_PKT_I_ADDR_CTXT_L_64IS1:
454 pName = "I_ADDR_CTXT_L_64IS1";
455 pDesc = "Address & Context, Long, 64 bit, IS1.";
456 break;
457
458 case ETM4_PKT_I_ADDR_MATCH:
459 pName = "I_ADDR_MATCH";
460 pDesc = "Exact Address Match.";
461 break;
462
463 case ETM4_PKT_I_ADDR_S_IS0:
464 pName = "I_ADDR_S_IS0";
465 pDesc = "Address, Short, IS0.";
466 break;
467
468 case ETM4_PKT_I_ADDR_S_IS1:
469 pName = "I_ADDR_S_IS1";
470 pDesc = "Address, Short, IS1.";
471 break;
472
473 case ETM4_PKT_I_ADDR_L_32IS0:
474 pName = "I_ADDR_L_32IS0";
475 pDesc = "Address, Long, 32 bit, IS0.";
476 break;
477
478 case ETM4_PKT_I_ADDR_L_32IS1:
479 pName = "I_ADDR_L_32IS1";
480 pDesc = "Address, Long, 32 bit, IS1.";
481 break;
482
483 case ETM4_PKT_I_ADDR_L_64IS0:
484 pName = "I_ADDR_L_64IS0";
485 pDesc = "Address, Long, 64 bit, IS0.";
486 break;
487
488 case ETM4_PKT_I_ADDR_L_64IS1:
489 pName = "I_ADDR_L_64IS1";
490 pDesc = "Address, Long, 64 bit, IS1.";
491 break;
492
493 case ETM4_PKT_I_Q:
494 pName = "I_Q";
495 pDesc = "Q Packet.";
496 break;
497
498 case ETM4_PKT_I_ATOM_F6:
499 pName = "I_ATOM_F6";
500 pDesc = "Atom format 6.";
501 break;
502
503 case ETM4_PKT_I_ATOM_F5:
504 pName = "I_ATOM_F5";
505 pDesc = "Atom format 5.";
506 break;
507
508 case ETM4_PKT_I_ATOM_F2:
509 pName = "I_ATOM_F2";
510 pDesc = "Atom format 2.";
511 break;
512
513 case ETM4_PKT_I_ATOM_F4:
514 pName = "I_ATOM_F4";
515 pDesc = "Atom format 4.";
516 break;
517
518 case ETM4_PKT_I_ATOM_F1:
519 pName = "I_ATOM_F1";
520 pDesc = "Atom format 1.";
521 break;
522
523 case ETM4_PKT_I_ATOM_F3:
524 pName = "I_ATOM_F3";
525 pDesc = "Atom format 3.";
526 break;
527
528 case ETM4_PKT_I_ASYNC:
529 pName = "I_ASYNC";
530 pDesc = "Alignment Synchronisation.";
531 break;
532
533 case ETM4_PKT_I_DISCARD:
534 pName = "I_DISCARD";
535 pDesc = "Discard.";
536 break;
537
538 case ETM4_PKT_I_OVERFLOW:
539 pName = "I_OVERFLOW";
540 pDesc = "Overflow.";
541 break;
542
543 default:
544 break;
545 }
546
547 if(ppDesc) *ppDesc = pDesc;
548 return pName;
549 }
550
contextStr(std::string & ctxtStr) const551 void EtmV4ITrcPacket::contextStr(std::string &ctxtStr) const
552 {
553 ctxtStr = "";
554 if(pkt_valid.bits.context_valid)
555 {
556 std::ostringstream oss;
557 if(context.updated)
558 {
559 oss << "Ctxt: " << (context.SF ? "AArch64," : "AArch32, ") << "EL" << context.EL << ", " << (context.NS ? "NS; " : "S; ");
560 if(context.updated_c)
561 {
562 oss << "CID=0x" << std::hex << std::setfill('0') << std::setw(8) << context.ctxtID << "; ";
563 }
564 if(context.updated_v)
565 {
566 oss << "VMID=0x" << std::hex << std::setfill('0') << std::setw(4) << context.VMID << "; ";
567 }
568 }
569 else
570 {
571 oss << "Ctxt: Same";
572 }
573 ctxtStr = oss.str();
574 }
575 }
576
atomSeq(std::string & valStr) const577 void EtmV4ITrcPacket::atomSeq(std::string &valStr) const
578 {
579 std::ostringstream oss;
580 uint32_t bitpattern = atom.En_bits;
581 for(int i = 0; i < atom.num; i++)
582 {
583 oss << ((bitpattern & 0x1) ? "E" : "N");
584 bitpattern >>= 1;
585 }
586 valStr = oss.str();
587 }
588
addrMatchIdx(std::string & valStr) const589 void EtmV4ITrcPacket::addrMatchIdx(std::string &valStr) const
590 {
591 std::ostringstream oss;
592 oss << "[" << (uint16_t)addr_exact_match_idx << "]";
593 valStr = oss.str();
594 }
595
exceptionInfo(std::string & valStr) const596 void EtmV4ITrcPacket::exceptionInfo(std::string &valStr) const
597 {
598 std::ostringstream oss;
599
600 static const char *ARv8Excep[] = {
601 "PE Reset", "Debug Halt", "Call", "Trap",
602 "System Error", "Reserved", "Inst Debug", "Data Debug",
603 "Reserved", "Reserved", "Alignment", "Inst Fault",
604 "Data Fault", "Reserved", "IRQ", "FIQ"
605 };
606
607 static const char *MExcep[] = {
608 "Reserved", "PE Reset", "NMI", "HardFault",
609 "MemManage", "BusFault", "UsageFault", "Reserved",
610 "Reserved","Reserved","Reserved","SVC",
611 "DebugMonitor", "Reserved","PendSV","SysTick",
612 "IRQ0","IRQ1","IRQ2","IRQ3",
613 "IRQ4","IRQ5","IRQ6","IRQ7",
614 "DebugHalt", "LazyFP Push", "Lockup", "Reserved",
615 "Reserved","Reserved","Reserved","Reserved"
616 };
617
618 if(exception_info.m_type == 0)
619 {
620 if(exception_info.exceptionType < 0x10)
621 oss << " " << ARv8Excep[exception_info.exceptionType] << ";";
622 else
623 oss << " Reserved;";
624
625 }
626 else
627 {
628 if(exception_info.exceptionType < 0x20)
629 oss << " " << MExcep[exception_info.exceptionType] << ";";
630 else if((exception_info.exceptionType >= 0x208) && (exception_info.exceptionType <= 0x3EF))
631 oss << " IRQ" << (int)(exception_info.exceptionType - 0x200) << ";";
632 else
633 oss << " Reserved;";
634 if(exception_info.m_fault_pending)
635 oss << " Fault Pending;";
636 }
637
638 if(exception_info.addr_interp == 0x1)
639 oss << " Ret Addr Follows;";
640 else if(exception_info.addr_interp == 0x2)
641 oss << " Ret Addr Follows, Match Prev;";
642
643 valStr = oss.str();
644 }
645
operator =(const ocsd_etmv4_i_pkt * p_pkt)646 EtmV4ITrcPacket &EtmV4ITrcPacket::operator =(const ocsd_etmv4_i_pkt* p_pkt)
647 {
648 *dynamic_cast<ocsd_etmv4_i_pkt *>(this) = *p_pkt;
649 return *this;
650 }
651
652 /* End of File trc_pkt_elem_etmv4i.cpp */
653