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1/*
2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef CPU_MACROS_S
7#define CPU_MACROS_S
8
9#include <arch.h>
10#include <assert_macros.S>
11#include <lib/cpus/errata_report.h>
12
13#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
14				(MIDR_PN_MASK << MIDR_PN_SHIFT)
15
16/* The number of CPU operations allowed */
17#define CPU_MAX_PWR_DWN_OPS		2
18
19/* Special constant to specify that CPU has no reset function */
20#define CPU_NO_RESET_FUNC		0
21
22#define CPU_NO_EXTRA1_FUNC		0
23#define CPU_NO_EXTRA2_FUNC		0
24
25/* Word size for 64-bit CPUs */
26#define CPU_WORD_SIZE			8
27
28#if defined(IMAGE_BL1) || defined(IMAGE_BL31) ||(defined(IMAGE_BL2) && BL2_AT_EL3)
29#define IMAGE_AT_EL3
30#endif
31
32/*
33 * Whether errata status needs reporting. Errata status is printed in debug
34 * builds for both BL1 and BL31 images.
35 */
36#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
37# define REPORT_ERRATA	1
38#else
39# define REPORT_ERRATA	0
40#endif
41
42
43	.equ	CPU_MIDR_SIZE, CPU_WORD_SIZE
44	.equ	CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
45	.equ	CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
46	.equ	CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
47	.equ	CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
48	.equ	CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
49	.equ	CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
50	.equ	CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
51	.equ	CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
52	.equ	CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
53
54#ifndef IMAGE_AT_EL3
55	.equ	CPU_RESET_FUNC_SIZE, 0
56#endif
57
58/* The power down core and cluster is needed only in BL31 */
59#ifndef IMAGE_BL31
60	.equ	CPU_PWR_DWN_OPS_SIZE, 0
61#endif
62
63/* Fields required to print errata status. */
64#if !REPORT_ERRATA
65	.equ	CPU_ERRATA_FUNC_SIZE, 0
66#endif
67
68/* Only BL31 requieres mutual exclusion and printed flag.  */
69#if !(REPORT_ERRATA && defined(IMAGE_BL31))
70	.equ	CPU_ERRATA_LOCK_SIZE, 0
71	.equ	CPU_ERRATA_PRINTED_SIZE, 0
72#endif
73
74#if !defined(IMAGE_BL31) || !CRASH_REPORTING
75	.equ	CPU_REG_DUMP_SIZE, 0
76#endif
77
78/*
79 * Define the offsets to the fields in cpu_ops structure.
80 * Every offset is defined based in the offset and size of the previous
81 * field.
82 */
83	.equ	CPU_MIDR, 0
84	.equ	CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
85	.equ	CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
86	.equ	CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
87	.equ	CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
88	.equ	CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
89	.equ	CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
90	.equ	CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
91	.equ	CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
92	.equ	CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
93	.equ	CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
94
95	/*
96	 * Write given expressions as quad words
97	 *
98	 * _count:
99	 *	Write at least _count quad words. If the given number of
100	 *	expressions is less than _count, repeat the last expression to
101	 *	fill _count quad words in total
102	 * _rest:
103	 *	Optional list of expressions. _this is for parameter extraction
104	 *	only, and has no significance to the caller
105	 *
106	 * Invoked as:
107	 *	fill_constants 2, foo, bar, blah, ...
108	 */
109	.macro fill_constants _count:req, _this, _rest:vararg
110	  .ifgt \_count
111	    /* Write the current expression */
112	    .ifb \_this
113	      .error "Nothing to fill"
114	    .endif
115	    .quad \_this
116
117	    /* Invoke recursively for remaining expressions */
118	    .ifnb \_rest
119	      fill_constants \_count-1, \_rest
120	    .else
121	      fill_constants \_count-1, \_this
122	    .endif
123	  .endif
124	.endm
125
126	/*
127	 * Declare CPU operations
128	 *
129	 * _name:
130	 *	Name of the CPU for which operations are being specified
131	 * _midr:
132	 *	Numeric value expected to read from CPU's MIDR
133	 * _resetfunc:
134	 *	Reset function for the CPU. If there's no CPU reset function,
135	 *	specify CPU_NO_RESET_FUNC
136	 * _extra1:
137	 *	This is a placeholder for future per CPU operations.  Currently,
138	 *	some CPUs use this entry to set a test function to determine if
139	 *	the workaround for CVE-2017-5715 needs to be applied or not.
140	 * _extra2:
141	 *	This is a placeholder for future per CPU operations.  Currently
142	 *	some CPUs use this entry to set a function to disable the
143	 *	workaround for CVE-2018-3639.
144	 * _e_handler:
145	 *	This is a placeholder for future per CPU exception handlers.
146	 * _power_down_ops:
147	 *	Comma-separated list of functions to perform power-down
148	 *	operatios on the CPU. At least one, and up to
149	 *	CPU_MAX_PWR_DWN_OPS number of functions may be specified.
150	 *	Starting at power level 0, these functions shall handle power
151	 *	down at subsequent power levels. If there aren't exactly
152	 *	CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
153	 *	used to handle power down at subsequent levels
154	 */
155	.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
156		_extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg
157	.section cpu_ops, "a"
158	.align 3
159	.type cpu_ops_\_name, %object
160	.quad \_midr
161#if defined(IMAGE_AT_EL3)
162	.quad \_resetfunc
163#endif
164	.quad \_extra1
165	.quad \_extra2
166	.quad \_e_handler
167#ifdef IMAGE_BL31
168	/* Insert list of functions */
169	fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
170#endif
171
172#if REPORT_ERRATA
173	.ifndef \_name\()_cpu_str
174	  /*
175	   * Place errata reported flag, and the spinlock to arbitrate access to
176	   * it in the data section.
177	   */
178	  .pushsection .data
179	  define_asm_spinlock \_name\()_errata_lock
180	  \_name\()_errata_reported:
181	  .word	0
182	  .popsection
183
184	  /* Place CPU string in rodata */
185	  .pushsection .rodata
186	  \_name\()_cpu_str:
187	  .asciz "\_name"
188	  .popsection
189	.endif
190
191	/*
192	 * Mandatory errata status printing function for CPUs of
193	 * this class.
194	 */
195	.quad \_name\()_errata_report
196
197#ifdef IMAGE_BL31
198	/* Pointers to errata lock and reported flag */
199	.quad \_name\()_errata_lock
200	.quad \_name\()_errata_reported
201#endif
202#endif
203
204#if defined(IMAGE_BL31) && CRASH_REPORTING
205	.quad \_name\()_cpu_reg_dump
206#endif
207	.endm
208
209	.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
210		_power_down_ops:vararg
211		declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \
212			\_power_down_ops
213	.endm
214
215	.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
216		_e_handler:req, _power_down_ops:vararg
217		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
218			0, 0, \_e_handler, \_power_down_ops
219	.endm
220
221	.macro declare_cpu_ops_wa _name:req, _midr:req, \
222		_resetfunc:req, _extra1:req, _extra2:req, \
223		_power_down_ops:vararg
224		declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
225			\_extra1, \_extra2, 0, \_power_down_ops
226	.endm
227
228#if REPORT_ERRATA
229	/*
230	 * Print status of a CPU errata
231	 *
232	 * _chosen:
233	 *	Identifier indicating whether or not a CPU errata has been
234	 *	compiled in.
235	 * _cpu:
236	 *	Name of the CPU
237	 * _id:
238	 *	Errata identifier
239	 * _rev_var:
240	 *	Register containing the combined value CPU revision and variant
241	 *	- typically the return value of cpu_get_rev_var
242	 */
243	.macro report_errata _chosen, _cpu, _id, _rev_var=x8
244	/* Stash a string with errata ID */
245	.pushsection .rodata
246	\_cpu\()_errata_\_id\()_str:
247	.asciz	"\_id"
248	.popsection
249
250	/* Check whether errata applies */
251	mov	x0, \_rev_var
252	/* Shall clobber: x0-x7 */
253	bl	check_errata_\_id
254
255	.ifeq \_chosen
256	/*
257	 * Errata workaround has not been compiled in. If the errata would have
258	 * applied had it been compiled in, print its status as missing.
259	 */
260	cbz	x0, 900f
261	mov	x0, #ERRATA_MISSING
262	.endif
263900:
264	adr	x1, \_cpu\()_cpu_str
265	adr	x2, \_cpu\()_errata_\_id\()_str
266	bl	errata_print_msg
267	.endm
268#endif
269
270	/*
271	 * This macro is used on some CPUs to detect if they are vulnerable
272	 * to CVE-2017-5715.
273	 */
274	.macro	cpu_check_csv2 _reg _label
275	mrs	\_reg, id_aa64pfr0_el1
276	ubfx	\_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
277	/*
278	 * If the field equals 1, branch targets trained in one context cannot
279	 * affect speculative execution in a different context.
280	 *
281	 * If the field equals 2, it means that the system is also aware of
282	 * SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
283	 * expect users of the registers to do the right thing.
284	 *
285	 * Only apply mitigations if the value of this field is 0.
286	 */
287#if ENABLE_ASSERTIONS
288	cmp	\_reg, #3 /* Only values 0 to 2 are expected */
289	ASM_ASSERT(lo)
290#endif
291
292	cmp	\_reg, #0
293	bne	\_label
294	.endm
295
296	/*
297	 * Helper macro that reads the part number of the current
298	 * CPU and jumps to the given label if it matches the CPU
299	 * MIDR provided.
300	 *
301	 * Clobbers x0.
302	 */
303	.macro  jump_if_cpu_midr _cpu_midr, _label
304	mrs	x0, midr_el1
305	ubfx	x0, x0, MIDR_PN_SHIFT, #12
306	cmp	w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
307	b.eq	\_label
308	.endm
309
310#endif /* CPU_MACROS_S */
311