1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2014 Google Inc.
4 * Copyright (c) 2016 Google, Inc
5 * Copyright (C) 2015-2018 Intel Corporation.
6 * Copyright (C) 2018 Siemens AG
7 * Some code taken from coreboot cpulib.c
8 */
9
10 #include <common.h>
11 #include <cpu.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <asm/cpu.h>
15 #include <asm/cpu_common.h>
16 #include <asm/intel_regs.h>
17 #include <asm/lapic.h>
18 #include <asm/lpc_common.h>
19 #include <asm/msr.h>
20 #include <asm/mtrr.h>
21 #include <asm/post.h>
22 #include <asm/microcode.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
report_bist_failure(void)26 static int report_bist_failure(void)
27 {
28 if (gd->arch.bist != 0) {
29 post_code(POST_BIST_FAILURE);
30 printf("BIST failed: %08x\n", gd->arch.bist);
31 return -EFAULT;
32 }
33
34 return 0;
35 }
36
cpu_common_init(void)37 int cpu_common_init(void)
38 {
39 struct udevice *dev, *lpc;
40 int ret;
41
42 /* Halt if there was a built in self test failure */
43 ret = report_bist_failure();
44 if (ret)
45 return ret;
46
47 enable_lapic();
48
49 ret = microcode_update_intel();
50 if (ret && ret != -EEXIST) {
51 debug("%s: Microcode update failure (err=%d)\n", __func__, ret);
52 return ret;
53 }
54
55 /* Enable upper 128bytes of CMOS */
56 writel(1 << 2, RCB_REG(RC));
57
58 /* Early chipset init required before RAM init can work */
59 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
60
61 ret = uclass_first_device(UCLASS_LPC, &lpc);
62 if (ret)
63 return ret;
64 if (!lpc)
65 return -ENODEV;
66
67 /* Cause the SATA device to do its early init */
68 uclass_first_device(UCLASS_AHCI, &dev);
69
70 return 0;
71 }
72
cpu_set_flex_ratio_to_tdp_nominal(void)73 int cpu_set_flex_ratio_to_tdp_nominal(void)
74 {
75 msr_t flex_ratio, msr;
76 u8 nominal_ratio;
77
78 /* Check for Flex Ratio support */
79 flex_ratio = msr_read(MSR_FLEX_RATIO);
80 if (!(flex_ratio.lo & FLEX_RATIO_EN))
81 return -EINVAL;
82
83 /* Check for >0 configurable TDPs */
84 msr = msr_read(MSR_PLATFORM_INFO);
85 if (((msr.hi >> 1) & 3) == 0)
86 return -EINVAL;
87
88 /* Use nominal TDP ratio for flex ratio */
89 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
90 nominal_ratio = msr.lo & 0xff;
91
92 /* See if flex ratio is already set to nominal TDP ratio */
93 if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
94 return 0;
95
96 /* Set flex ratio to nominal TDP ratio */
97 flex_ratio.lo &= ~0xff00;
98 flex_ratio.lo |= nominal_ratio << 8;
99 flex_ratio.lo |= FLEX_RATIO_LOCK;
100 msr_write(MSR_FLEX_RATIO, flex_ratio);
101
102 /* Set flex ratio in soft reset data register bits 11:6 */
103 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
104 (nominal_ratio & 0x3f) << 6);
105
106 debug("CPU: Soft reset to set up flex ratio\n");
107
108 /* Set soft reset control to use register value */
109 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
110
111 /* Issue warm reset, will be "CPU only" due to soft reset data */
112 outb(0x0, IO_PORT_RESET);
113 outb(SYS_RST | RST_CPU, IO_PORT_RESET);
114 cpu_hlt();
115
116 /* Not reached */
117 return -EINVAL;
118 }
119
cpu_intel_get_info(struct cpu_info * info,int bclk)120 int cpu_intel_get_info(struct cpu_info *info, int bclk)
121 {
122 msr_t msr;
123
124 msr = msr_read(MSR_IA32_PERF_CTL);
125 info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
126 info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
127 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
128
129 return 0;
130 }
131
cpu_configure_thermal_target(struct udevice * dev)132 int cpu_configure_thermal_target(struct udevice *dev)
133 {
134 u32 tcc_offset;
135 msr_t msr;
136 int ret;
137
138 ret = dev_read_u32(dev, "tcc-offset", &tcc_offset);
139 if (!ret)
140 return -ENOENT;
141
142 /* Set TCC activaiton offset if supported */
143 msr = msr_read(MSR_PLATFORM_INFO);
144 if (msr.lo & (1 << 30)) {
145 msr = msr_read(MSR_TEMPERATURE_TARGET);
146 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
147 msr.lo |= (tcc_offset & 0xf) << 24;
148 msr_write(MSR_TEMPERATURE_TARGET, msr);
149 }
150
151 return 0;
152 }
153
cpu_set_perf_control(uint clk_ratio)154 void cpu_set_perf_control(uint clk_ratio)
155 {
156 msr_t perf_ctl;
157
158 perf_ctl.lo = (clk_ratio & 0xff) << 8;
159 perf_ctl.hi = 0;
160 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
161 debug("CPU: frequency set to %d MHz\n", clk_ratio * INTEL_BCLK_MHZ);
162 }
163
cpu_config_tdp_levels(void)164 bool cpu_config_tdp_levels(void)
165 {
166 msr_t platform_info;
167
168 /* Bits 34:33 indicate how many levels supported */
169 platform_info = msr_read(MSR_PLATFORM_INFO);
170
171 return ((platform_info.hi >> 1) & 3) != 0;
172 }
173
cpu_set_p_state_to_turbo_ratio(void)174 void cpu_set_p_state_to_turbo_ratio(void)
175 {
176 msr_t msr;
177
178 msr = msr_read(MSR_TURBO_RATIO_LIMIT);
179 cpu_set_perf_control(msr.lo);
180 }
181
cpu_get_burst_mode_state(void)182 enum burst_mode_t cpu_get_burst_mode_state(void)
183 {
184 enum burst_mode_t state;
185 int burst_en, burst_cap;
186 msr_t msr;
187 uint eax;
188
189 eax = cpuid_eax(0x6);
190 burst_cap = eax & 0x2;
191 msr = msr_read(MSR_IA32_MISC_ENABLE);
192 burst_en = !(msr.hi & BURST_MODE_DISABLE);
193
194 if (!burst_cap && burst_en)
195 state = BURST_MODE_UNAVAILABLE;
196 else if (burst_cap && !burst_en)
197 state = BURST_MODE_DISABLED;
198 else if (burst_cap && burst_en)
199 state = BURST_MODE_ENABLED;
200 else
201 state = BURST_MODE_UNKNOWN;
202
203 return state;
204 }
205
cpu_set_burst_mode(bool burst_mode)206 void cpu_set_burst_mode(bool burst_mode)
207 {
208 msr_t msr;
209
210 msr = msr_read(MSR_IA32_MISC_ENABLE);
211 if (burst_mode)
212 msr.hi &= ~BURST_MODE_DISABLE;
213 else
214 msr.hi |= BURST_MODE_DISABLE;
215 msr_write(MSR_IA32_MISC_ENABLE, msr);
216 }
217
cpu_set_eist(bool eist_status)218 void cpu_set_eist(bool eist_status)
219 {
220 msr_t msr;
221
222 msr = msr_read(MSR_IA32_MISC_ENABLE);
223 if (eist_status)
224 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
225 else
226 msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
227 msr_write(MSR_IA32_MISC_ENABLE, msr);
228 }
229