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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Davinci MMC Controller Driver
4  *
5  * Copyright (C) 2010 Texas Instruments Incorporated
6  */
7 
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <mmc.h>
13 #include <command.h>
14 #include <part.h>
15 #include <malloc.h>
16 #include <asm/io.h>
17 #include <asm/arch/sdmmc_defs.h>
18 #include <asm-generic/gpio.h>
19 
20 #define DAVINCI_MAX_BLOCKS	(32)
21 #define WATCHDOG_COUNT		(100000)
22 
23 #define get_val(addr)		REG(addr)
24 #define set_val(addr, val)	REG(addr) = (val)
25 #define set_bit(addr, val)	set_val((addr), (get_val(addr) | (val)))
26 #define clear_bit(addr, val)	set_val((addr), (get_val(addr) & ~(val)))
27 
28 #ifdef CONFIG_DM_MMC
29 /* Davinci MMC board definitions */
30 struct davinci_mmc_priv {
31 	struct davinci_mmc_regs *reg_base;	/* Register base address */
32 	uint input_clk;		/* Input clock to MMC controller */
33 	struct gpio_desc cd_gpio;       /* Card Detect GPIO */
34 	struct gpio_desc wp_gpio;       /* Write Protect GPIO */
35 };
36 
37 struct davinci_mmc_plat
38 {
39 	struct mmc_config cfg;
40 	struct mmc mmc;
41 };
42 #endif
43 
44 /* Set davinci clock prescalar value based on the required clock in HZ */
45 #if !CONFIG_IS_ENABLED(DM_MMC)
dmmc_set_clock(struct mmc * mmc,uint clock)46 static void dmmc_set_clock(struct mmc *mmc, uint clock)
47 {
48 	struct davinci_mmc *host = mmc->priv;
49 #else
50 
51 static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
52 {
53 	struct davinci_mmc_priv *host = dev_get_priv(dev);
54         struct mmc *mmc = mmc_get_mmc_dev(dev);
55 #endif
56 	struct davinci_mmc_regs *regs = host->reg_base;
57 	uint clkrt, sysclk2, act_clock;
58 
59 	if (clock < mmc->cfg->f_min)
60 		clock = mmc->cfg->f_min;
61 	if (clock > mmc->cfg->f_max)
62 		clock = mmc->cfg->f_max;
63 
64 	set_val(&regs->mmcclk, 0);
65 	sysclk2 = host->input_clk;
66 	clkrt = (sysclk2 / (2 * clock)) - 1;
67 
68 	/* Calculate the actual clock for the divider used */
69 	act_clock = (sysclk2 / (2 * (clkrt + 1)));
70 
71 	/* Adjust divider if actual clock exceeds the required clock */
72 	if (act_clock > clock)
73 		clkrt++;
74 
75 	/* check clock divider boundary and correct it */
76 	if (clkrt > 0xFF)
77 		clkrt = 0xFF;
78 
79 	set_val(&regs->mmcclk, (clkrt | MMCCLK_CLKEN));
80 }
81 
82 /* Status bit wait loop for MMCST1 */
83 static int
84 dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
85 {
86 	uint wdog = WATCHDOG_COUNT;
87 
88 	while (--wdog && ((get_val(&regs->mmcst1) & status) != status))
89 		udelay(10);
90 
91 	if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT))
92 		udelay(100);
93 
94 	if (wdog == 0)
95 		return -ECOMM;
96 
97 	return 0;
98 }
99 
100 /* Busy bit wait loop for MMCST1 */
101 static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
102 {
103 	uint wdog = WATCHDOG_COUNT;
104 
105 	while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY))
106 		udelay(10);
107 
108 	if (wdog == 0)
109 		return -ECOMM;
110 
111 	return 0;
112 }
113 
114 /* Status bit wait loop for MMCST0 - Checks for error bits as well */
115 static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
116 		uint *cur_st, uint st_ready, uint st_error)
117 {
118 	uint wdog = WATCHDOG_COUNT;
119 	uint mmcstatus = *cur_st;
120 
121 	while (wdog--) {
122 		if (mmcstatus & st_ready) {
123 			*cur_st = mmcstatus;
124 			mmcstatus = get_val(&regs->mmcst1);
125 			return 0;
126 		} else if (mmcstatus & st_error) {
127 			if (mmcstatus & MMCST0_TOUTRS)
128 				return -ETIMEDOUT;
129 			printf("[ ST0 ERROR %x]\n", mmcstatus);
130 			/*
131 			 * Ignore CRC errors as some MMC cards fail to
132 			 * initialize on DM365-EVM on the SD1 slot
133 			 */
134 			if (mmcstatus & MMCST0_CRCRS)
135 				return 0;
136 			return -ECOMM;
137 		}
138 		udelay(10);
139 
140 		mmcstatus = get_val(&regs->mmcst0);
141 	}
142 
143 	printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
144 			get_val(&regs->mmcst1));
145 	return -ECOMM;
146 }
147 
148 /*
149  * Sends a command out on the bus.  Takes the device pointer,
150  * a command pointer, and an optional data pointer.
151  */
152 #if !CONFIG_IS_ENABLED(DM_MMC)
153 static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
154 {
155 	struct davinci_mmc *host = mmc->priv;
156 #else
157 static int
158 davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
159 {
160 	struct davinci_mmc_priv *host = dev_get_priv(dev);
161 #endif
162 	volatile struct davinci_mmc_regs *regs = host->reg_base;
163 	uint mmcstatus, status_rdy, status_err;
164 	uint i, cmddata, bytes_left = 0;
165 	int fifo_words, fifo_bytes, err;
166 	char *data_buf = NULL;
167 
168 	/* Clear status registers */
169 	mmcstatus = get_val(&regs->mmcst0);
170 	fifo_words = 16;
171 	fifo_bytes = fifo_words << 2;
172 
173 	/* Wait for any previous busy signal to be cleared */
174 	dmmc_busy_wait(regs);
175 
176 	cmddata = cmd->cmdidx;
177 	cmddata |= MMCCMD_PPLEN;
178 
179 	/* Send init clock for CMD0 */
180 	if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
181 		cmddata |= MMCCMD_INITCK;
182 
183 	switch (cmd->resp_type) {
184 	case MMC_RSP_R1b:
185 		cmddata |= MMCCMD_BSYEXP;
186 		/* Fall-through */
187 	case MMC_RSP_R1:    /* R1, R1b, R5, R6, R7 */
188 		cmddata |= MMCCMD_RSPFMT_R1567;
189 		break;
190 	case MMC_RSP_R2:
191 		cmddata |= MMCCMD_RSPFMT_R2;
192 		break;
193 	case MMC_RSP_R3: /* R3, R4 */
194 		cmddata |= MMCCMD_RSPFMT_R3;
195 		break;
196 	}
197 
198 	set_val(&regs->mmcim, 0);
199 
200 	if (data) {
201 		/* clear previous data transfer if any and set new one */
202 		bytes_left = (data->blocksize * data->blocks);
203 
204 		/* Reset FIFO - Always use 32 byte fifo threshold */
205 		set_val(&regs->mmcfifoctl,
206 				(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
207 
208 		cmddata |= MMCCMD_DMATRIG;
209 
210 		cmddata |= MMCCMD_WDATX;
211 		if (data->flags == MMC_DATA_READ) {
212 			set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
213 		} else if (data->flags == MMC_DATA_WRITE) {
214 			set_val(&regs->mmcfifoctl,
215 					(MMCFIFOCTL_FIFOLEV |
216 					 MMCFIFOCTL_FIFODIR));
217 			cmddata |= MMCCMD_DTRW;
218 		}
219 
220 		set_val(&regs->mmctod, 0xFFFF);
221 		set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
222 		set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
223 
224 		if (data->flags == MMC_DATA_WRITE) {
225 			uint val;
226 			data_buf = (char *)data->src;
227 			/* For write, fill FIFO with data before issue of CMD */
228 			for (i = 0; (i < fifo_words) && bytes_left; i++) {
229 				memcpy((char *)&val, data_buf, 4);
230 				set_val(&regs->mmcdxr, val);
231 				data_buf += 4;
232 				bytes_left -= 4;
233 			}
234 		}
235 	} else {
236 		set_val(&regs->mmcblen, 0);
237 		set_val(&regs->mmcnblk, 0);
238 	}
239 
240 	set_val(&regs->mmctor, 0x1FFF);
241 
242 	/* Send the command */
243 	set_val(&regs->mmcarghl, cmd->cmdarg);
244 	set_val(&regs->mmccmd, cmddata);
245 
246 	status_rdy = MMCST0_RSPDNE;
247 	status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
248 			MMCST0_CRCWR | MMCST0_CRCRD);
249 	if (cmd->resp_type & MMC_RSP_CRC)
250 		status_err |= MMCST0_CRCRS;
251 
252 	mmcstatus = get_val(&regs->mmcst0);
253 	err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
254 	if (err)
255 		return err;
256 
257 	/* For R1b wait for busy done */
258 	if (cmd->resp_type == MMC_RSP_R1b)
259 		dmmc_busy_wait(regs);
260 
261 	/* Collect response from controller for specific commands */
262 	if (mmcstatus & MMCST0_RSPDNE) {
263 		/* Copy the response to the response buffer */
264 		if (cmd->resp_type & MMC_RSP_136) {
265 			cmd->response[0] = get_val(&regs->mmcrsp67);
266 			cmd->response[1] = get_val(&regs->mmcrsp45);
267 			cmd->response[2] = get_val(&regs->mmcrsp23);
268 			cmd->response[3] = get_val(&regs->mmcrsp01);
269 		} else if (cmd->resp_type & MMC_RSP_PRESENT) {
270 			cmd->response[0] = get_val(&regs->mmcrsp67);
271 		}
272 	}
273 
274 	if (data == NULL)
275 		return 0;
276 
277 	if (data->flags == MMC_DATA_READ) {
278 		/* check for DATDNE along with DRRDY as the controller might
279 		 * set the DATDNE without DRRDY for smaller transfers with
280 		 * less than FIFO threshold bytes
281 		 */
282 		status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
283 		status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
284 		data_buf = data->dest;
285 	} else {
286 		status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
287 		status_err = MMCST0_CRCWR;
288 	}
289 
290 	/* Wait until all of the blocks are transferred */
291 	while (bytes_left) {
292 		err = dmmc_check_status(regs, &mmcstatus, status_rdy,
293 				status_err);
294 		if (err)
295 			return err;
296 
297 		if (data->flags == MMC_DATA_READ) {
298 			/*
299 			 * MMC controller sets the Data receive ready bit
300 			 * (DRRDY) in MMCST0 even before the entire FIFO is
301 			 * full. This results in erratic behavior if we start
302 			 * reading the FIFO soon after DRRDY.  Wait for the
303 			 * FIFO full bit in MMCST1 for proper FIFO clearing.
304 			 */
305 			if (bytes_left > fifo_bytes)
306 				dmmc_wait_fifo_status(regs, 0x4a);
307 			else if (bytes_left == fifo_bytes) {
308 				dmmc_wait_fifo_status(regs, 0x40);
309 				if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
310 					udelay(600);
311 			}
312 
313 			for (i = 0; bytes_left && (i < fifo_words); i++) {
314 				cmddata = get_val(&regs->mmcdrr);
315 				memcpy(data_buf, (char *)&cmddata, 4);
316 				data_buf += 4;
317 				bytes_left -= 4;
318 			}
319 		} else {
320 			/*
321 			 * MMC controller sets the Data transmit ready bit
322 			 * (DXRDY) in MMCST0 even before the entire FIFO is
323 			 * empty. This results in erratic behavior if we start
324 			 * writing the FIFO soon after DXRDY.  Wait for the
325 			 * FIFO empty bit in MMCST1 for proper FIFO clearing.
326 			 */
327 			dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
328 			for (i = 0; bytes_left && (i < fifo_words); i++) {
329 				memcpy((char *)&cmddata, data_buf, 4);
330 				set_val(&regs->mmcdxr, cmddata);
331 				data_buf += 4;
332 				bytes_left -= 4;
333 			}
334 			dmmc_busy_wait(regs);
335 		}
336 	}
337 
338 	err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
339 	if (err)
340 		return err;
341 
342 	return 0;
343 }
344 
345 /* Initialize Davinci MMC controller */
346 #if !CONFIG_IS_ENABLED(DM_MMC)
347 static int dmmc_init(struct mmc *mmc)
348 {
349 	struct davinci_mmc *host = mmc->priv;
350 #else
351 static int davinci_dm_mmc_init(struct udevice *dev)
352 {
353 	struct davinci_mmc_priv *host = dev_get_priv(dev);
354 #endif
355 	struct davinci_mmc_regs *regs = host->reg_base;
356 
357 	/* Clear status registers explicitly - soft reset doesn't clear it
358 	 * If Uboot is invoked from UBL with SDMMC Support, the status
359 	 * registers can have uncleared bits
360 	 */
361 	get_val(&regs->mmcst0);
362 	get_val(&regs->mmcst1);
363 
364 	/* Hold software reset */
365 	set_bit(&regs->mmcctl, MMCCTL_DATRST);
366 	set_bit(&regs->mmcctl, MMCCTL_CMDRST);
367 	udelay(10);
368 
369 	set_val(&regs->mmcclk, 0x0);
370 	set_val(&regs->mmctor, 0x1FFF);
371 	set_val(&regs->mmctod, 0xFFFF);
372 
373 	/* Clear software reset */
374 	clear_bit(&regs->mmcctl, MMCCTL_DATRST);
375 	clear_bit(&regs->mmcctl, MMCCTL_CMDRST);
376 
377 	udelay(10);
378 
379 	/* Reset FIFO - Always use the maximum fifo threshold */
380 	set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
381 	set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
382 
383 	return 0;
384 }
385 
386 /* Set buswidth or clock as indicated by the MMC framework */
387 #if !CONFIG_IS_ENABLED(DM_MMC)
388 static int dmmc_set_ios(struct mmc *mmc)
389 {
390 	struct davinci_mmc *host = mmc->priv;
391 	struct davinci_mmc_regs *regs = host->reg_base;
392 #else
393 static int davinci_mmc_set_ios(struct udevice *dev)
394 {
395 	struct mmc *mmc = mmc_get_mmc_dev(dev);
396 
397 	struct davinci_mmc_priv *host = dev_get_priv(dev);
398 	struct davinci_mmc_regs *regs = host->reg_base;
399 #endif
400 	/* Set the bus width */
401 	if (mmc->bus_width == 4)
402 		set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
403 	else
404 		clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
405 
406 	/* Set clock speed */
407 	if (mmc->clock) {
408 #if !CONFIG_IS_ENABLED(DM_MMC)
409 		dmmc_set_clock(mmc, mmc->clock);
410 #else
411 		davinci_mmc_set_clock(dev, mmc->clock);
412 #endif
413 	}
414 	return 0;
415 }
416 
417 #if !CONFIG_IS_ENABLED(DM_MMC)
418 static const struct mmc_ops dmmc_ops = {
419        .send_cmd       = dmmc_send_cmd,
420        .set_ios        = dmmc_set_ios,
421        .init           = dmmc_init,
422 };
423 #else
424 
425 static int davinci_mmc_getcd(struct udevice *dev)
426 {
427 	int value = -1;
428 #if CONFIG_IS_ENABLED(DM_GPIO)
429 	struct davinci_mmc_priv *priv = dev_get_priv(dev);
430 	value = dm_gpio_get_value(&priv->cd_gpio);
431 #endif
432 	/* if no CD return as 1 */
433 	if (value < 0)
434 		return 1;
435 
436 	return value;
437 }
438 
439 static int davinci_mmc_getwp(struct udevice *dev)
440 {
441 	int value = -1;
442 #if CONFIG_IS_ENABLED(DM_GPIO)
443 	struct davinci_mmc_priv *priv = dev_get_priv(dev);
444 
445 	value = dm_gpio_get_value(&priv->wp_gpio);
446 #endif
447 	/* if no WP return as 0 */
448 	if (value < 0)
449 		return 0;
450 
451 	return value;
452 }
453 
454 static const struct dm_mmc_ops davinci_mmc_ops = {
455 	.send_cmd	= davinci_mmc_send_cmd,
456 	.set_ios	= davinci_mmc_set_ios,
457 	.get_cd		= davinci_mmc_getcd,
458 	.get_wp		= davinci_mmc_getwp,
459 };
460 #endif
461 
462 #if !CONFIG_IS_ENABLED(DM_MMC)
463 /* Called from board_mmc_init during startup. Can be called multiple times
464 * depending on the number of slots available on board and controller
465 */
466 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
467 {
468 	host->cfg.name = "davinci";
469 	host->cfg.ops = &dmmc_ops;
470 	host->cfg.f_min = 200000;
471 	host->cfg.f_max = 25000000;
472 	host->cfg.voltages = host->voltages;
473 	host->cfg.host_caps = host->host_caps;
474 
475 	host->cfg.b_max = DAVINCI_MAX_BLOCKS;
476 
477 	mmc_create(&host->cfg, host);
478 
479 	return 0;
480 }
481 #else
482 
483 
484 static int davinci_mmc_probe(struct udevice *dev)
485 {
486 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
487 	struct davinci_mmc_plat *plat = dev_get_platdata(dev);
488 	struct davinci_mmc_priv *priv = dev_get_priv(dev);
489  	struct mmc_config *cfg = &plat->cfg;
490 #ifdef CONFIG_SPL_BUILD
491 	int ret;
492 #endif
493 
494 	cfg->f_min = 200000;
495 	cfg->f_max = 25000000;
496 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
497 	cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
498 	cfg->b_max = DAVINCI_MAX_BLOCKS;
499 	cfg->name = "da830-mmc";
500 
501 	priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
502 	priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
503 
504 #if CONFIG_IS_ENABLED(DM_GPIO)
505 	/* These GPIOs are optional */
506 	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
507 	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
508 #endif
509 
510 	upriv->mmc = &plat->mmc;
511 
512 #ifdef CONFIG_SPL_BUILD
513 	/*
514 	 * FIXME This is a temporary workaround to enable the driver model in
515 	 * SPL on omapl138-lcdk. For some reason the bind() callback is not
516 	 * being called in SPL for MMC which breaks the mmc boot - the hack
517 	 * is to call mmc_bind() from probe(). We also don't have full DT
518 	 * support in SPL, hence the hard-coded base register address.
519 	 */
520 	priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
521 	ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
522 	if (ret)
523 		return ret;
524 #endif
525 
526 	return davinci_dm_mmc_init(dev);
527 }
528 
529 static int davinci_mmc_bind(struct udevice *dev)
530 {
531 	struct davinci_mmc_plat *plat = dev_get_platdata(dev);
532 
533 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
534 }
535 
536 static const struct udevice_id davinci_mmc_ids[] = {
537 	{ .compatible = "ti,da830-mmc" },
538 	{},
539 };
540 
541 U_BOOT_DRIVER(davinci_mmc_drv) = {
542 	.name = "davinci_mmc",
543 	.id		= UCLASS_MMC,
544 	.of_match	= davinci_mmc_ids,
545 #if CONFIG_BLK
546 	.bind		= davinci_mmc_bind,
547 #endif
548 	.probe = davinci_mmc_probe,
549 	.ops = &davinci_mmc_ops,
550 	.platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
551 	.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
552 };
553 #endif
554