1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <linux/compiler.h>
9 #include <fsl_errata.h>
10 #include <asm/processor.h>
11 #include <fsl_usb.h>
12 #include "fsl_corenet_serdes.h"
13
14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
15 /*
16 * This work-around is implemented in PBI, so just check to see if the
17 * work-around was actually applied. To do this, we check for specific data
18 * at specific addresses in DCSR.
19 *
20 * Array offsets[] contains a list of offsets within DCSR. According to the
21 * erratum document, the value at each offset should be 2.
22 */
check_erratum_a4849(uint32_t svr)23 static void check_erratum_a4849(uint32_t svr)
24 {
25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
26 unsigned int i;
27
28 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
29 static const uint8_t offsets[] = {
30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
31 };
32 #endif
33 #ifdef CONFIG_ARCH_P4080
34 static const uint8_t offsets[] = {
35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
36 };
37 #endif
38 uint32_t x108; /* The value that should be at offset 0x108 */
39
40 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
41 if (in_be32(dcsr + offsets[i]) != 2) {
42 printf("Work-around for Erratum A004849 is not enabled\n");
43 return;
44 }
45 }
46
47 #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041)
48 x108 = 0x12;
49 #endif
50
51 #ifdef CONFIG_ARCH_P4080
52 /*
53 * For P4080, the erratum document says that the value at offset 0x108
54 * should be 0x12 on rev2, or 0x1c on rev3.
55 */
56 if (SVR_MAJ(svr) == 2)
57 x108 = 0x12;
58 if (SVR_MAJ(svr) == 3)
59 x108 = 0x1c;
60 #endif
61
62 if (in_be32(dcsr + 0x108) != x108) {
63 printf("Work-around for Erratum A004849 is not enabled\n");
64 return;
65 }
66
67 /* Everything matches, so the erratum work-around was applied */
68
69 printf("Work-around for Erratum A004849 enabled\n");
70 }
71 #endif
72
73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
74 /*
75 * This work-around is implemented in PBI, so just check to see if the
76 * work-around was actually applied. To do this, we check for specific data
77 * at specific addresses in the SerDes register block.
78 *
79 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
81
82 */
check_erratum_a4580(uint32_t svr)83 static void check_erratum_a4580(uint32_t svr)
84 {
85 const serdes_corenet_t __iomem *srds_regs =
86 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
87 unsigned int lane;
88
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
90 if (serdes_lane_enabled(lane)) {
91 const struct serdes_lane __iomem *srds_lane =
92 &srds_regs->lane[serdes_get_lane_idx(lane)];
93
94 /*
95 * Verify that the values we were supposed to write in
96 * the PBI are actually there. Also, the lower 15
97 * bits of res4[3] should be the same as the upper 15
98 * bits of res4[1].
99 */
100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
101 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
103 printf("Work-around for Erratum A004580 is "
104 "not enabled\n");
105 return;
106 }
107 }
108 }
109
110 /* Everything matches, so the erratum work-around was applied */
111
112 printf("Work-around for Erratum A004580 enabled\n");
113 }
114 #endif
115
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
117 /*
118 * This workaround can be implemented in PBI, or by u-boot.
119 */
check_erratum_a007212(void)120 static void check_erratum_a007212(void)
121 {
122 u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
123
124 if (in_be32(plldgdcr) & 0x1fe) {
125 /* check if PLL ratio is set by workaround */
126 puts("Work-around for Erratum A007212 enabled\n");
127 }
128 }
129 #endif
130
do_errata(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])131 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
132 {
133 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
134 extern int enable_cpu_a011_workaround;
135 #endif
136 __maybe_unused u32 svr = get_svr();
137
138 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
139 if (IS_SVR_REV(svr, 1, 0)) {
140 switch (SVR_SOC_VER(svr)) {
141 case SVR_P1013:
142 case SVR_P1022:
143 puts("Work-around for Erratum SATA A001 enabled\n");
144 }
145 }
146 #endif
147
148 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
149 puts("Work-around for Erratum SERDES8 enabled\n");
150 #endif
151 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
152 puts("Work-around for Erratum SERDES9 enabled\n");
153 #endif
154 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
155 puts("Work-around for Erratum SERDES-A005 enabled\n");
156 #endif
157 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
158 if (SVR_MAJ(svr) < 3)
159 puts("Work-around for Erratum CPU22 enabled\n");
160 #endif
161 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
162 /*
163 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
164 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
165 * The SVR has been checked by cpu_init_r().
166 */
167 if (enable_cpu_a011_workaround)
168 puts("Work-around for Erratum CPU-A011 enabled\n");
169 #endif
170 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
171 puts("Work-around for Erratum CPU-A003999 enabled\n");
172 #endif
173 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
174 puts("Work-around for Erratum DDR-A003474 enabled\n");
175 #endif
176 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
177 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
178 #endif
179 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
180 puts("Work-around for Erratum ESDHC111 enabled\n");
181 #endif
182 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
183 puts("Work-around for Erratum A004468 enabled\n");
184 #endif
185 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
186 puts("Work-around for Erratum ESDHC135 enabled\n");
187 #endif
188 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
189 if (SVR_MAJ(svr) < 3)
190 puts("Work-around for Erratum ESDHC13 enabled\n");
191 #endif
192 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
193 puts("Work-around for Erratum ESDHC-A001 enabled\n");
194 #endif
195 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
196 puts("Work-around for Erratum CPC-A002 enabled\n");
197 #endif
198 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
199 puts("Work-around for Erratum CPC-A003 enabled\n");
200 #endif
201 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
202 puts("Work-around for Erratum ELBC-A001 enabled\n");
203 #endif
204 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
205 puts("Work-around for Erratum DDR-A003 enabled\n");
206 #endif
207 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
208 puts("Work-around for Erratum DDR115 enabled\n");
209 #endif
210 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
211 puts("Work-around for Erratum DDR111 enabled\n");
212 puts("Work-around for Erratum DDR134 enabled\n");
213 #endif
214 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
215 puts("Work-around for Erratum IFC-A002769 enabled\n");
216 #endif
217 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
218 puts("Work-around for Erratum P1010-A003549 enabled\n");
219 #endif
220 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
221 puts("Work-around for Erratum IFC A-003399 enabled\n");
222 #endif
223 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
224 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
225 puts("Work-around for Erratum NMG DDR120 enabled\n");
226 #endif
227 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
228 puts("Work-around for Erratum NMG_LBC103 enabled\n");
229 #endif
230 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
231 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
232 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
233 #endif
234 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
235 puts("Work-around for Erratum A004508 enabled\n");
236 #endif
237 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
238 puts("Work-around for Erratum A004510 enabled\n");
239 #endif
240 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
241 puts("Work-around for Erratum SRIO-A004034 enabled\n");
242 #endif
243 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
244 puts("Work-around for Erratum A004934 enabled\n");
245 #endif
246 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
247 if (IS_SVR_REV(svr, 1, 0))
248 puts("Work-around for Erratum A005871 enabled\n");
249 #endif
250 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475
251 if (SVR_MAJ(get_svr()) == 1)
252 puts("Work-around for Erratum A006475 enabled\n");
253 #endif
254 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384
255 if (SVR_MAJ(get_svr()) == 1)
256 puts("Work-around for Erratum A006384 enabled\n");
257 #endif
258 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
259 /* This work-around is implemented in PBI, so just check for it */
260 check_erratum_a4849(svr);
261 #endif
262 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
263 /* This work-around is implemented in PBI, so just check for it */
264 check_erratum_a4580(svr);
265 #endif
266 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
267 puts("Work-around for Erratum PCIe-A003 enabled\n");
268 #endif
269 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
270 puts("Work-around for Erratum USB14 enabled\n");
271 #endif
272 #ifdef CONFIG_SYS_FSL_ERRATUM_A007186
273 if (has_erratum_a007186())
274 puts("Work-around for Erratum A007186 enabled\n");
275 #endif
276 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
277 puts("Work-around for Erratum A006593 enabled\n");
278 #endif
279 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
280 if (has_erratum_a006379())
281 puts("Work-around for Erratum A006379 enabled\n");
282 #endif
283 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
284 if (IS_SVR_REV(svr, 1, 0))
285 puts("Work-around for Erratum A003571 enabled\n");
286 #endif
287 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
288 puts("Work-around for Erratum A-005812 enabled\n");
289 #endif
290 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
291 puts("Work-around for Erratum A005125 enabled\n");
292 #endif
293 #ifdef CONFIG_SYS_FSL_ERRATUM_A007075
294 if (has_erratum_a007075())
295 puts("Work-around for Erratum A007075 enabled\n");
296 #endif
297 #ifdef CONFIG_SYS_FSL_ERRATUM_A007798
298 if (has_erratum_a007798())
299 puts("Work-around for Erratum A007798 enabled\n");
300 #endif
301 #ifdef CONFIG_SYS_FSL_ERRATUM_A004477
302 if (has_erratum_a004477())
303 puts("Work-around for Erratum A004477 enabled\n");
304 #endif
305 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
306 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
307 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
308 puts("Work-around for Erratum I2C-A004447 enabled\n");
309 #endif
310 #ifdef CONFIG_SYS_FSL_ERRATUM_A005275
311 if (has_erratum_a005275())
312 puts("Work-around for Erratum A005275 enabled\n");
313 #endif
314 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
315 if (has_erratum_a006261())
316 puts("Work-around for Erratum A006261 enabled\n");
317 #endif
318 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
319 check_erratum_a007212();
320 #endif
321 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
322 puts("Work-around for Erratum A-005434 enabled\n");
323 #endif
324 #if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
325 defined(CONFIG_A008044_WORKAROUND)
326 if (IS_SVR_REV(svr, 1, 0))
327 puts("Work-around for Erratum A-008044 enabled\n");
328 #endif
329 #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && \
330 (defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS))
331 puts("Work-around for Erratum XFI on B4860QDS enabled\n");
332 #endif
333 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
334 puts("Work-around for Erratum A009663 enabled\n");
335 #endif
336 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
337 puts("Work-around for Erratum A007907 enabled\n");
338 #endif
339 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
340 puts("Work-around for Erratum A007815 enabled\n");
341 #endif
342
343 return 0;
344 }
345
346 U_BOOT_CMD(
347 errata, 1, 0, do_errata,
348 "Report errata workarounds",
349 ""
350 );
351