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Searched defs:fbits (Results 1 – 18 of 18) sorted by relevance

/external/cbor-java/src/main/java/co/nstant/in/cbor/encoder/
DHalfPrecisionFloatEncoder.java29 int fbits = Float.floatToIntBits(fval); in fromFloat() local
/external/vixl/src/aarch64/
Dlogic-aarch64.cc87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) { in FixedToFloat16()
153 int fbits, in UFixedToFloat16()
4949 int fbits) { in fcvts()
4977 int fbits) { in fcvtu()
5483 int fbits, in scvtf()
5505 int fbits, in ucvtf()
Dassembler-aarch64.cc3140 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
3159 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
3173 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
3191 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
3209 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf()
3228 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
3242 void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) { in ucvtf()
Dsimulator-aarch64.cc3244 int fbits = 64 - instr->GetFPScale(); in VisitFPFixedPointConvert() local
/external/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc41 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
51 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
66 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
76 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
3780 FPRounding rounding_mode, int fbits) { in fcvts()
3799 FPRounding rounding_mode, int fbits) { in fcvtu()
4215 const LogicVRegister& src, int fbits, in scvtf()
4231 const LogicVRegister& src, int fbits, in ucvtf()
Dsimulator-arm64.cc2814 int fbits = 64 - instr->FPScale(); in VisitFPFixedPointConvert() local
/external/v8/src/codegen/arm64/
Dassembler-arm64.cc2810 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
2820 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
2830 void Assembler::ucvtf(const VRegister& fd, const Register& rn, int fbits) { in ucvtf()
2951 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in fcvtzs()
2962 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
2972 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
2983 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
Dmacro-assembler-arm64-inl.h912 unsigned fbits) { in Scvtf()
992 unsigned fbits) { in Ucvtf()
/external/vixl/test/aarch64/
Dtest-assembler-fp-aarch64.cc4415 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtfHelper() local
4428 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
4443 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtfHelper() local
4451 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
4570 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
4583 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
4598 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
4606 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
Dtest-simulator-aarch64.cc1021 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper() local
1330 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS() local
1408 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedU() local
/external/python/cpython3/Objects/
Dfloatobject.c2171 unsigned int fbits; in _PyFloat_Pack4() local
/external/python/cpython2/Objects/
Dfloatobject.c2318 unsigned int fbits; in _PyFloat_Pack4() local
/external/skqp/third_party/skcms/
Dskcms.cc1380 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
/external/skia/third_party/skcms/
Dskcms.cc81 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
/external/vixl/src/aarch32/
Ddisasm-aarch32.cc4428 int32_t fbits) { in vcvt()
4439 int32_t fbits) { in vcvt()
4450 int32_t fbits) { in vcvt()
23878 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
23956 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24224 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24302 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
36096 uint32_t fbits = in DecodeT32() local
38262 uint32_t fbits = in DecodeT32() local
47736 uint32_t fbits = 64 - ((instr >> 16) & 0x3f); in DecodeA32() local
[all …]
Dmacro-assembler-aarch32.h6308 int32_t fbits) { in Vcvt()
6318 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in Vcvt()
6327 int32_t fbits) { in Vcvt()
6337 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in Vcvt()
6346 int32_t fbits) { in Vcvt()
6356 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in Vcvt()
Dassembler-aarch32.h4239 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt()
4250 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in vcvt()
4261 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in vcvt()
Dassembler-aarch32.cc16279 int32_t fbits) { in vcvt()
16383 int32_t fbits) { in vcvt()
16419 int32_t fbits) { in vcvt()