1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <env.h>
14 #include <malloc.h>
15 #include <memalign.h>
16 #include <miiphy.h>
17 #include <net.h>
18 #include <netdev.h>
19 #include <power/regulator.h>
20
21 #include <asm/io.h>
22 #include <linux/errno.h>
23 #include <linux/compiler.h>
24
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/mach-imx/sys_proto.h>
28 #include <asm-generic/gpio.h>
29
30 #include "fec_mxc.h"
31
32 DECLARE_GLOBAL_DATA_PTR;
33
34 /*
35 * Timeout the transfer after 5 mS. This is usually a bit more, since
36 * the code in the tightloops this timeout is used in adds some overhead.
37 */
38 #define FEC_XFER_TIMEOUT 5000
39
40 /*
41 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
42 * 64-byte alignment in the DMA RX FEC buffer.
43 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
44 * satisfies the alignment on other SoCs (32-bytes)
45 */
46 #define FEC_DMA_RX_MINALIGN 64
47
48 #ifndef CONFIG_MII
49 #error "CONFIG_MII has to be defined!"
50 #endif
51
52 #ifndef CONFIG_FEC_XCV_TYPE
53 #define CONFIG_FEC_XCV_TYPE MII100
54 #endif
55
56 /*
57 * The i.MX28 operates with packets in big endian. We need to swap them before
58 * sending and after receiving.
59 */
60 #ifdef CONFIG_MX28
61 #define CONFIG_FEC_MXC_SWAP_PACKET
62 #endif
63
64 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
65
66 /* Check various alignment issues at compile time */
67 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
68 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
69 #endif
70
71 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
72 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
73 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
74 #endif
75
76 #undef DEBUG
77
78 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet(uint32_t * packet,int length)79 static void swap_packet(uint32_t *packet, int length)
80 {
81 int i;
82
83 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
84 packet[i] = __swab32(packet[i]);
85 }
86 #endif
87
88 /* MII-interface related functions */
fec_mdio_read(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr)89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
90 uint8_t regaddr)
91 {
92 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
94 uint32_t start;
95 int val;
96
97 /*
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
100 */
101 writel(FEC_IEVENT_MII, ð->ievent);
102 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
104
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
106 phy | reg, ð->mii_data);
107
108 /* wait for the related interrupt */
109 start = get_timer(0);
110 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
113 return -1;
114 }
115 }
116
117 /* clear mii interrupt bit */
118 writel(FEC_IEVENT_MII, ð->ievent);
119
120 /* it's now safe to read the PHY's register */
121 val = (unsigned short)readl(ð->mii_data);
122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
123 regaddr, val);
124 return val;
125 }
126
127 #ifndef imx_get_fecclk
imx_get_fecclk(void)128 u32 __weak imx_get_fecclk(void)
129 {
130 return 0;
131 }
132 #endif
133
fec_get_clk_rate(void * udev,int idx)134 static int fec_get_clk_rate(void *udev, int idx)
135 {
136 struct fec_priv *fec;
137 struct udevice *dev;
138 int ret;
139
140 if (IS_ENABLED(CONFIG_IMX8) ||
141 CONFIG_IS_ENABLED(CLK_CCF)) {
142 dev = udev;
143 if (!dev) {
144 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
145 if (ret < 0) {
146 debug("Can't get FEC udev: %d\n", ret);
147 return ret;
148 }
149 }
150
151 fec = dev_get_priv(dev);
152 if (fec)
153 return fec->clk_rate;
154
155 return -EINVAL;
156 } else {
157 return imx_get_fecclk();
158 }
159 }
160
fec_mii_setspeed(struct ethernet_regs * eth)161 static void fec_mii_setspeed(struct ethernet_regs *eth)
162 {
163 /*
164 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
165 * and do not drop the Preamble.
166 *
167 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
168 * MII_SPEED) register that defines the MDIO output hold time. Earlier
169 * versions are RAZ there, so just ignore the difference and write the
170 * register always.
171 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
172 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
173 * output.
174 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
175 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
176 * holdtime cannot result in a value greater than 3.
177 */
178 u32 pclk;
179 u32 speed;
180 u32 hold;
181 int ret;
182
183 ret = fec_get_clk_rate(NULL, 0);
184 if (ret < 0) {
185 printf("Can't find FEC0 clk rate: %d\n", ret);
186 return;
187 }
188 pclk = ret;
189 speed = DIV_ROUND_UP(pclk, 5000000);
190 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
191
192 #ifdef FEC_QUIRK_ENET_MAC
193 speed--;
194 #endif
195 writel(speed << 1 | hold << 8, ð->mii_speed);
196 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
197 }
198
fec_mdio_write(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr,uint16_t data)199 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
200 uint8_t regaddr, uint16_t data)
201 {
202 uint32_t reg; /* convenient holder for the PHY register */
203 uint32_t phy; /* convenient holder for the PHY */
204 uint32_t start;
205
206 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
207 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
208
209 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
210 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
211
212 /* wait for the MII interrupt */
213 start = get_timer(0);
214 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
215 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
216 printf("Write MDIO failed...\n");
217 return -1;
218 }
219 }
220
221 /* clear MII interrupt bit */
222 writel(FEC_IEVENT_MII, ð->ievent);
223 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
224 regaddr, data);
225
226 return 0;
227 }
228
fec_phy_read(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr)229 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
230 int regaddr)
231 {
232 return fec_mdio_read(bus->priv, phyaddr, regaddr);
233 }
234
fec_phy_write(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr,u16 data)235 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
236 int regaddr, u16 data)
237 {
238 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
239 }
240
241 #ifndef CONFIG_PHYLIB
miiphy_restart_aneg(struct eth_device * dev)242 static int miiphy_restart_aneg(struct eth_device *dev)
243 {
244 int ret = 0;
245 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
246 struct fec_priv *fec = (struct fec_priv *)dev->priv;
247 struct ethernet_regs *eth = fec->bus->priv;
248
249 /*
250 * Wake up from sleep if necessary
251 * Reset PHY, then delay 300ns
252 */
253 #ifdef CONFIG_MX27
254 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
255 #endif
256 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
257 udelay(1000);
258
259 /* Set the auto-negotiation advertisement register bits */
260 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
261 LPA_100FULL | LPA_100HALF | LPA_10FULL |
262 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
263 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
264 BMCR_ANENABLE | BMCR_ANRESTART);
265
266 if (fec->mii_postcall)
267 ret = fec->mii_postcall(fec->phy_id);
268
269 #endif
270 return ret;
271 }
272
273 #ifndef CONFIG_FEC_FIXED_SPEED
miiphy_wait_aneg(struct eth_device * dev)274 static int miiphy_wait_aneg(struct eth_device *dev)
275 {
276 uint32_t start;
277 int status;
278 struct fec_priv *fec = (struct fec_priv *)dev->priv;
279 struct ethernet_regs *eth = fec->bus->priv;
280
281 /* Wait for AN completion */
282 start = get_timer(0);
283 do {
284 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
285 printf("%s: Autonegotiation timeout\n", dev->name);
286 return -1;
287 }
288
289 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
290 if (status < 0) {
291 printf("%s: Autonegotiation failed. status: %d\n",
292 dev->name, status);
293 return -1;
294 }
295 } while (!(status & BMSR_LSTATUS));
296
297 return 0;
298 }
299 #endif /* CONFIG_FEC_FIXED_SPEED */
300 #endif
301
fec_rx_task_enable(struct fec_priv * fec)302 static int fec_rx_task_enable(struct fec_priv *fec)
303 {
304 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
305 return 0;
306 }
307
fec_rx_task_disable(struct fec_priv * fec)308 static int fec_rx_task_disable(struct fec_priv *fec)
309 {
310 return 0;
311 }
312
fec_tx_task_enable(struct fec_priv * fec)313 static int fec_tx_task_enable(struct fec_priv *fec)
314 {
315 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
316 return 0;
317 }
318
fec_tx_task_disable(struct fec_priv * fec)319 static int fec_tx_task_disable(struct fec_priv *fec)
320 {
321 return 0;
322 }
323
324 /**
325 * Initialize receive task's buffer descriptors
326 * @param[in] fec all we know about the device yet
327 * @param[in] count receive buffer count to be allocated
328 * @param[in] dsize desired size of each receive buffer
329 * @return 0 on success
330 *
331 * Init all RX descriptors to default values.
332 */
fec_rbd_init(struct fec_priv * fec,int count,int dsize)333 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
334 {
335 uint32_t size;
336 ulong data;
337 int i;
338
339 /*
340 * Reload the RX descriptors with default values and wipe
341 * the RX buffers.
342 */
343 size = roundup(dsize, ARCH_DMA_MINALIGN);
344 for (i = 0; i < count; i++) {
345 data = fec->rbd_base[i].data_pointer;
346 memset((void *)data, 0, dsize);
347 flush_dcache_range(data, data + size);
348
349 fec->rbd_base[i].status = FEC_RBD_EMPTY;
350 fec->rbd_base[i].data_length = 0;
351 }
352
353 /* Mark the last RBD to close the ring. */
354 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
355 fec->rbd_index = 0;
356
357 flush_dcache_range((ulong)fec->rbd_base,
358 (ulong)fec->rbd_base + size);
359 }
360
361 /**
362 * Initialize transmit task's buffer descriptors
363 * @param[in] fec all we know about the device yet
364 *
365 * Transmit buffers are created externally. We only have to init the BDs here.\n
366 * Note: There is a race condition in the hardware. When only one BD is in
367 * use it must be marked with the WRAP bit to use it for every transmitt.
368 * This bit in combination with the READY bit results into double transmit
369 * of each data buffer. It seems the state machine checks READY earlier then
370 * resetting it after the first transfer.
371 * Using two BDs solves this issue.
372 */
fec_tbd_init(struct fec_priv * fec)373 static void fec_tbd_init(struct fec_priv *fec)
374 {
375 ulong addr = (ulong)fec->tbd_base;
376 unsigned size = roundup(2 * sizeof(struct fec_bd),
377 ARCH_DMA_MINALIGN);
378
379 memset(fec->tbd_base, 0, size);
380 fec->tbd_base[0].status = 0;
381 fec->tbd_base[1].status = FEC_TBD_WRAP;
382 fec->tbd_index = 0;
383 flush_dcache_range(addr, addr + size);
384 }
385
386 /**
387 * Mark the given read buffer descriptor as free
388 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
389 * @param[in] prbd buffer descriptor to mark free again
390 */
fec_rbd_clean(int last,struct fec_bd * prbd)391 static void fec_rbd_clean(int last, struct fec_bd *prbd)
392 {
393 unsigned short flags = FEC_RBD_EMPTY;
394 if (last)
395 flags |= FEC_RBD_WRAP;
396 writew(flags, &prbd->status);
397 writew(0, &prbd->data_length);
398 }
399
fec_get_hwaddr(int dev_id,unsigned char * mac)400 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
401 {
402 imx_get_mac_from_fuse(dev_id, mac);
403 return !is_valid_ethaddr(mac);
404 }
405
406 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(struct udevice * dev)407 static int fecmxc_set_hwaddr(struct udevice *dev)
408 #else
409 static int fec_set_hwaddr(struct eth_device *dev)
410 #endif
411 {
412 #ifdef CONFIG_DM_ETH
413 struct fec_priv *fec = dev_get_priv(dev);
414 struct eth_pdata *pdata = dev_get_platdata(dev);
415 uchar *mac = pdata->enetaddr;
416 #else
417 uchar *mac = dev->enetaddr;
418 struct fec_priv *fec = (struct fec_priv *)dev->priv;
419 #endif
420
421 writel(0, &fec->eth->iaddr1);
422 writel(0, &fec->eth->iaddr2);
423 writel(0, &fec->eth->gaddr1);
424 writel(0, &fec->eth->gaddr2);
425
426 /* Set physical address */
427 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
428 &fec->eth->paddr1);
429 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
430
431 return 0;
432 }
433
434 /* Do initial configuration of the FEC registers */
fec_reg_setup(struct fec_priv * fec)435 static void fec_reg_setup(struct fec_priv *fec)
436 {
437 uint32_t rcntrl;
438
439 /* Set interrupt mask register */
440 writel(0x00000000, &fec->eth->imask);
441
442 /* Clear FEC-Lite interrupt event register(IEVENT) */
443 writel(0xffffffff, &fec->eth->ievent);
444
445 /* Set FEC-Lite receive control register(R_CNTRL): */
446
447 /* Start with frame length = 1518, common for all modes. */
448 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
449 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
450 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
451 if (fec->xcv_type == RGMII)
452 rcntrl |= FEC_RCNTRL_RGMII;
453 else if (fec->xcv_type == RMII)
454 rcntrl |= FEC_RCNTRL_RMII;
455
456 writel(rcntrl, &fec->eth->r_cntrl);
457 }
458
459 /**
460 * Start the FEC engine
461 * @param[in] dev Our device to handle
462 */
463 #ifdef CONFIG_DM_ETH
fec_open(struct udevice * dev)464 static int fec_open(struct udevice *dev)
465 #else
466 static int fec_open(struct eth_device *edev)
467 #endif
468 {
469 #ifdef CONFIG_DM_ETH
470 struct fec_priv *fec = dev_get_priv(dev);
471 #else
472 struct fec_priv *fec = (struct fec_priv *)edev->priv;
473 #endif
474 int speed;
475 ulong addr, size;
476 int i;
477
478 debug("fec_open: fec_open(dev)\n");
479 /* full-duplex, heartbeat disabled */
480 writel(1 << 2, &fec->eth->x_cntrl);
481 fec->rbd_index = 0;
482
483 /* Invalidate all descriptors */
484 for (i = 0; i < FEC_RBD_NUM - 1; i++)
485 fec_rbd_clean(0, &fec->rbd_base[i]);
486 fec_rbd_clean(1, &fec->rbd_base[i]);
487
488 /* Flush the descriptors into RAM */
489 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
490 ARCH_DMA_MINALIGN);
491 addr = (ulong)fec->rbd_base;
492 flush_dcache_range(addr, addr + size);
493
494 #ifdef FEC_QUIRK_ENET_MAC
495 /* Enable ENET HW endian SWAP */
496 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
497 &fec->eth->ecntrl);
498 /* Enable ENET store and forward mode */
499 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
500 &fec->eth->x_wmrk);
501 #endif
502 /* Enable FEC-Lite controller */
503 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
504 &fec->eth->ecntrl);
505
506 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
507 udelay(100);
508
509 /* setup the MII gasket for RMII mode */
510 /* disable the gasket */
511 writew(0, &fec->eth->miigsk_enr);
512
513 /* wait for the gasket to be disabled */
514 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
515 udelay(2);
516
517 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
518 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
519
520 /* re-enable the gasket */
521 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
522
523 /* wait until MII gasket is ready */
524 int max_loops = 10;
525 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
526 if (--max_loops <= 0) {
527 printf("WAIT for MII Gasket ready timed out\n");
528 break;
529 }
530 }
531 #endif
532
533 #ifdef CONFIG_PHYLIB
534 {
535 /* Start up the PHY */
536 int ret = phy_startup(fec->phydev);
537
538 if (ret) {
539 printf("Could not initialize PHY %s\n",
540 fec->phydev->dev->name);
541 return ret;
542 }
543 speed = fec->phydev->speed;
544 }
545 #elif CONFIG_FEC_FIXED_SPEED
546 speed = CONFIG_FEC_FIXED_SPEED;
547 #else
548 miiphy_wait_aneg(edev);
549 speed = miiphy_speed(edev->name, fec->phy_id);
550 miiphy_duplex(edev->name, fec->phy_id);
551 #endif
552
553 #ifdef FEC_QUIRK_ENET_MAC
554 {
555 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
556 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
557 if (speed == _1000BASET)
558 ecr |= FEC_ECNTRL_SPEED;
559 else if (speed != _100BASET)
560 rcr |= FEC_RCNTRL_RMII_10T;
561 writel(ecr, &fec->eth->ecntrl);
562 writel(rcr, &fec->eth->r_cntrl);
563 }
564 #endif
565 debug("%s:Speed=%i\n", __func__, speed);
566
567 /* Enable SmartDMA receive task */
568 fec_rx_task_enable(fec);
569
570 udelay(100000);
571 return 0;
572 }
573
574 #ifdef CONFIG_DM_ETH
fecmxc_init(struct udevice * dev)575 static int fecmxc_init(struct udevice *dev)
576 #else
577 static int fec_init(struct eth_device *dev, bd_t *bd)
578 #endif
579 {
580 #ifdef CONFIG_DM_ETH
581 struct fec_priv *fec = dev_get_priv(dev);
582 #else
583 struct fec_priv *fec = (struct fec_priv *)dev->priv;
584 #endif
585 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
586 u8 *i;
587 ulong addr;
588
589 /* Initialize MAC address */
590 #ifdef CONFIG_DM_ETH
591 fecmxc_set_hwaddr(dev);
592 #else
593 fec_set_hwaddr(dev);
594 #endif
595
596 /* Setup transmit descriptors, there are two in total. */
597 fec_tbd_init(fec);
598
599 /* Setup receive descriptors. */
600 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
601
602 fec_reg_setup(fec);
603
604 if (fec->xcv_type != SEVENWIRE)
605 fec_mii_setspeed(fec->bus->priv);
606
607 /* Set Opcode/Pause Duration Register */
608 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
609 writel(0x2, &fec->eth->x_wmrk);
610
611 /* Set multicast address filter */
612 writel(0x00000000, &fec->eth->gaddr1);
613 writel(0x00000000, &fec->eth->gaddr2);
614
615 /* Do not access reserved register */
616 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
617 /* clear MIB RAM */
618 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
619 writel(0, i);
620
621 /* FIFO receive start register */
622 writel(0x520, &fec->eth->r_fstart);
623 }
624
625 /* size and address of each buffer */
626 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
627
628 addr = (ulong)fec->tbd_base;
629 writel((uint32_t)addr, &fec->eth->etdsr);
630
631 addr = (ulong)fec->rbd_base;
632 writel((uint32_t)addr, &fec->eth->erdsr);
633
634 #ifndef CONFIG_PHYLIB
635 if (fec->xcv_type != SEVENWIRE)
636 miiphy_restart_aneg(dev);
637 #endif
638 fec_open(dev);
639 return 0;
640 }
641
642 /**
643 * Halt the FEC engine
644 * @param[in] dev Our device to handle
645 */
646 #ifdef CONFIG_DM_ETH
fecmxc_halt(struct udevice * dev)647 static void fecmxc_halt(struct udevice *dev)
648 #else
649 static void fec_halt(struct eth_device *dev)
650 #endif
651 {
652 #ifdef CONFIG_DM_ETH
653 struct fec_priv *fec = dev_get_priv(dev);
654 #else
655 struct fec_priv *fec = (struct fec_priv *)dev->priv;
656 #endif
657 int counter = 0xffff;
658
659 /* issue graceful stop command to the FEC transmitter if necessary */
660 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
661 &fec->eth->x_cntrl);
662
663 debug("eth_halt: wait for stop regs\n");
664 /* wait for graceful stop to register */
665 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
666 udelay(1);
667
668 /* Disable SmartDMA tasks */
669 fec_tx_task_disable(fec);
670 fec_rx_task_disable(fec);
671
672 /*
673 * Disable the Ethernet Controller
674 * Note: this will also reset the BD index counter!
675 */
676 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
677 &fec->eth->ecntrl);
678 fec->rbd_index = 0;
679 fec->tbd_index = 0;
680 debug("eth_halt: done\n");
681 }
682
683 /**
684 * Transmit one frame
685 * @param[in] dev Our ethernet device to handle
686 * @param[in] packet Pointer to the data to be transmitted
687 * @param[in] length Data count in bytes
688 * @return 0 on success
689 */
690 #ifdef CONFIG_DM_ETH
fecmxc_send(struct udevice * dev,void * packet,int length)691 static int fecmxc_send(struct udevice *dev, void *packet, int length)
692 #else
693 static int fec_send(struct eth_device *dev, void *packet, int length)
694 #endif
695 {
696 unsigned int status;
697 u32 size;
698 ulong addr, end;
699 int timeout = FEC_XFER_TIMEOUT;
700 int ret = 0;
701
702 /*
703 * This routine transmits one frame. This routine only accepts
704 * 6-byte Ethernet addresses.
705 */
706 #ifdef CONFIG_DM_ETH
707 struct fec_priv *fec = dev_get_priv(dev);
708 #else
709 struct fec_priv *fec = (struct fec_priv *)dev->priv;
710 #endif
711
712 /*
713 * Check for valid length of data.
714 */
715 if ((length > 1500) || (length <= 0)) {
716 printf("Payload (%d) too large\n", length);
717 return -1;
718 }
719
720 /*
721 * Setup the transmit buffer. We are always using the first buffer for
722 * transmission, the second will be empty and only used to stop the DMA
723 * engine. We also flush the packet to RAM here to avoid cache trouble.
724 */
725 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
726 swap_packet((uint32_t *)packet, length);
727 #endif
728
729 addr = (ulong)packet;
730 end = roundup(addr + length, ARCH_DMA_MINALIGN);
731 addr &= ~(ARCH_DMA_MINALIGN - 1);
732 flush_dcache_range(addr, end);
733
734 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
735 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
736
737 /*
738 * update BD's status now
739 * This block:
740 * - is always the last in a chain (means no chain)
741 * - should transmitt the CRC
742 * - might be the last BD in the list, so the address counter should
743 * wrap (-> keep the WRAP flag)
744 */
745 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
746 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
747 writew(status, &fec->tbd_base[fec->tbd_index].status);
748
749 /*
750 * Flush data cache. This code flushes both TX descriptors to RAM.
751 * After this code, the descriptors will be safely in RAM and we
752 * can start DMA.
753 */
754 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
755 addr = (ulong)fec->tbd_base;
756 flush_dcache_range(addr, addr + size);
757
758 /*
759 * Below we read the DMA descriptor's last four bytes back from the
760 * DRAM. This is important in order to make sure that all WRITE
761 * operations on the bus that were triggered by previous cache FLUSH
762 * have completed.
763 *
764 * Otherwise, on MX28, it is possible to observe a corruption of the
765 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
766 * for the bus structure of MX28. The scenario is as follows:
767 *
768 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
769 * to DRAM due to flush_dcache_range()
770 * 2) ARM core writes the FEC registers via AHB_ARB2
771 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
772 *
773 * Note that 2) does sometimes finish before 1) due to reordering of
774 * WRITE accesses on the AHB bus, therefore triggering 3) before the
775 * DMA descriptor is fully written into DRAM. This results in occasional
776 * corruption of the DMA descriptor.
777 */
778 readl(addr + size - 4);
779
780 /* Enable SmartDMA transmit task */
781 fec_tx_task_enable(fec);
782
783 /*
784 * Wait until frame is sent. On each turn of the wait cycle, we must
785 * invalidate data cache to see what's really in RAM. Also, we need
786 * barrier here.
787 */
788 while (--timeout) {
789 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
790 break;
791 }
792
793 if (!timeout) {
794 ret = -EINVAL;
795 goto out;
796 }
797
798 /*
799 * The TDAR bit is cleared when the descriptors are all out from TX
800 * but on mx6solox we noticed that the READY bit is still not cleared
801 * right after TDAR.
802 * These are two distinct signals, and in IC simulation, we found that
803 * TDAR always gets cleared prior than the READY bit of last BD becomes
804 * cleared.
805 * In mx6solox, we use a later version of FEC IP. It looks like that
806 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
807 * version.
808 *
809 * Fix this by polling the READY bit of BD after the TDAR polling,
810 * which covers the mx6solox case and does not harm the other SoCs.
811 */
812 timeout = FEC_XFER_TIMEOUT;
813 while (--timeout) {
814 invalidate_dcache_range(addr, addr + size);
815 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
816 FEC_TBD_READY))
817 break;
818 }
819
820 if (!timeout)
821 ret = -EINVAL;
822
823 out:
824 debug("fec_send: status 0x%x index %d ret %i\n",
825 readw(&fec->tbd_base[fec->tbd_index].status),
826 fec->tbd_index, ret);
827 /* for next transmission use the other buffer */
828 if (fec->tbd_index)
829 fec->tbd_index = 0;
830 else
831 fec->tbd_index = 1;
832
833 return ret;
834 }
835
836 /**
837 * Pull one frame from the card
838 * @param[in] dev Our ethernet device to handle
839 * @return Length of packet read
840 */
841 #ifdef CONFIG_DM_ETH
fecmxc_recv(struct udevice * dev,int flags,uchar ** packetp)842 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
843 #else
844 static int fec_recv(struct eth_device *dev)
845 #endif
846 {
847 #ifdef CONFIG_DM_ETH
848 struct fec_priv *fec = dev_get_priv(dev);
849 #else
850 struct fec_priv *fec = (struct fec_priv *)dev->priv;
851 #endif
852 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
853 unsigned long ievent;
854 int frame_length, len = 0;
855 uint16_t bd_status;
856 ulong addr, size, end;
857 int i;
858
859 #ifdef CONFIG_DM_ETH
860 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
861 if (*packetp == 0) {
862 printf("%s: error allocating packetp\n", __func__);
863 return -ENOMEM;
864 }
865 #else
866 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
867 #endif
868
869 /* Check if any critical events have happened */
870 ievent = readl(&fec->eth->ievent);
871 writel(ievent, &fec->eth->ievent);
872 debug("fec_recv: ievent 0x%lx\n", ievent);
873 if (ievent & FEC_IEVENT_BABR) {
874 #ifdef CONFIG_DM_ETH
875 fecmxc_halt(dev);
876 fecmxc_init(dev);
877 #else
878 fec_halt(dev);
879 fec_init(dev, fec->bd);
880 #endif
881 printf("some error: 0x%08lx\n", ievent);
882 return 0;
883 }
884 if (ievent & FEC_IEVENT_HBERR) {
885 /* Heartbeat error */
886 writel(0x00000001 | readl(&fec->eth->x_cntrl),
887 &fec->eth->x_cntrl);
888 }
889 if (ievent & FEC_IEVENT_GRA) {
890 /* Graceful stop complete */
891 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
892 #ifdef CONFIG_DM_ETH
893 fecmxc_halt(dev);
894 #else
895 fec_halt(dev);
896 #endif
897 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
898 &fec->eth->x_cntrl);
899 #ifdef CONFIG_DM_ETH
900 fecmxc_init(dev);
901 #else
902 fec_init(dev, fec->bd);
903 #endif
904 }
905 }
906
907 /*
908 * Read the buffer status. Before the status can be read, the data cache
909 * must be invalidated, because the data in RAM might have been changed
910 * by DMA. The descriptors are properly aligned to cachelines so there's
911 * no need to worry they'd overlap.
912 *
913 * WARNING: By invalidating the descriptor here, we also invalidate
914 * the descriptors surrounding this one. Therefore we can NOT change the
915 * contents of this descriptor nor the surrounding ones. The problem is
916 * that in order to mark the descriptor as processed, we need to change
917 * the descriptor. The solution is to mark the whole cache line when all
918 * descriptors in the cache line are processed.
919 */
920 addr = (ulong)rbd;
921 addr &= ~(ARCH_DMA_MINALIGN - 1);
922 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
923 invalidate_dcache_range(addr, addr + size);
924
925 bd_status = readw(&rbd->status);
926 debug("fec_recv: status 0x%x\n", bd_status);
927
928 if (!(bd_status & FEC_RBD_EMPTY)) {
929 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
930 ((readw(&rbd->data_length) - 4) > 14)) {
931 /* Get buffer address and size */
932 addr = readl(&rbd->data_pointer);
933 frame_length = readw(&rbd->data_length) - 4;
934 /* Invalidate data cache over the buffer */
935 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
936 addr &= ~(ARCH_DMA_MINALIGN - 1);
937 invalidate_dcache_range(addr, end);
938
939 /* Fill the buffer and pass it to upper layers */
940 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
941 swap_packet((uint32_t *)addr, frame_length);
942 #endif
943
944 #ifdef CONFIG_DM_ETH
945 memcpy(*packetp, (char *)addr, frame_length);
946 #else
947 memcpy(buff, (char *)addr, frame_length);
948 net_process_received_packet(buff, frame_length);
949 #endif
950 len = frame_length;
951 } else {
952 if (bd_status & FEC_RBD_ERR)
953 debug("error frame: 0x%08lx 0x%08x\n",
954 addr, bd_status);
955 }
956
957 /*
958 * Free the current buffer, restart the engine and move forward
959 * to the next buffer. Here we check if the whole cacheline of
960 * descriptors was already processed and if so, we mark it free
961 * as whole.
962 */
963 size = RXDESC_PER_CACHELINE - 1;
964 if ((fec->rbd_index & size) == size) {
965 i = fec->rbd_index - size;
966 addr = (ulong)&fec->rbd_base[i];
967 for (; i <= fec->rbd_index ; i++) {
968 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
969 &fec->rbd_base[i]);
970 }
971 flush_dcache_range(addr,
972 addr + ARCH_DMA_MINALIGN);
973 }
974
975 fec_rx_task_enable(fec);
976 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
977 }
978 debug("fec_recv: stop\n");
979
980 return len;
981 }
982
fec_set_dev_name(char * dest,int dev_id)983 static void fec_set_dev_name(char *dest, int dev_id)
984 {
985 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
986 }
987
fec_alloc_descs(struct fec_priv * fec)988 static int fec_alloc_descs(struct fec_priv *fec)
989 {
990 unsigned int size;
991 int i;
992 uint8_t *data;
993 ulong addr;
994
995 /* Allocate TX descriptors. */
996 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
997 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
998 if (!fec->tbd_base)
999 goto err_tx;
1000
1001 /* Allocate RX descriptors. */
1002 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1003 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1004 if (!fec->rbd_base)
1005 goto err_rx;
1006
1007 memset(fec->rbd_base, 0, size);
1008
1009 /* Allocate RX buffers. */
1010
1011 /* Maximum RX buffer size. */
1012 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1013 for (i = 0; i < FEC_RBD_NUM; i++) {
1014 data = memalign(FEC_DMA_RX_MINALIGN, size);
1015 if (!data) {
1016 printf("%s: error allocating rxbuf %d\n", __func__, i);
1017 goto err_ring;
1018 }
1019
1020 memset(data, 0, size);
1021
1022 addr = (ulong)data;
1023 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1024 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1025 fec->rbd_base[i].data_length = 0;
1026 /* Flush the buffer to memory. */
1027 flush_dcache_range(addr, addr + size);
1028 }
1029
1030 /* Mark the last RBD to close the ring. */
1031 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1032
1033 fec->rbd_index = 0;
1034 fec->tbd_index = 0;
1035
1036 return 0;
1037
1038 err_ring:
1039 for (; i >= 0; i--) {
1040 addr = fec->rbd_base[i].data_pointer;
1041 free((void *)addr);
1042 }
1043 free(fec->rbd_base);
1044 err_rx:
1045 free(fec->tbd_base);
1046 err_tx:
1047 return -ENOMEM;
1048 }
1049
fec_free_descs(struct fec_priv * fec)1050 static void fec_free_descs(struct fec_priv *fec)
1051 {
1052 int i;
1053 ulong addr;
1054
1055 for (i = 0; i < FEC_RBD_NUM; i++) {
1056 addr = fec->rbd_base[i].data_pointer;
1057 free((void *)addr);
1058 }
1059 free(fec->rbd_base);
1060 free(fec->tbd_base);
1061 }
1062
fec_get_miibus(ulong base_addr,int dev_id)1063 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1064 {
1065 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1066 struct mii_dev *bus;
1067 int ret;
1068
1069 bus = mdio_alloc();
1070 if (!bus) {
1071 printf("mdio_alloc failed\n");
1072 return NULL;
1073 }
1074 bus->read = fec_phy_read;
1075 bus->write = fec_phy_write;
1076 bus->priv = eth;
1077 fec_set_dev_name(bus->name, dev_id);
1078
1079 ret = mdio_register(bus);
1080 if (ret) {
1081 printf("mdio_register failed\n");
1082 free(bus);
1083 return NULL;
1084 }
1085 fec_mii_setspeed(eth);
1086 return bus;
1087 }
1088
1089 #ifndef CONFIG_DM_ETH
1090 #ifdef CONFIG_PHYLIB
fec_probe(bd_t * bd,int dev_id,uint32_t base_addr,struct mii_dev * bus,struct phy_device * phydev)1091 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1092 struct mii_dev *bus, struct phy_device *phydev)
1093 #else
1094 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1095 struct mii_dev *bus, int phy_id)
1096 #endif
1097 {
1098 struct eth_device *edev;
1099 struct fec_priv *fec;
1100 unsigned char ethaddr[6];
1101 char mac[16];
1102 uint32_t start;
1103 int ret = 0;
1104
1105 /* create and fill edev struct */
1106 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1107 if (!edev) {
1108 puts("fec_mxc: not enough malloc memory for eth_device\n");
1109 ret = -ENOMEM;
1110 goto err1;
1111 }
1112
1113 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1114 if (!fec) {
1115 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1116 ret = -ENOMEM;
1117 goto err2;
1118 }
1119
1120 memset(edev, 0, sizeof(*edev));
1121 memset(fec, 0, sizeof(*fec));
1122
1123 ret = fec_alloc_descs(fec);
1124 if (ret)
1125 goto err3;
1126
1127 edev->priv = fec;
1128 edev->init = fec_init;
1129 edev->send = fec_send;
1130 edev->recv = fec_recv;
1131 edev->halt = fec_halt;
1132 edev->write_hwaddr = fec_set_hwaddr;
1133
1134 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1135 fec->bd = bd;
1136
1137 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1138
1139 /* Reset chip. */
1140 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1141 start = get_timer(0);
1142 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1143 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1144 printf("FEC MXC: Timeout resetting chip\n");
1145 goto err4;
1146 }
1147 udelay(10);
1148 }
1149
1150 fec_reg_setup(fec);
1151 fec_set_dev_name(edev->name, dev_id);
1152 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1153 fec->bus = bus;
1154 fec_mii_setspeed(bus->priv);
1155 #ifdef CONFIG_PHYLIB
1156 fec->phydev = phydev;
1157 phy_connect_dev(phydev, edev);
1158 /* Configure phy */
1159 phy_config(phydev);
1160 #else
1161 fec->phy_id = phy_id;
1162 #endif
1163 eth_register(edev);
1164 /* only support one eth device, the index number pointed by dev_id */
1165 edev->index = fec->dev_id;
1166
1167 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1168 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1169 memcpy(edev->enetaddr, ethaddr, 6);
1170 if (fec->dev_id)
1171 sprintf(mac, "eth%daddr", fec->dev_id);
1172 else
1173 strcpy(mac, "ethaddr");
1174 if (!env_get(mac))
1175 eth_env_set_enetaddr(mac, ethaddr);
1176 }
1177 return ret;
1178 err4:
1179 fec_free_descs(fec);
1180 err3:
1181 free(fec);
1182 err2:
1183 free(edev);
1184 err1:
1185 return ret;
1186 }
1187
fecmxc_initialize_multi(bd_t * bd,int dev_id,int phy_id,uint32_t addr)1188 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1189 {
1190 uint32_t base_mii;
1191 struct mii_dev *bus = NULL;
1192 #ifdef CONFIG_PHYLIB
1193 struct phy_device *phydev = NULL;
1194 #endif
1195 int ret;
1196
1197 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1198 /*
1199 * The i.MX28 has two ethernet interfaces, but they are not equal.
1200 * Only the first one can access the MDIO bus.
1201 */
1202 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1203 #else
1204 base_mii = addr;
1205 #endif
1206 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1207 bus = fec_get_miibus(base_mii, dev_id);
1208 if (!bus)
1209 return -ENOMEM;
1210 #ifdef CONFIG_PHYLIB
1211 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1212 if (!phydev) {
1213 mdio_unregister(bus);
1214 free(bus);
1215 return -ENOMEM;
1216 }
1217 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1218 #else
1219 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1220 #endif
1221 if (ret) {
1222 #ifdef CONFIG_PHYLIB
1223 free(phydev);
1224 #endif
1225 mdio_unregister(bus);
1226 free(bus);
1227 }
1228 return ret;
1229 }
1230
1231 #ifdef CONFIG_FEC_MXC_PHYADDR
fecmxc_initialize(bd_t * bd)1232 int fecmxc_initialize(bd_t *bd)
1233 {
1234 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1235 IMX_FEC_BASE);
1236 }
1237 #endif
1238
1239 #ifndef CONFIG_PHYLIB
fecmxc_register_mii_postcall(struct eth_device * dev,int (* cb)(int))1240 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1241 {
1242 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1243 fec->mii_postcall = cb;
1244 return 0;
1245 }
1246 #endif
1247
1248 #else
1249
fecmxc_read_rom_hwaddr(struct udevice * dev)1250 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1251 {
1252 struct fec_priv *priv = dev_get_priv(dev);
1253 struct eth_pdata *pdata = dev_get_platdata(dev);
1254
1255 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1256 }
1257
fecmxc_free_pkt(struct udevice * dev,uchar * packet,int length)1258 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1259 {
1260 if (packet)
1261 free(packet);
1262
1263 return 0;
1264 }
1265
1266 static const struct eth_ops fecmxc_ops = {
1267 .start = fecmxc_init,
1268 .send = fecmxc_send,
1269 .recv = fecmxc_recv,
1270 .free_pkt = fecmxc_free_pkt,
1271 .stop = fecmxc_halt,
1272 .write_hwaddr = fecmxc_set_hwaddr,
1273 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1274 };
1275
device_get_phy_addr(struct udevice * dev)1276 static int device_get_phy_addr(struct udevice *dev)
1277 {
1278 struct ofnode_phandle_args phandle_args;
1279 int reg;
1280
1281 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1282 &phandle_args)) {
1283 debug("Failed to find phy-handle");
1284 return -ENODEV;
1285 }
1286
1287 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1288
1289 return reg;
1290 }
1291
fec_phy_init(struct fec_priv * priv,struct udevice * dev)1292 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1293 {
1294 struct phy_device *phydev;
1295 int addr;
1296
1297 addr = device_get_phy_addr(dev);
1298 #ifdef CONFIG_FEC_MXC_PHYADDR
1299 addr = CONFIG_FEC_MXC_PHYADDR;
1300 #endif
1301
1302 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1303 if (!phydev)
1304 return -ENODEV;
1305
1306 priv->phydev = phydev;
1307 phy_config(phydev);
1308
1309 return 0;
1310 }
1311
1312 #ifdef CONFIG_DM_GPIO
1313 /* FEC GPIO reset */
fec_gpio_reset(struct fec_priv * priv)1314 static void fec_gpio_reset(struct fec_priv *priv)
1315 {
1316 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1317 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1318 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1319 mdelay(priv->reset_delay);
1320 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1321 if (priv->reset_post_delay)
1322 mdelay(priv->reset_post_delay);
1323 }
1324 }
1325 #endif
1326
fecmxc_probe(struct udevice * dev)1327 static int fecmxc_probe(struct udevice *dev)
1328 {
1329 struct eth_pdata *pdata = dev_get_platdata(dev);
1330 struct fec_priv *priv = dev_get_priv(dev);
1331 struct mii_dev *bus = NULL;
1332 uint32_t start;
1333 int ret;
1334
1335 if (IS_ENABLED(CONFIG_IMX8)) {
1336 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1337 if (ret < 0) {
1338 debug("Can't get FEC ipg clk: %d\n", ret);
1339 return ret;
1340 }
1341 ret = clk_enable(&priv->ipg_clk);
1342 if (ret < 0) {
1343 debug("Can't enable FEC ipg clk: %d\n", ret);
1344 return ret;
1345 }
1346
1347 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1348 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1349 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1350 if (ret < 0) {
1351 debug("Can't get FEC ipg clk: %d\n", ret);
1352 return ret;
1353 }
1354 ret = clk_enable(&priv->ipg_clk);
1355 if(ret)
1356 return ret;
1357
1358 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1359 if (ret < 0) {
1360 debug("Can't get FEC ahb clk: %d\n", ret);
1361 return ret;
1362 }
1363 ret = clk_enable(&priv->ahb_clk);
1364 if (ret)
1365 return ret;
1366
1367 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1368 if (!ret) {
1369 ret = clk_enable(&priv->clk_enet_out);
1370 if (ret)
1371 return ret;
1372 }
1373
1374 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1375 if (!ret) {
1376 ret = clk_enable(&priv->clk_ref);
1377 if (ret)
1378 return ret;
1379 }
1380
1381 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1382 if (!ret) {
1383 ret = clk_enable(&priv->clk_ptp);
1384 if (ret)
1385 return ret;
1386 }
1387
1388 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1389 }
1390
1391 ret = fec_alloc_descs(priv);
1392 if (ret)
1393 return ret;
1394
1395 #ifdef CONFIG_DM_REGULATOR
1396 if (priv->phy_supply) {
1397 ret = regulator_set_enable(priv->phy_supply, true);
1398 if (ret) {
1399 printf("%s: Error enabling phy supply\n", dev->name);
1400 return ret;
1401 }
1402 }
1403 #endif
1404
1405 #ifdef CONFIG_DM_GPIO
1406 fec_gpio_reset(priv);
1407 #endif
1408 /* Reset chip. */
1409 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1410 &priv->eth->ecntrl);
1411 start = get_timer(0);
1412 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1413 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1414 printf("FEC MXC: Timeout reseting chip\n");
1415 goto err_timeout;
1416 }
1417 udelay(10);
1418 }
1419
1420 fec_reg_setup(priv);
1421
1422 priv->dev_id = dev->seq;
1423 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1424 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1425 #else
1426 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1427 #endif
1428 if (!bus) {
1429 ret = -ENOMEM;
1430 goto err_mii;
1431 }
1432
1433 priv->bus = bus;
1434 priv->interface = pdata->phy_interface;
1435 switch (priv->interface) {
1436 case PHY_INTERFACE_MODE_MII:
1437 priv->xcv_type = MII100;
1438 break;
1439 case PHY_INTERFACE_MODE_RMII:
1440 priv->xcv_type = RMII;
1441 break;
1442 case PHY_INTERFACE_MODE_RGMII:
1443 case PHY_INTERFACE_MODE_RGMII_ID:
1444 case PHY_INTERFACE_MODE_RGMII_RXID:
1445 case PHY_INTERFACE_MODE_RGMII_TXID:
1446 priv->xcv_type = RGMII;
1447 break;
1448 default:
1449 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1450 printf("Unsupported interface type %d defaulting to %d\n",
1451 priv->interface, priv->xcv_type);
1452 break;
1453 }
1454
1455 ret = fec_phy_init(priv, dev);
1456 if (ret)
1457 goto err_phy;
1458
1459 return 0;
1460
1461 err_phy:
1462 mdio_unregister(bus);
1463 free(bus);
1464 err_mii:
1465 err_timeout:
1466 fec_free_descs(priv);
1467 return ret;
1468 }
1469
fecmxc_remove(struct udevice * dev)1470 static int fecmxc_remove(struct udevice *dev)
1471 {
1472 struct fec_priv *priv = dev_get_priv(dev);
1473
1474 free(priv->phydev);
1475 fec_free_descs(priv);
1476 mdio_unregister(priv->bus);
1477 mdio_free(priv->bus);
1478
1479 #ifdef CONFIG_DM_REGULATOR
1480 if (priv->phy_supply)
1481 regulator_set_enable(priv->phy_supply, false);
1482 #endif
1483
1484 return 0;
1485 }
1486
fecmxc_ofdata_to_platdata(struct udevice * dev)1487 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1488 {
1489 int ret = 0;
1490 struct eth_pdata *pdata = dev_get_platdata(dev);
1491 struct fec_priv *priv = dev_get_priv(dev);
1492 const char *phy_mode;
1493
1494 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1495 priv->eth = (struct ethernet_regs *)pdata->iobase;
1496
1497 pdata->phy_interface = -1;
1498 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1499 NULL);
1500 if (phy_mode)
1501 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1502 if (pdata->phy_interface == -1) {
1503 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1504 return -EINVAL;
1505 }
1506
1507 #ifdef CONFIG_DM_REGULATOR
1508 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1509 #endif
1510
1511 #ifdef CONFIG_DM_GPIO
1512 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1513 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1514 if (ret < 0)
1515 return 0; /* property is optional, don't return error! */
1516
1517 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1518 if (priv->reset_delay > 1000) {
1519 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1520 /* property value wrong, use default value */
1521 priv->reset_delay = 1;
1522 }
1523
1524 priv->reset_post_delay = dev_read_u32_default(dev,
1525 "phy-reset-post-delay",
1526 0);
1527 if (priv->reset_post_delay > 1000) {
1528 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1529 /* property value wrong, use default value */
1530 priv->reset_post_delay = 0;
1531 }
1532 #endif
1533
1534 return 0;
1535 }
1536
1537 static const struct udevice_id fecmxc_ids[] = {
1538 { .compatible = "fsl,imx28-fec" },
1539 { .compatible = "fsl,imx6q-fec" },
1540 { .compatible = "fsl,imx6sl-fec" },
1541 { .compatible = "fsl,imx6sx-fec" },
1542 { .compatible = "fsl,imx6ul-fec" },
1543 { .compatible = "fsl,imx53-fec" },
1544 { .compatible = "fsl,imx7d-fec" },
1545 { .compatible = "fsl,mvf600-fec" },
1546 { }
1547 };
1548
1549 U_BOOT_DRIVER(fecmxc_gem) = {
1550 .name = "fecmxc",
1551 .id = UCLASS_ETH,
1552 .of_match = fecmxc_ids,
1553 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1554 .probe = fecmxc_probe,
1555 .remove = fecmxc_remove,
1556 .ops = &fecmxc_ops,
1557 .priv_auto_alloc_size = sizeof(struct fec_priv),
1558 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1559 };
1560 #endif
1561