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1 /*
2  * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <common/debug.h>
10 #include <drivers/arm/cci.h>
11 #include <drivers/arm/ccn.h>
12 #include <drivers/arm/gicv2.h>
13 #include <drivers/arm/sp804_delay_timer.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <lib/mmio.h>
16 #include <lib/xlat_tables/xlat_tables_compat.h>
17 #include <plat/arm/common/arm_config.h>
18 #include <plat/arm/common/plat_arm.h>
19 #include <plat/common/platform.h>
20 #include <platform_def.h>
21 #include <services/spm_mm_partition.h>
22 
23 #include "fvp_private.h"
24 
25 /* Defines for GIC Driver build time selection */
26 #define FVP_GICV2		1
27 #define FVP_GICV3		2
28 
29 /*******************************************************************************
30  * arm_config holds the characteristics of the differences between the three FVP
31  * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
32  * at each boot stage by the primary before enabling the MMU (to allow
33  * interconnect configuration) & used thereafter. Each BL will have its own copy
34  * to allow independent operation.
35  ******************************************************************************/
36 arm_config_t arm_config;
37 
38 #define MAP_DEVICE0	MAP_REGION_FLAT(DEVICE0_BASE,			\
39 					DEVICE0_SIZE,			\
40 					MT_DEVICE | MT_RW | MT_SECURE)
41 
42 #define MAP_DEVICE1	MAP_REGION_FLAT(DEVICE1_BASE,			\
43 					DEVICE1_SIZE,			\
44 					MT_DEVICE | MT_RW | MT_SECURE)
45 
46 /*
47  * Need to be mapped with write permissions in order to set a new non-volatile
48  * counter value.
49  */
50 #define MAP_DEVICE2	MAP_REGION_FLAT(DEVICE2_BASE,			\
51 					DEVICE2_SIZE,			\
52 					MT_DEVICE | MT_RW | MT_SECURE)
53 
54 /*
55  * Table of memory regions for various BL stages to map using the MMU.
56  * This doesn't include Trusted SRAM as setup_page_tables() already takes care
57  * of mapping it.
58  *
59  * The flash needs to be mapped as writable in order to erase the FIP's Table of
60  * Contents in case of unrecoverable error (see plat_error_handler()).
61  */
62 #ifdef IMAGE_BL1
63 const mmap_region_t plat_arm_mmap[] = {
64 	ARM_MAP_SHARED_RAM,
65 	V2M_MAP_FLASH0_RW,
66 	V2M_MAP_IOFPGA,
67 	MAP_DEVICE0,
68 	MAP_DEVICE1,
69 #if TRUSTED_BOARD_BOOT
70 	/* To access the Root of Trust Public Key registers. */
71 	MAP_DEVICE2,
72 	/* Map DRAM to authenticate NS_BL2U image. */
73 	ARM_MAP_NS_DRAM1,
74 #endif
75 	{0}
76 };
77 #endif
78 #ifdef IMAGE_BL2
79 const mmap_region_t plat_arm_mmap[] = {
80 	ARM_MAP_SHARED_RAM,
81 	V2M_MAP_FLASH0_RW,
82 	V2M_MAP_IOFPGA,
83 	MAP_DEVICE0,
84 	MAP_DEVICE1,
85 	ARM_MAP_NS_DRAM1,
86 #ifdef __aarch64__
87 	ARM_MAP_DRAM2,
88 #endif
89 #ifdef SPD_tspd
90 	ARM_MAP_TSP_SEC_MEM,
91 #endif
92 #if TRUSTED_BOARD_BOOT
93 	/* To access the Root of Trust Public Key registers. */
94 	MAP_DEVICE2,
95 #if !BL2_AT_EL3
96 	ARM_MAP_BL1_RW,
97 #endif
98 #endif /* TRUSTED_BOARD_BOOT */
99 #if SPM_MM
100 	ARM_SP_IMAGE_MMAP,
101 #endif
102 #if ARM_BL31_IN_DRAM
103 	ARM_MAP_BL31_SEC_DRAM,
104 #endif
105 #ifdef SPD_opteed
106 	ARM_MAP_OPTEE_CORE_MEM,
107 	ARM_OPTEE_PAGEABLE_LOAD_MEM,
108 #endif
109 	{0}
110 };
111 #endif
112 #ifdef IMAGE_BL2U
113 const mmap_region_t plat_arm_mmap[] = {
114 	MAP_DEVICE0,
115 	V2M_MAP_IOFPGA,
116 	{0}
117 };
118 #endif
119 #ifdef IMAGE_BL31
120 const mmap_region_t plat_arm_mmap[] = {
121 	ARM_MAP_SHARED_RAM,
122 #if USE_DEBUGFS
123 	/* Required by devfip, can be removed if devfip is not used */
124 	V2M_MAP_FLASH0_RW,
125 #endif /* USE_DEBUGFS */
126 	ARM_MAP_EL3_TZC_DRAM,
127 	V2M_MAP_IOFPGA,
128 	MAP_DEVICE0,
129 	MAP_DEVICE1,
130 	ARM_V2M_MAP_MEM_PROTECT,
131 #if SPM_MM
132 	ARM_SPM_BUF_EL3_MMAP,
133 #endif
134 	{0}
135 };
136 
137 #if defined(IMAGE_BL31) && SPM_MM
138 const mmap_region_t plat_arm_secure_partition_mmap[] = {
139 	V2M_MAP_IOFPGA_EL0, /* for the UART */
140 	MAP_REGION_FLAT(DEVICE0_BASE,				\
141 			DEVICE0_SIZE,				\
142 			MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
143 	ARM_SP_IMAGE_MMAP,
144 	ARM_SP_IMAGE_NS_BUF_MMAP,
145 	ARM_SP_IMAGE_RW_MMAP,
146 	ARM_SPM_BUF_EL0_MMAP,
147 	{0}
148 };
149 #endif
150 #endif
151 #ifdef IMAGE_BL32
152 const mmap_region_t plat_arm_mmap[] = {
153 #ifndef __aarch64__
154 	ARM_MAP_SHARED_RAM,
155 	ARM_V2M_MAP_MEM_PROTECT,
156 #endif
157 	V2M_MAP_IOFPGA,
158 	MAP_DEVICE0,
159 	MAP_DEVICE1,
160 	{0}
161 };
162 #endif
163 
164 ARM_CASSERT_MMAP
165 
166 #if FVP_INTERCONNECT_DRIVER != FVP_CCN
167 static const int fvp_cci400_map[] = {
168 	PLAT_FVP_CCI400_CLUS0_SL_PORT,
169 	PLAT_FVP_CCI400_CLUS1_SL_PORT,
170 };
171 
172 static const int fvp_cci5xx_map[] = {
173 	PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
174 	PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
175 };
176 
get_interconnect_master(void)177 static unsigned int get_interconnect_master(void)
178 {
179 	unsigned int master;
180 	u_register_t mpidr;
181 
182 	mpidr = read_mpidr_el1();
183 	master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
184 		MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
185 
186 	assert(master < FVP_CLUSTER_COUNT);
187 	return master;
188 }
189 #endif
190 
191 #if defined(IMAGE_BL31) && SPM_MM
192 /*
193  * Boot information passed to a secure partition during initialisation. Linear
194  * indices in MP information will be filled at runtime.
195  */
196 static spm_mm_mp_info_t sp_mp_info[] = {
197 	[0] = {0x80000000, 0},
198 	[1] = {0x80000001, 0},
199 	[2] = {0x80000002, 0},
200 	[3] = {0x80000003, 0},
201 	[4] = {0x80000100, 0},
202 	[5] = {0x80000101, 0},
203 	[6] = {0x80000102, 0},
204 	[7] = {0x80000103, 0},
205 };
206 
207 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
208 	.h.type              = PARAM_SP_IMAGE_BOOT_INFO,
209 	.h.version           = VERSION_1,
210 	.h.size              = sizeof(spm_mm_boot_info_t),
211 	.h.attr              = 0,
212 	.sp_mem_base         = ARM_SP_IMAGE_BASE,
213 	.sp_mem_limit        = ARM_SP_IMAGE_LIMIT,
214 	.sp_image_base       = ARM_SP_IMAGE_BASE,
215 	.sp_stack_base       = PLAT_SP_IMAGE_STACK_BASE,
216 	.sp_heap_base        = ARM_SP_IMAGE_HEAP_BASE,
217 	.sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
218 	.sp_shared_buf_base  = PLAT_SPM_BUF_BASE,
219 	.sp_image_size       = ARM_SP_IMAGE_SIZE,
220 	.sp_pcpu_stack_size  = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
221 	.sp_heap_size        = ARM_SP_IMAGE_HEAP_SIZE,
222 	.sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
223 	.sp_shared_buf_size  = PLAT_SPM_BUF_SIZE,
224 	.num_sp_mem_regions  = ARM_SP_IMAGE_NUM_MEM_REGIONS,
225 	.num_cpus            = PLATFORM_CORE_COUNT,
226 	.mp_info             = &sp_mp_info[0],
227 };
228 
plat_get_secure_partition_mmap(void * cookie)229 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
230 {
231 	return plat_arm_secure_partition_mmap;
232 }
233 
plat_get_secure_partition_boot_info(void * cookie)234 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
235 		void *cookie)
236 {
237 	return &plat_arm_secure_partition_boot_info;
238 }
239 #endif
240 
241 /*******************************************************************************
242  * A single boot loader stack is expected to work on both the Foundation FVP
243  * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
244  * SYS_ID register provides a mechanism for detecting the differences between
245  * these platforms. This information is stored in a per-BL array to allow the
246  * code to take the correct path.Per BL platform configuration.
247  ******************************************************************************/
fvp_config_setup(void)248 void __init fvp_config_setup(void)
249 {
250 	unsigned int rev, hbi, bld, arch, sys_id;
251 
252 	sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
253 	rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
254 	hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
255 	bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
256 	arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
257 
258 	if (arch != ARCH_MODEL) {
259 		ERROR("This firmware is for FVP models\n");
260 		panic();
261 	}
262 
263 	/*
264 	 * The build field in the SYS_ID tells which variant of the GIC
265 	 * memory is implemented by the model.
266 	 */
267 	switch (bld) {
268 	case BLD_GIC_VE_MMAP:
269 		ERROR("Legacy Versatile Express memory map for GIC peripheral"
270 				" is not supported\n");
271 		panic();
272 		break;
273 	case BLD_GIC_A53A57_MMAP:
274 		break;
275 	default:
276 		ERROR("Unsupported board build %x\n", bld);
277 		panic();
278 	}
279 
280 	/*
281 	 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
282 	 * for the Foundation FVP.
283 	 */
284 	switch (hbi) {
285 	case HBI_FOUNDATION_FVP:
286 		arm_config.flags = 0;
287 
288 		/*
289 		 * Check for supported revisions of Foundation FVP
290 		 * Allow future revisions to run but emit warning diagnostic
291 		 */
292 		switch (rev) {
293 		case REV_FOUNDATION_FVP_V2_0:
294 		case REV_FOUNDATION_FVP_V2_1:
295 		case REV_FOUNDATION_FVP_v9_1:
296 		case REV_FOUNDATION_FVP_v9_6:
297 			break;
298 		default:
299 			WARN("Unrecognized Foundation FVP revision %x\n", rev);
300 			break;
301 		}
302 		break;
303 	case HBI_BASE_FVP:
304 		arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
305 
306 		/*
307 		 * Check for supported revisions
308 		 * Allow future revisions to run but emit warning diagnostic
309 		 */
310 		switch (rev) {
311 		case REV_BASE_FVP_V0:
312 			arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
313 			break;
314 		case REV_BASE_FVP_REVC:
315 			arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
316 					ARM_CONFIG_FVP_HAS_CCI5XX);
317 			break;
318 		default:
319 			WARN("Unrecognized Base FVP revision %x\n", rev);
320 			break;
321 		}
322 		break;
323 	default:
324 		ERROR("Unsupported board HBI number 0x%x\n", hbi);
325 		panic();
326 	}
327 
328 	/*
329 	 * We assume that the presence of MT bit, and therefore shifted
330 	 * affinities, is uniform across the platform: either all CPUs, or no
331 	 * CPUs implement it.
332 	 */
333 	if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
334 		arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
335 }
336 
337 
fvp_interconnect_init(void)338 void __init fvp_interconnect_init(void)
339 {
340 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
341 	if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
342 		ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
343 		panic();
344 	}
345 
346 	plat_arm_interconnect_init();
347 #else
348 	uintptr_t cci_base = 0U;
349 	const int *cci_map = NULL;
350 	unsigned int map_size = 0U;
351 
352 	/* Initialize the right interconnect */
353 	if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
354 		cci_base = PLAT_FVP_CCI5XX_BASE;
355 		cci_map = fvp_cci5xx_map;
356 		map_size = ARRAY_SIZE(fvp_cci5xx_map);
357 	} else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
358 		cci_base = PLAT_FVP_CCI400_BASE;
359 		cci_map = fvp_cci400_map;
360 		map_size = ARRAY_SIZE(fvp_cci400_map);
361 	} else {
362 		return;
363 	}
364 
365 	assert(cci_base != 0U);
366 	assert(cci_map != NULL);
367 	cci_init(cci_base, cci_map, map_size);
368 #endif
369 }
370 
fvp_interconnect_enable(void)371 void fvp_interconnect_enable(void)
372 {
373 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
374 	plat_arm_interconnect_enter_coherency();
375 #else
376 	unsigned int master;
377 
378 	if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
379 				 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
380 		master = get_interconnect_master();
381 		cci_enable_snoop_dvm_reqs(master);
382 	}
383 #endif
384 }
385 
fvp_interconnect_disable(void)386 void fvp_interconnect_disable(void)
387 {
388 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
389 	plat_arm_interconnect_exit_coherency();
390 #else
391 	unsigned int master;
392 
393 	if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
394 				 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
395 		master = get_interconnect_master();
396 		cci_disable_snoop_dvm_reqs(master);
397 	}
398 #endif
399 }
400 
401 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)402 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
403 {
404 	assert(heap_addr != NULL);
405 	assert(heap_size != NULL);
406 
407 	return arm_get_mbedtls_heap(heap_addr, heap_size);
408 }
409 #endif
410 
fvp_timer_init(void)411 void fvp_timer_init(void)
412 {
413 #if FVP_USE_SP804_TIMER
414 	/* Enable the clock override for SP804 timer 0, which means that no
415 	 * clock dividers are applied and the raw (35MHz) clock will be used.
416 	 */
417 	mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
418 
419 	/* Initialize delay timer driver using SP804 dual timer 0 */
420 	sp804_timer_init(V2M_SP804_TIMER0_BASE,
421 			SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
422 #else
423 	generic_delay_timer_init();
424 
425 	/* Enable System level generic timer */
426 	mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
427 			CNTCR_FCREQ(0U) | CNTCR_EN);
428 #endif /* FVP_USE_SP804_TIMER */
429 }
430