| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 169 X86InstructionSelector::getRegClass(LLT Ty, const RegisterBank &RB) const { in getRegClass() function in X86InstructionSelector
197 X86InstructionSelector::getRegClass(LLT Ty, unsigned Reg, in getRegClass() function in X86InstructionSelector
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 439 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass() function
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 742 const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF, in getRegClass() function in MIRParserImpl
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 417 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass() function
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 574 const TargetRegisterClass *getRegClass(unsigned Reg) const { in getRegClass() function
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 649 const TargetRegisterClass *getRegClass(unsigned i) const { in getRegClass() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 627 const TargetRegisterClass *getRegClass(unsigned Reg) const { in getRegClass() function
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| D | TargetRegisterInfo.h | 689 const TargetRegisterClass *getRegClass(unsigned i) const { in getRegClass() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 871 const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF, in getRegClass() function in MIRParserImpl
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 45 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceOperand.h | 793 RegClass getRegClass() const { return RegisterClass; } in getRegClass() function
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1063 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { in getRegClass() function in CodeGenRegBank
|
| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1252 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { in getRegClass() function in CodeGenRegBank
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 741 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1885 auto getRegClass = [&MRI,&HRI] (HexagonBlockRanges::RegisterRef R) in optimizeSpillSlots() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3079 auto getRegClass = [&](unsigned Reg) { in foldMemoryOperandImpl() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1562 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass() function
|