1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019 DENX Software Engineering
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6 #ifndef __MACH_IMX_CLK_H
7 #define __MACH_IMX_CLK_H
8
9 #include <linux/clk-provider.h>
10
11 enum imx_pllv3_type {
12 IMX_PLLV3_GENERIC,
13 IMX_PLLV3_SYS,
14 IMX_PLLV3_USB,
15 IMX_PLLV3_USB_VF610,
16 IMX_PLLV3_AV,
17 IMX_PLLV3_ENET,
18 IMX_PLLV3_ENET_IMX7,
19 IMX_PLLV3_SYS_VF610,
20 IMX_PLLV3_DDR_IMX7,
21 };
22
23 enum imx_pll14xx_type {
24 PLL_1416X,
25 PLL_1443X,
26 };
27
28 /* NOTE: Rate table should be kept sorted in descending order. */
29 struct imx_pll14xx_rate_table {
30 unsigned int rate;
31 unsigned int pdiv;
32 unsigned int mdiv;
33 unsigned int sdiv;
34 unsigned int kdiv;
35 };
36
37 struct imx_pll14xx_clk {
38 enum imx_pll14xx_type type;
39 const struct imx_pll14xx_rate_table *rate_table;
40 int rate_count;
41 int flags;
42 };
43
44 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
45 void __iomem *base,
46 const struct imx_pll14xx_clk *pll_clk);
47
48 struct clk *clk_register_gate2(struct device *dev, const char *name,
49 const char *parent_name, unsigned long flags,
50 void __iomem *reg, u8 bit_idx, u8 cgr_val,
51 u8 clk_gate_flags);
52
53 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
54 const char *parent_name, void __iomem *base,
55 u32 div_mask);
56
imx_clk_gate2(const char * name,const char * parent,void __iomem * reg,u8 shift)57 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
58 void __iomem *reg, u8 shift)
59 {
60 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
61 shift, 0x3, 0);
62 }
63
imx_clk_gate4(const char * name,const char * parent,void __iomem * reg,u8 shift)64 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
65 void __iomem *reg, u8 shift)
66 {
67 return clk_register_gate2(NULL, name, parent,
68 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
69 reg, shift, 0x3, 0);
70 }
71
imx_clk_gate4_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)72 static inline struct clk *imx_clk_gate4_flags(const char *name,
73 const char *parent, void __iomem *reg, u8 shift,
74 unsigned long flags)
75 {
76 return clk_register_gate2(NULL, name, parent,
77 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
78 reg, shift, 0x3, 0);
79 }
80
imx_clk_fixed_factor(const char * name,const char * parent,unsigned int mult,unsigned int div)81 static inline struct clk *imx_clk_fixed_factor(const char *name,
82 const char *parent, unsigned int mult, unsigned int div)
83 {
84 return clk_register_fixed_factor(NULL, name, parent,
85 CLK_SET_RATE_PARENT, mult, div);
86 }
87
imx_clk_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)88 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
89 void __iomem *reg, u8 shift, u8 width)
90 {
91 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
92 reg, shift, width, 0);
93 }
94
95 static inline struct clk *
imx_clk_busy_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,void __iomem * busy_reg,u8 busy_shift)96 imx_clk_busy_divider(const char *name, const char *parent, void __iomem *reg,
97 u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift)
98 {
99 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
100 reg, shift, width, 0);
101 }
102
imx_clk_divider2(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)103 static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
104 void __iomem *reg, u8 shift, u8 width)
105 {
106 return clk_register_divider(NULL, name, parent,
107 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
108 reg, shift, width, 0);
109 }
110
111 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
112 void __iomem *reg, u8 idx);
113
114 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
115 u8 shift, u8 width, const char * const *parents,
116 int num_parents, void (*fixup)(u32 *val));
117
imx_clk_mux_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)118 static inline struct clk *imx_clk_mux_flags(const char *name,
119 void __iomem *reg, u8 shift, u8 width,
120 const char * const *parents, int num_parents,
121 unsigned long flags)
122 {
123 return clk_register_mux(NULL, name, parents, num_parents,
124 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
125 width, 0);
126 }
127
imx_clk_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)128 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
129 u8 shift, u8 width, const char * const *parents,
130 int num_parents)
131 {
132 return clk_register_mux(NULL, name, parents, num_parents,
133 CLK_SET_RATE_NO_REPARENT, reg, shift,
134 width, 0);
135 }
136
137 static inline struct clk *
imx_clk_busy_mux(const char * name,void __iomem * reg,u8 shift,u8 width,void __iomem * busy_reg,u8 busy_shift,const char * const * parents,int num_parents)138 imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width,
139 void __iomem *busy_reg, u8 busy_shift,
140 const char * const *parents, int num_parents)
141 {
142 return clk_register_mux(NULL, name, parents, num_parents,
143 CLK_SET_RATE_NO_REPARENT, reg, shift,
144 width, 0);
145 }
146
imx_clk_mux2(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)147 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
148 u8 shift, u8 width, const char * const *parents,
149 int num_parents)
150 {
151 return clk_register_mux(NULL, name, parents, num_parents,
152 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
153 reg, shift, width, 0);
154 }
155
imx_clk_gate(const char * name,const char * parent,void __iomem * reg,u8 shift)156 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
157 void __iomem *reg, u8 shift)
158 {
159 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
160 shift, 0, NULL);
161 }
162
imx_clk_gate_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)163 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
164 void __iomem *reg, u8 shift, unsigned long flags)
165 {
166 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
167 shift, 0, NULL);
168 }
169
imx_clk_gate3(const char * name,const char * parent,void __iomem * reg,u8 shift)170 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
171 void __iomem *reg, u8 shift)
172 {
173 return clk_register_gate(NULL, name, parent,
174 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
175 reg, shift, 0, NULL);
176 }
177
178 struct clk *imx8m_clk_composite_flags(const char *name,
179 const char * const *parent_names,
180 int num_parents, void __iomem *reg, unsigned long flags);
181
182 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
183 imx8m_clk_composite_flags(name, parent_names, \
184 ARRAY_SIZE(parent_names), reg, \
185 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
186
187 #define imx8m_clk_composite(name, parent_names, reg) \
188 __imx8m_clk_composite(name, parent_names, reg, 0)
189
190 #define imx8m_clk_composite_critical(name, parent_names, reg) \
191 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
192
193 #endif /* __MACH_IMX_CLK_H */
194