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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017 NXP
4  *
5  * Peng Fan <peng.fan@nxp.com>
6  */
7 
8 #include <common.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/io.h>
12 #include <asm/arch/sys_proto.h>
13 #include <errno.h>
14 #include <linux/iopoll.h>
15 
16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
17 
decode_frac_pll(enum clk_root_src frac_pll)18 static u32 decode_frac_pll(enum clk_root_src frac_pll)
19 {
20 	u32 pll_cfg0, pll_cfg1, pllout;
21 	u32 pll_refclk_sel, pll_refclk;
22 	u32 divr_val, divq_val, divf_val, divff, divfi;
23 	u32 pllout_div_shift, pllout_div_mask, pllout_div;
24 
25 	switch (frac_pll) {
26 	case ARM_PLL_CLK:
27 		pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
28 		pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
29 		pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
30 		pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
31 		break;
32 	default:
33 		printf("Frac PLL %d not supporte\n", frac_pll);
34 		return 0;
35 	}
36 
37 	pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
38 	pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
39 
40 	/* Power down */
41 	if (pll_cfg0 & FRAC_PLL_PD_MASK)
42 		return 0;
43 
44 	/* output not enabled */
45 	if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
46 		return 0;
47 
48 	pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
49 
50 	if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
51 		pll_refclk = 25000000u;
52 	else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
53 		pll_refclk = 27000000u;
54 	else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
55 		pll_refclk = 27000000u;
56 	else
57 		pll_refclk = 0;
58 
59 	if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
60 		return pll_refclk;
61 
62 	divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
63 		FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
64 	divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
65 
66 	divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
67 		FRAC_PLL_FRAC_DIV_CTL_SHIFT;
68 	divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
69 
70 	divf_val = 1 + divfi + divff / (1 << 24);
71 
72 	pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
73 		((divq_val + 1) * 2);
74 
75 	return pllout / (pllout_div + 1);
76 }
77 
decode_sscg_pll(enum clk_root_src sscg_pll)78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
79 {
80 	u32 pll_cfg0, pll_cfg1, pll_cfg2;
81 	u32 pll_refclk_sel, pll_refclk;
82 	u32 divr1, divr2, divf1, divf2, divq, div;
83 	u32 sse;
84 	u32 pll_clke;
85 	u32 pllout_div_shift, pllout_div_mask, pllout_div;
86 	u32 pllout;
87 
88 	switch (sscg_pll) {
89 	case SYSTEM_PLL1_800M_CLK:
90 	case SYSTEM_PLL1_400M_CLK:
91 	case SYSTEM_PLL1_266M_CLK:
92 	case SYSTEM_PLL1_200M_CLK:
93 	case SYSTEM_PLL1_160M_CLK:
94 	case SYSTEM_PLL1_133M_CLK:
95 	case SYSTEM_PLL1_100M_CLK:
96 	case SYSTEM_PLL1_80M_CLK:
97 	case SYSTEM_PLL1_40M_CLK:
98 		pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
99 		pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
100 		pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
101 		pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
102 		pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
103 		break;
104 	case SYSTEM_PLL2_1000M_CLK:
105 	case SYSTEM_PLL2_500M_CLK:
106 	case SYSTEM_PLL2_333M_CLK:
107 	case SYSTEM_PLL2_250M_CLK:
108 	case SYSTEM_PLL2_200M_CLK:
109 	case SYSTEM_PLL2_166M_CLK:
110 	case SYSTEM_PLL2_125M_CLK:
111 	case SYSTEM_PLL2_100M_CLK:
112 	case SYSTEM_PLL2_50M_CLK:
113 		pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
114 		pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
115 		pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
116 		pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
117 		pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
118 		break;
119 	case SYSTEM_PLL3_CLK:
120 		pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
121 		pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
122 		pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
123 		pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
124 		pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
125 		break;
126 	case DRAM_PLL1_CLK:
127 		pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
128 		pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
129 		pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
130 		pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
131 		pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
132 		break;
133 	default:
134 		printf("sscg pll %d not supporte\n", sscg_pll);
135 		return 0;
136 	}
137 
138 	switch (sscg_pll) {
139 	case DRAM_PLL1_CLK:
140 		pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
141 		div = 1;
142 		break;
143 	case SYSTEM_PLL3_CLK:
144 		pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
145 		div = 1;
146 		break;
147 	case SYSTEM_PLL2_1000M_CLK:
148 	case SYSTEM_PLL1_800M_CLK:
149 		pll_clke = SSCG_PLL_CLKE_MASK;
150 		div = 1;
151 		break;
152 	case SYSTEM_PLL2_500M_CLK:
153 	case SYSTEM_PLL1_400M_CLK:
154 		pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
155 		div = 2;
156 		break;
157 	case SYSTEM_PLL2_333M_CLK:
158 	case SYSTEM_PLL1_266M_CLK:
159 		pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
160 		div = 3;
161 		break;
162 	case SYSTEM_PLL2_250M_CLK:
163 	case SYSTEM_PLL1_200M_CLK:
164 		pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
165 		div = 4;
166 		break;
167 	case SYSTEM_PLL2_200M_CLK:
168 	case SYSTEM_PLL1_160M_CLK:
169 		pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
170 		div = 5;
171 		break;
172 	case SYSTEM_PLL2_166M_CLK:
173 	case SYSTEM_PLL1_133M_CLK:
174 		pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
175 		div = 6;
176 		break;
177 	case SYSTEM_PLL2_125M_CLK:
178 	case SYSTEM_PLL1_100M_CLK:
179 		pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
180 		div = 8;
181 		break;
182 	case SYSTEM_PLL2_100M_CLK:
183 	case SYSTEM_PLL1_80M_CLK:
184 		pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
185 		div = 10;
186 		break;
187 	case SYSTEM_PLL2_50M_CLK:
188 	case SYSTEM_PLL1_40M_CLK:
189 		pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
190 		div = 20;
191 		break;
192 	default:
193 		printf("sscg pll %d not supporte\n", sscg_pll);
194 		return 0;
195 	}
196 
197 	/* Power down */
198 	if (pll_cfg0 & SSCG_PLL_PD_MASK)
199 		return 0;
200 
201 	/* output not enabled */
202 	if ((pll_cfg0 & pll_clke) == 0)
203 		return 0;
204 
205 	pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
206 	pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
207 
208 	pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
209 
210 	if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
211 		pll_refclk = 25000000u;
212 	else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
213 		pll_refclk = 27000000u;
214 	else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
215 		pll_refclk = 27000000u;
216 	else
217 		pll_refclk = 0;
218 
219 	/* We assume bypass1/2 are the same value */
220 	if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
221 	    (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
222 		return pll_refclk;
223 
224 	divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
225 		SSCG_PLL_REF_DIVR1_SHIFT;
226 	divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
227 		SSCG_PLL_REF_DIVR2_SHIFT;
228 	divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
229 		SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
230 	divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
231 		SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
232 	divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
233 		SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
234 	sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
235 
236 	if (sse)
237 		sse = 8;
238 	else
239 		sse = 2;
240 
241 	pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
242 		(divr2 + 1) * (divf2 + 1) / (divq + 1);
243 
244 	return pllout / (pllout_div + 1) / div;
245 }
246 
get_root_src_clk(enum clk_root_src root_src)247 static u32 get_root_src_clk(enum clk_root_src root_src)
248 {
249 	switch (root_src) {
250 	case OSC_25M_CLK:
251 		return 25000000;
252 	case OSC_27M_CLK:
253 		return 27000000;
254 	case OSC_32K_CLK:
255 		return 32768;
256 	case ARM_PLL_CLK:
257 		return decode_frac_pll(root_src);
258 	case SYSTEM_PLL1_800M_CLK:
259 	case SYSTEM_PLL1_400M_CLK:
260 	case SYSTEM_PLL1_266M_CLK:
261 	case SYSTEM_PLL1_200M_CLK:
262 	case SYSTEM_PLL1_160M_CLK:
263 	case SYSTEM_PLL1_133M_CLK:
264 	case SYSTEM_PLL1_100M_CLK:
265 	case SYSTEM_PLL1_80M_CLK:
266 	case SYSTEM_PLL1_40M_CLK:
267 	case SYSTEM_PLL2_1000M_CLK:
268 	case SYSTEM_PLL2_500M_CLK:
269 	case SYSTEM_PLL2_333M_CLK:
270 	case SYSTEM_PLL2_250M_CLK:
271 	case SYSTEM_PLL2_200M_CLK:
272 	case SYSTEM_PLL2_166M_CLK:
273 	case SYSTEM_PLL2_125M_CLK:
274 	case SYSTEM_PLL2_100M_CLK:
275 	case SYSTEM_PLL2_50M_CLK:
276 	case SYSTEM_PLL3_CLK:
277 		return decode_sscg_pll(root_src);
278 	default:
279 		return 0;
280 	}
281 
282 	return 0;
283 }
284 
get_root_clk(enum clk_root_index clock_id)285 static u32 get_root_clk(enum clk_root_index clock_id)
286 {
287 	enum clk_root_src root_src;
288 	u32 post_podf, pre_podf, root_src_clk;
289 
290 	if (clock_root_enabled(clock_id) <= 0)
291 		return 0;
292 
293 	if (clock_get_prediv(clock_id, &pre_podf) < 0)
294 		return 0;
295 
296 	if (clock_get_postdiv(clock_id, &post_podf) < 0)
297 		return 0;
298 
299 	if (clock_get_src(clock_id, &root_src) < 0)
300 		return 0;
301 
302 	root_src_clk = get_root_src_clk(root_src);
303 
304 	return root_src_clk / (post_podf + 1) / (pre_podf + 1);
305 }
306 
307 #ifdef CONFIG_MXC_OCOTP
enable_ocotp_clk(unsigned char enable)308 void enable_ocotp_clk(unsigned char enable)
309 {
310 	clock_enable(CCGR_OCOTP, !!enable);
311 }
312 #endif
313 
enable_i2c_clk(unsigned char enable,unsigned int i2c_num)314 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
315 {
316 	/* 0 - 3 is valid i2c num */
317 	if (i2c_num > 3)
318 		return -EINVAL;
319 
320 	clock_enable(CCGR_I2C1 + i2c_num, !!enable);
321 
322 	return 0;
323 }
324 
mxc_get_clock(enum mxc_clock clk)325 unsigned int mxc_get_clock(enum mxc_clock clk)
326 {
327 	u32 val;
328 
329 	if (clk == MXC_ARM_CLK)
330 		return get_root_clk(ARM_A53_CLK_ROOT);
331 
332 	if (clk == MXC_IPG_CLK) {
333 		clock_get_target_val(IPG_CLK_ROOT, &val);
334 		val = val & 0x3;
335 		return get_root_clk(AHB_CLK_ROOT) / (val + 1);
336 	}
337 
338 	return get_root_clk(clk);
339 }
340 
imx_get_uartclk(void)341 u32 imx_get_uartclk(void)
342 {
343 	return mxc_get_clock(UART1_CLK_ROOT);
344 }
345 
mxs_set_lcdclk(u32 base_addr,u32 freq)346 void mxs_set_lcdclk(u32 base_addr, u32 freq)
347 {
348 	/*
349 	 * LCDIF_PIXEL_CLK: select 800MHz root clock,
350 	 * select pre divider 8, output is 100 MHz
351 	 */
352 	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
353 			     CLK_ROOT_SOURCE_SEL(4) |
354 			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
355 }
356 
init_wdog_clk(void)357 void init_wdog_clk(void)
358 {
359 	clock_enable(CCGR_WDOG1, 0);
360 	clock_enable(CCGR_WDOG2, 0);
361 	clock_enable(CCGR_WDOG3, 0);
362 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
363 			     CLK_ROOT_SOURCE_SEL(0));
364 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
365 			     CLK_ROOT_SOURCE_SEL(0));
366 	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
367 			     CLK_ROOT_SOURCE_SEL(0));
368 	clock_enable(CCGR_WDOG1, 1);
369 	clock_enable(CCGR_WDOG2, 1);
370 	clock_enable(CCGR_WDOG3, 1);
371 }
372 
init_usb_clk(void)373 void init_usb_clk(void)
374 {
375 	if (!is_usb_boot()) {
376 		clock_enable(CCGR_USB_CTRL1, 0);
377 		clock_enable(CCGR_USB_CTRL2, 0);
378 		clock_enable(CCGR_USB_PHY1, 0);
379 		clock_enable(CCGR_USB_PHY2, 0);
380 		/* 500MHz */
381 		clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
382 				     CLK_ROOT_SOURCE_SEL(1));
383 		/* 100MHz */
384 		clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
385 				     CLK_ROOT_SOURCE_SEL(1));
386 		/* 100MHz */
387 		clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
388 				     CLK_ROOT_SOURCE_SEL(1));
389 		clock_enable(CCGR_USB_CTRL1, 1);
390 		clock_enable(CCGR_USB_CTRL2, 1);
391 		clock_enable(CCGR_USB_PHY1, 1);
392 		clock_enable(CCGR_USB_PHY2, 1);
393 	}
394 }
395 
init_nand_clk(void)396 void init_nand_clk(void)
397 {
398 	clock_enable(CCGR_RAWNAND, 0);
399 	clock_set_target_val(NAND_CLK_ROOT,
400 			     CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(3) |
401 			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4));
402 	clock_enable(CCGR_RAWNAND, 1);
403 }
404 
init_uart_clk(u32 index)405 void init_uart_clk(u32 index)
406 {
407 	/* Set uart clock root 25M OSC */
408 	switch (index) {
409 	case 0:
410 		clock_enable(CCGR_UART1, 0);
411 		clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
412 				     CLK_ROOT_SOURCE_SEL(0));
413 		clock_enable(CCGR_UART1, 1);
414 		return;
415 	case 1:
416 		clock_enable(CCGR_UART2, 0);
417 		clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
418 				     CLK_ROOT_SOURCE_SEL(0));
419 		clock_enable(CCGR_UART2, 1);
420 		return;
421 	case 2:
422 		clock_enable(CCGR_UART3, 0);
423 		clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
424 				     CLK_ROOT_SOURCE_SEL(0));
425 		clock_enable(CCGR_UART3, 1);
426 		return;
427 	case 3:
428 		clock_enable(CCGR_UART4, 0);
429 		clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
430 				     CLK_ROOT_SOURCE_SEL(0));
431 		clock_enable(CCGR_UART4, 1);
432 		return;
433 	default:
434 		printf("Invalid uart index\n");
435 		return;
436 	}
437 }
438 
init_clk_usdhc(u32 index)439 void init_clk_usdhc(u32 index)
440 {
441 	/*
442 	 * set usdhc clock root
443 	 * sys pll1 400M
444 	 */
445 	switch (index) {
446 	case 0:
447 		clock_enable(CCGR_USDHC1, 0);
448 		clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
449 				     CLK_ROOT_SOURCE_SEL(1) |
450 				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
451 		clock_enable(CCGR_USDHC1, 1);
452 		return;
453 	case 1:
454 		clock_enable(CCGR_USDHC2, 0);
455 		clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
456 				     CLK_ROOT_SOURCE_SEL(1) |
457 				     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
458 		clock_enable(CCGR_USDHC2, 1);
459 		return;
460 	default:
461 		printf("Invalid usdhc index\n");
462 		return;
463 	}
464 }
465 
set_clk_qspi(void)466 int set_clk_qspi(void)
467 {
468 	/*
469 	 * set qspi root
470 	 * sys pll1 100M
471 	 */
472 	clock_enable(CCGR_QSPI, 0);
473 	clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
474 			     CLK_ROOT_SOURCE_SEL(7));
475 	clock_enable(CCGR_QSPI, 1);
476 
477 	return 0;
478 }
479 
480 #ifdef CONFIG_FEC_MXC
set_clk_enet(enum enet_freq type)481 int set_clk_enet(enum enet_freq type)
482 {
483 	u32 target;
484 	u32 enet1_ref;
485 
486 	switch (type) {
487 	case ENET_125MHZ:
488 		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
489 		break;
490 	case ENET_50MHZ:
491 		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
492 		break;
493 	case ENET_25MHZ:
494 		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
495 		break;
496 	default:
497 		return -EINVAL;
498 	}
499 
500 	/* disable the clock first */
501 	clock_enable(CCGR_ENET1, 0);
502 	clock_enable(CCGR_SIM_ENET, 0);
503 
504 	/* set enet axi clock 266Mhz */
505 	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
506 		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
507 		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
508 	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
509 
510 	target = CLK_ROOT_ON | enet1_ref |
511 		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
512 		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
513 	clock_set_target_val(ENET_REF_CLK_ROOT, target);
514 
515 	target = CLK_ROOT_ON |
516 		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
517 		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
518 		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
519 	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
520 
521 	/* enable clock */
522 	clock_enable(CCGR_SIM_ENET, 1);
523 	clock_enable(CCGR_ENET1, 1);
524 
525 	return 0;
526 }
527 #endif
528 
imx_get_fecclk(void)529 u32 imx_get_fecclk(void)
530 {
531 	return get_root_clk(ENET_AXI_CLK_ROOT);
532 }
533 
534 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
535 	DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
536 				CLK_ROOT_PRE_DIV2),
537 	DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
538 				CLK_ROOT_PRE_DIV2),
539 	DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
540 				CLK_ROOT_PRE_DIV2),
541 };
542 
dram_enable_bypass(ulong clk_val)543 void dram_enable_bypass(ulong clk_val)
544 {
545 	int i;
546 	struct dram_bypass_clk_setting *config;
547 
548 	for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
549 		if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
550 			break;
551 	}
552 
553 	if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
554 		printf("No matched freq table %lu\n", clk_val);
555 		return;
556 	}
557 
558 	config = &imx8mq_dram_bypass_tbl[i];
559 
560 	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
561 			     CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
562 			     CLK_ROOT_PRE_DIV(config->alt_pre_div));
563 	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
564 			     CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
565 			     CLK_ROOT_PRE_DIV(config->apb_pre_div));
566 	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
567 			     CLK_ROOT_SOURCE_SEL(1));
568 }
569 
dram_disable_bypass(void)570 void dram_disable_bypass(void)
571 {
572 	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
573 			     CLK_ROOT_SOURCE_SEL(0));
574 	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
575 			     CLK_ROOT_SOURCE_SEL(4) |
576 			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
577 }
578 
579 #ifdef CONFIG_SPL_BUILD
dram_pll_init(ulong pll_val)580 void dram_pll_init(ulong pll_val)
581 {
582 	u32 val;
583 	void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
584 	void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
585 
586 	/* Bypass */
587 	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
588 	setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
589 
590 	switch (pll_val) {
591 	case MHZ(800):
592 		val = readl(pll_cfg_reg2);
593 		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
594 			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
595 			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
596 			 SSCG_PLL_REF_DIVR2_MASK);
597 		val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
598 		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
599 		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
600 		val |= SSCG_PLL_REF_DIVR2_VAL(29);
601 		writel(val, pll_cfg_reg2);
602 		break;
603 	case MHZ(600):
604 		val = readl(pll_cfg_reg2);
605 		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
606 			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
607 			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
608 			 SSCG_PLL_REF_DIVR2_MASK);
609 		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
610 		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
611 		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
612 		val |= SSCG_PLL_REF_DIVR2_VAL(29);
613 		writel(val, pll_cfg_reg2);
614 		break;
615 	case MHZ(400):
616 		val = readl(pll_cfg_reg2);
617 		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
618 			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
619 			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
620 			 SSCG_PLL_REF_DIVR2_MASK);
621 		val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
622 		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
623 		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
624 		val |= SSCG_PLL_REF_DIVR2_VAL(29);
625 		writel(val, pll_cfg_reg2);
626 		break;
627 	case MHZ(167):
628 		val = readl(pll_cfg_reg2);
629 		val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
630 			 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
631 			 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
632 			 SSCG_PLL_REF_DIVR2_MASK);
633 		val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
634 		val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
635 		val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
636 		val |= SSCG_PLL_REF_DIVR2_VAL(30);
637 		writel(val, pll_cfg_reg2);
638 		break;
639 	default:
640 		break;
641 	}
642 
643 	/* Clear power down bit */
644 	clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
645 	/* Eanble ARM_PLL/SYS_PLL  */
646 	setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
647 
648 	/* Clear bypass */
649 	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
650 	__udelay(100);
651 	clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
652 	/* Wait lock */
653 	while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
654 		;
655 }
656 
frac_pll_init(u32 pll,enum frac_pll_out_val val)657 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
658 {
659 	void __iomem *pll_cfg0, __iomem *pll_cfg1;
660 	u32 val_cfg0, val_cfg1;
661 	int ret;
662 
663 	switch (pll) {
664 	case ANATOP_ARM_PLL:
665 		pll_cfg0 = &ana_pll->arm_pll_cfg0;
666 		pll_cfg1 = &ana_pll->arm_pll_cfg1;
667 
668 		if (val == FRAC_PLL_OUT_1000M)
669 			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
670 		else
671 			val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
672 		val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
673 			FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
674 			FRAC_PLL_REFCLK_DIV_VAL(4) |
675 			FRAC_PLL_OUTPUT_DIV_VAL(0);
676 		break;
677 	default:
678 		return -EINVAL;
679 	}
680 
681 	/* bypass the clock */
682 	setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
683 	/* Set the value */
684 	writel(val_cfg1, pll_cfg1);
685 	writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
686 	val_cfg0 = readl(pll_cfg0);
687 	/* unbypass the clock */
688 	clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
689 	ret = readl_poll_timeout(pll_cfg0, val_cfg0,
690 				 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
691 	if (ret)
692 		printf("%s timeout\n", __func__);
693 	clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
694 
695 	return 0;
696 }
697 
sscg_pll_init(u32 pll)698 int sscg_pll_init(u32 pll)
699 {
700 	void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
701 	u32 val_cfg0, val_cfg1, val_cfg2, val;
702 	u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
703 	int ret;
704 
705 	switch (pll) {
706 	case ANATOP_SYSTEM_PLL1:
707 		pll_cfg0 = &ana_pll->sys_pll1_cfg0;
708 		pll_cfg1 = &ana_pll->sys_pll1_cfg1;
709 		pll_cfg2 = &ana_pll->sys_pll1_cfg2;
710 		/* 800MHz */
711 		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
712 			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
713 		val_cfg1 = 0;
714 		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
715 			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
716 			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
717 			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
718 			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
719 			SSCG_PLL_REFCLK_SEL_OSC_25M;
720 		break;
721 	case ANATOP_SYSTEM_PLL2:
722 		pll_cfg0 = &ana_pll->sys_pll2_cfg0;
723 		pll_cfg1 = &ana_pll->sys_pll2_cfg1;
724 		pll_cfg2 = &ana_pll->sys_pll2_cfg2;
725 		/* 1000MHz */
726 		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
727 			SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
728 		val_cfg1 = 0;
729 		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
730 			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
731 			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
732 			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
733 			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
734 			SSCG_PLL_REFCLK_SEL_OSC_25M;
735 		break;
736 	case ANATOP_SYSTEM_PLL3:
737 		pll_cfg0 = &ana_pll->sys_pll3_cfg0;
738 		pll_cfg1 = &ana_pll->sys_pll3_cfg1;
739 		pll_cfg2 = &ana_pll->sys_pll3_cfg2;
740 		/* 800MHz */
741 		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
742 			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
743 		val_cfg1 = 0;
744 		val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK |  SSCG_PLL_LOCK_SEL_MASK |
745 			SSCG_PLL_REFCLK_SEL_OSC_25M;
746 		break;
747 	default:
748 		return -EINVAL;
749 	}
750 
751 	/*bypass*/
752 	setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
753 	/* set value */
754 	writel(val_cfg2, pll_cfg2);
755 	writel(val_cfg1, pll_cfg1);
756 	/*unbypass1 and wait 70us */
757 	writel(val_cfg0 | bypass2_mask, pll_cfg1);
758 
759 	__udelay(70);
760 
761 	/* unbypass2 and wait lock */
762 	writel(val_cfg0, pll_cfg1);
763 	ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
764 	if (ret)
765 		printf("%s timeout\n", __func__);
766 
767 	return ret;
768 }
769 
clock_init(void)770 int clock_init(void)
771 {
772 	u32 grade;
773 
774 	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
775 			     CLK_ROOT_SOURCE_SEL(0));
776 
777 	/*
778 	 * 8MQ only supports two grades: consumer and industrial.
779 	 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
780 	 */
781 	grade = get_cpu_temp_grade(NULL, NULL);
782 	if (!grade) {
783 		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
784 		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
785 			     CLK_ROOT_SOURCE_SEL(1) |
786 			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
787 	} else {
788 		frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
789 		clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
790 			     CLK_ROOT_SOURCE_SEL(1) |
791 			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
792 	}
793 	/*
794 	 * According to ANAMIX SPEC
795 	 * sys pll1 fixed at 800MHz
796 	 * sys pll2 fixed at 1GHz
797 	 * Here we only enable the outputs.
798 	 */
799 	setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
800 		     SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
801 		     SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
802 		     SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
803 		     SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
804 
805 	setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
806 		     SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
807 		     SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
808 		     SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
809 		     SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
810 
811 	clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
812 			     CLK_ROOT_SOURCE_SEL(1));
813 
814 	init_wdog_clk();
815 	clock_enable(CCGR_TSENSOR, 1);
816 	clock_enable(CCGR_OCOTP, 1);
817 
818 	/* config GIC ROOT to sys_pll2_200m */
819 	clock_enable(CCGR_GIC, 0);
820 	clock_set_target_val(GIC_CLK_ROOT,
821 			     CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
822 	clock_enable(CCGR_GIC, 1);
823 
824 	return 0;
825 }
826 #endif
827 
828 /*
829  * Dump some clockes.
830  */
831 #ifndef CONFIG_SPL_BUILD
do_imx8m_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])832 int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
833 		       char * const argv[])
834 {
835 	u32 freq;
836 
837 	freq = decode_frac_pll(ARM_PLL_CLK);
838 	printf("ARM_PLL    %8d MHz\n", freq / 1000000);
839 	freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
840 	printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
841 	freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
842 	printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
843 	freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
844 	printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
845 	freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
846 	printf("SYS_PLL1_200    %8d MHz\n", freq / 1000000);
847 	freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
848 	printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
849 	freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
850 	printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
851 	freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
852 	printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
853 	freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
854 	printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
855 	freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
856 	printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
857 	freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
858 	printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
859 	freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
860 	printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
861 	freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
862 	printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
863 	freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
864 	printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
865 	freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
866 	printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
867 	freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
868 	printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
869 	freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
870 	printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
871 	freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
872 	printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
873 	freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
874 	printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
875 	freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
876 	printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
877 	freq = mxc_get_clock(UART1_CLK_ROOT);
878 	printf("UART1          %8d MHz\n", freq / 1000000);
879 	freq = mxc_get_clock(USDHC1_CLK_ROOT);
880 	printf("USDHC1         %8d MHz\n", freq / 1000000);
881 	freq = mxc_get_clock(QSPI_CLK_ROOT);
882 	printf("QSPI           %8d MHz\n", freq / 1000000);
883 	return 0;
884 }
885 
886 U_BOOT_CMD(
887 	clocks,	CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
888 	"display clocks",
889 	""
890 );
891 #endif
892