1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <time.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "util/ralloc.h"
28 #include "util/u_inlines.h"
29 #include "util/format/u_format.h"
30 #include "util/u_upload_mgr.h"
31 #include "drm-uapi/i915_drm.h"
32 #include "iris_context.h"
33 #include "iris_resource.h"
34 #include "iris_screen.h"
35 #include "common/gen_defines.h"
36 #include "common/gen_sample_positions.h"
37
38 /**
39 * For debugging purposes, this returns a time in seconds.
40 */
41 double
get_time(void)42 get_time(void)
43 {
44 struct timespec tp;
45
46 clock_gettime(CLOCK_MONOTONIC, &tp);
47
48 return tp.tv_sec + tp.tv_nsec / 1000000000.0;
49 }
50
51 /**
52 * The pipe->set_debug_callback() driver hook.
53 */
54 static void
iris_set_debug_callback(struct pipe_context * ctx,const struct pipe_debug_callback * cb)55 iris_set_debug_callback(struct pipe_context *ctx,
56 const struct pipe_debug_callback *cb)
57 {
58 struct iris_context *ice = (struct iris_context *)ctx;
59
60 if (cb)
61 ice->dbg = *cb;
62 else
63 memset(&ice->dbg, 0, sizeof(ice->dbg));
64 }
65
66 /**
67 * Called from the batch module when it detects a GPU hang.
68 *
69 * In this case, we've lost our GEM context, and can't rely on any existing
70 * state on the GPU. We must mark everything dirty and wipe away any saved
71 * assumptions about the last known state of the GPU.
72 */
73 void
iris_lost_context_state(struct iris_batch * batch)74 iris_lost_context_state(struct iris_batch *batch)
75 {
76 /* The batch module doesn't have an iris_context, because we want to
77 * avoid introducing lots of layering violations. Unfortunately, here
78 * we do need to inform the context of batch catastrophe. We know the
79 * batch is one of our context's, so hackily claw our way back.
80 */
81 struct iris_context *ice = NULL;
82
83 if (batch->name == IRIS_BATCH_RENDER) {
84 ice = container_of(batch, ice, batches[IRIS_BATCH_RENDER]);
85 assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
86
87 batch->screen->vtbl.init_render_context(batch);
88 } else if (batch->name == IRIS_BATCH_COMPUTE) {
89 ice = container_of(batch, ice, batches[IRIS_BATCH_COMPUTE]);
90 assert(&ice->batches[IRIS_BATCH_COMPUTE] == batch);
91
92 batch->screen->vtbl.init_compute_context(batch);
93 } else {
94 unreachable("unhandled batch reset");
95 }
96
97 ice->state.dirty = ~0ull;
98 ice->state.stage_dirty = ~0ull;
99 ice->state.current_hash_scale = 0;
100 memset(ice->state.last_block, 0, sizeof(ice->state.last_block));
101 memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
102 batch->last_surface_base_address = ~0ull;
103 batch->last_aux_map_state = 0;
104 batch->screen->vtbl.lost_genx_state(ice, batch);
105 }
106
107 static enum pipe_reset_status
iris_get_device_reset_status(struct pipe_context * ctx)108 iris_get_device_reset_status(struct pipe_context *ctx)
109 {
110 struct iris_context *ice = (struct iris_context *)ctx;
111
112 enum pipe_reset_status worst_reset = PIPE_NO_RESET;
113
114 /* Check the reset status of each batch's hardware context, and take the
115 * worst status (if one was guilty, proclaim guilt).
116 */
117 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
118 /* This will also recreate the hardware contexts as necessary, so any
119 * future queries will show no resets. We only want to report once.
120 */
121 enum pipe_reset_status batch_reset =
122 iris_batch_check_for_reset(&ice->batches[i]);
123
124 if (batch_reset == PIPE_NO_RESET)
125 continue;
126
127 if (worst_reset == PIPE_NO_RESET) {
128 worst_reset = batch_reset;
129 } else {
130 /* GUILTY < INNOCENT < UNKNOWN */
131 worst_reset = MIN2(worst_reset, batch_reset);
132 }
133 }
134
135 if (worst_reset != PIPE_NO_RESET && ice->reset.reset)
136 ice->reset.reset(ice->reset.data, worst_reset);
137
138 return worst_reset;
139 }
140
141 static void
iris_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)142 iris_set_device_reset_callback(struct pipe_context *ctx,
143 const struct pipe_device_reset_callback *cb)
144 {
145 struct iris_context *ice = (struct iris_context *)ctx;
146
147 if (cb)
148 ice->reset = *cb;
149 else
150 memset(&ice->reset, 0, sizeof(ice->reset));
151 }
152
153 static void
iris_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)154 iris_get_sample_position(struct pipe_context *ctx,
155 unsigned sample_count,
156 unsigned sample_index,
157 float *out_value)
158 {
159 union {
160 struct {
161 float x[16];
162 float y[16];
163 } a;
164 struct {
165 float _0XOffset, _1XOffset, _2XOffset, _3XOffset,
166 _4XOffset, _5XOffset, _6XOffset, _7XOffset,
167 _8XOffset, _9XOffset, _10XOffset, _11XOffset,
168 _12XOffset, _13XOffset, _14XOffset, _15XOffset;
169 float _0YOffset, _1YOffset, _2YOffset, _3YOffset,
170 _4YOffset, _5YOffset, _6YOffset, _7YOffset,
171 _8YOffset, _9YOffset, _10YOffset, _11YOffset,
172 _12YOffset, _13YOffset, _14YOffset, _15YOffset;
173 } v;
174 } u;
175 switch (sample_count) {
176 case 1: GEN_SAMPLE_POS_1X(u.v._); break;
177 case 2: GEN_SAMPLE_POS_2X(u.v._); break;
178 case 4: GEN_SAMPLE_POS_4X(u.v._); break;
179 case 8: GEN_SAMPLE_POS_8X(u.v._); break;
180 case 16: GEN_SAMPLE_POS_16X(u.v._); break;
181 default: unreachable("invalid sample count");
182 }
183
184 out_value[0] = u.a.x[sample_index];
185 out_value[1] = u.a.y[sample_index];
186 }
187
188 static bool
create_dirty_dmabuf_set(struct iris_context * ice)189 create_dirty_dmabuf_set(struct iris_context *ice)
190 {
191 assert(ice->dirty_dmabufs == NULL);
192
193 ice->dirty_dmabufs = _mesa_pointer_set_create(ice);
194 return ice->dirty_dmabufs != NULL;
195 }
196
197 void
iris_mark_dirty_dmabuf(struct iris_context * ice,struct pipe_resource * res)198 iris_mark_dirty_dmabuf(struct iris_context *ice,
199 struct pipe_resource *res)
200 {
201 if (!_mesa_set_search(ice->dirty_dmabufs, res)) {
202 _mesa_set_add(ice->dirty_dmabufs, res);
203 pipe_reference(NULL, &res->reference);
204 }
205 }
206
207 static void
clear_dirty_dmabuf_set(struct iris_context * ice)208 clear_dirty_dmabuf_set(struct iris_context *ice)
209 {
210 set_foreach(ice->dirty_dmabufs, entry) {
211 struct pipe_resource *res = (struct pipe_resource *)entry->key;
212 if (pipe_reference(&res->reference, NULL))
213 res->screen->resource_destroy(res->screen, res);
214 }
215
216 _mesa_set_clear(ice->dirty_dmabufs, NULL);
217 }
218
219 void
iris_flush_dirty_dmabufs(struct iris_context * ice)220 iris_flush_dirty_dmabufs(struct iris_context *ice)
221 {
222 set_foreach(ice->dirty_dmabufs, entry) {
223 struct pipe_resource *res = (struct pipe_resource *)entry->key;
224 ice->ctx.flush_resource(&ice->ctx, res);
225 }
226
227 clear_dirty_dmabuf_set(ice);
228 }
229
230
231 /**
232 * Destroy a context, freeing any associated memory.
233 */
234 static void
iris_destroy_context(struct pipe_context * ctx)235 iris_destroy_context(struct pipe_context *ctx)
236 {
237 struct iris_context *ice = (struct iris_context *)ctx;
238 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
239
240 if (ctx->stream_uploader)
241 u_upload_destroy(ctx->stream_uploader);
242
243 clear_dirty_dmabuf_set(ice);
244
245 screen->vtbl.destroy_state(ice);
246 iris_destroy_program_cache(ice);
247 iris_destroy_border_color_pool(ice);
248 u_upload_destroy(ice->state.surface_uploader);
249 u_upload_destroy(ice->state.dynamic_uploader);
250 u_upload_destroy(ice->query_buffer_uploader);
251
252 iris_batch_free(&ice->batches[IRIS_BATCH_RENDER]);
253 iris_batch_free(&ice->batches[IRIS_BATCH_COMPUTE]);
254 iris_destroy_binder(&ice->state.binder);
255
256 slab_destroy_child(&ice->transfer_pool);
257
258 ralloc_free(ice);
259 }
260
261 #define genX_call(devinfo, func, ...) \
262 switch (devinfo->gen) { \
263 case 12: \
264 gen12_##func(__VA_ARGS__); \
265 break; \
266 case 11: \
267 gen11_##func(__VA_ARGS__); \
268 break; \
269 case 9: \
270 gen9_##func(__VA_ARGS__); \
271 break; \
272 case 8: \
273 gen8_##func(__VA_ARGS__); \
274 break; \
275 default: \
276 unreachable("Unknown hardware generation"); \
277 }
278
279 /**
280 * Create a context.
281 *
282 * This is where each context begins.
283 */
284 struct pipe_context *
iris_create_context(struct pipe_screen * pscreen,void * priv,unsigned flags)285 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
286 {
287 struct iris_screen *screen = (struct iris_screen*)pscreen;
288 const struct gen_device_info *devinfo = &screen->devinfo;
289 struct iris_context *ice = rzalloc(NULL, struct iris_context);
290
291 if (!ice)
292 return NULL;
293
294 struct pipe_context *ctx = &ice->ctx;
295
296 ctx->screen = pscreen;
297 ctx->priv = priv;
298
299 ctx->stream_uploader = u_upload_create_default(ctx);
300 if (!ctx->stream_uploader) {
301 free(ctx);
302 return NULL;
303 }
304 ctx->const_uploader = ctx->stream_uploader;
305
306 if (!create_dirty_dmabuf_set(ice)) {
307 ralloc_free(ice);
308 return NULL;
309 }
310
311 ctx->destroy = iris_destroy_context;
312 ctx->set_debug_callback = iris_set_debug_callback;
313 ctx->set_device_reset_callback = iris_set_device_reset_callback;
314 ctx->get_device_reset_status = iris_get_device_reset_status;
315 ctx->get_sample_position = iris_get_sample_position;
316
317 iris_init_context_fence_functions(ctx);
318 iris_init_blit_functions(ctx);
319 iris_init_clear_functions(ctx);
320 iris_init_program_functions(ctx);
321 iris_init_resource_functions(ctx);
322 iris_init_flush_functions(ctx);
323 iris_init_perfquery_functions(ctx);
324
325 iris_init_program_cache(ice);
326 iris_init_border_color_pool(ice);
327 iris_init_binder(ice);
328
329 slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
330
331 ice->state.surface_uploader =
332 u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
333 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE);
334 ice->state.dynamic_uploader =
335 u_upload_create(ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
336 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE);
337
338 ice->query_buffer_uploader =
339 u_upload_create(ctx, 4096, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
340 0);
341
342 genX_call(devinfo, init_state, ice);
343 genX_call(devinfo, init_blorp, ice);
344 genX_call(devinfo, init_query, ice);
345
346 int priority = 0;
347 if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
348 priority = GEN_CONTEXT_HIGH_PRIORITY;
349 if (flags & PIPE_CONTEXT_LOW_PRIORITY)
350 priority = GEN_CONTEXT_LOW_PRIORITY;
351
352 if (INTEL_DEBUG & DEBUG_BATCH)
353 ice->state.sizes = _mesa_hash_table_u64_create(ice);
354
355 for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
356 iris_init_batch(ice, (enum iris_batch_name) i, priority);
357 }
358
359 screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
360 screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
361
362 return ctx;
363 }
364