1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #ifndef V8_CODEGEN_ARM64_CONSTANTS_ARM64_H_
6 #define V8_CODEGEN_ARM64_CONSTANTS_ARM64_H_
7
8 #include "src/base/macros.h"
9 #include "src/common/globals.h"
10
11 // Assert that this is an LP64 system, or LLP64 on Windows.
12 STATIC_ASSERT(sizeof(int) == sizeof(int32_t));
13 #if defined(V8_OS_WIN)
14 STATIC_ASSERT(sizeof(1L) == sizeof(int32_t));
15 #else
16 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int)
17 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t));
18 #endif
19 STATIC_ASSERT(sizeof(void*) == sizeof(int64_t));
20 STATIC_ASSERT(sizeof(1) == sizeof(int32_t));
21
22 // Get the standard printf format macros for C99 stdint types.
23 #ifndef __STDC_FORMAT_MACROS
24 #define __STDC_FORMAT_MACROS
25 #endif
26 #include <inttypes.h>
27
28 namespace v8 {
29 namespace internal {
30
31 constexpr size_t kMaxPCRelativeCodeRangeInMB = 128;
32
33 constexpr uint8_t kInstrSize = 4;
34 constexpr uint8_t kInstrSizeLog2 = 2;
35 constexpr uint8_t kLoadLiteralScaleLog2 = 2;
36 constexpr uint8_t kLoadLiteralScale = 1 << kLoadLiteralScaleLog2;
37 constexpr int kMaxLoadLiteralRange = 1 * MB;
38
39 const int kNumberOfRegisters = 32;
40 const int kNumberOfVRegisters = 32;
41 // Callee saved registers are x19-x28.
42 const int kNumberOfCalleeSavedRegisters = 10;
43 // Callee saved FP registers are d8-d15.
44 const int kNumberOfCalleeSavedVRegisters = 8;
45 const int kWRegSizeInBits = 32;
46 const int kWRegSizeInBitsLog2 = 5;
47 const int kWRegSize = kWRegSizeInBits >> 3;
48 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3;
49 const int kXRegSizeInBits = 64;
50 const int kXRegSizeInBitsLog2 = 6;
51 const int kXRegSize = kXRegSizeInBits >> 3;
52 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3;
53 const int kSRegSizeInBits = 32;
54 const int kSRegSizeInBitsLog2 = 5;
55 const int kSRegSize = kSRegSizeInBits >> 3;
56 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3;
57 const int kDRegSizeInBits = 64;
58 const int kDRegSizeInBitsLog2 = 6;
59 const int kDRegSize = kDRegSizeInBits >> 3;
60 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3;
61 const int kDRegSizeInBytesLog2 = kDRegSizeInBitsLog2 - 3;
62 const int kBRegSizeInBits = 8;
63 const int kBRegSize = kBRegSizeInBits >> 3;
64 const int kHRegSizeInBits = 16;
65 const int kHRegSize = kHRegSizeInBits >> 3;
66 const int kQRegSizeInBits = 128;
67 const int kQRegSizeInBitsLog2 = 7;
68 const int kQRegSize = kQRegSizeInBits >> 3;
69 const int kQRegSizeLog2 = kQRegSizeInBitsLog2 - 3;
70 const int kVRegSizeInBits = kQRegSizeInBits;
71 const int kVRegSize = kVRegSizeInBits >> 3;
72 const int64_t kWRegMask = 0x00000000ffffffffL;
73 const int64_t kXRegMask = 0xffffffffffffffffL;
74 const int64_t kSRegMask = 0x00000000ffffffffL;
75 const int64_t kDRegMask = 0xffffffffffffffffL;
76 // TODO(all) check if the expression below works on all compilers or if it
77 // triggers an overflow error.
78 const int64_t kDSignBit = 63;
79 const int64_t kDSignMask = 0x1LL << kDSignBit;
80 const int64_t kSSignBit = 31;
81 const int64_t kSSignMask = 0x1LL << kSSignBit;
82 const int64_t kXSignBit = 63;
83 const int64_t kXSignMask = 0x1LL << kXSignBit;
84 const int64_t kWSignBit = 31;
85 const int64_t kWSignMask = 0x1LL << kWSignBit;
86 const int64_t kDQuietNanBit = 51;
87 const int64_t kDQuietNanMask = 0x1LL << kDQuietNanBit;
88 const int64_t kSQuietNanBit = 22;
89 const int64_t kSQuietNanMask = 0x1LL << kSQuietNanBit;
90 const int64_t kByteMask = 0xffL;
91 const int64_t kHalfWordMask = 0xffffL;
92 const int64_t kWordMask = 0xffffffffL;
93 const uint64_t kXMaxUInt = 0xffffffffffffffffUL;
94 const uint64_t kWMaxUInt = 0xffffffffUL;
95 const int64_t kXMaxInt = 0x7fffffffffffffffL;
96 const int64_t kXMinInt = 0x8000000000000000L;
97 const int32_t kWMaxInt = 0x7fffffff;
98 const int32_t kWMinInt = 0x80000000;
99 const int kIp0Code = 16;
100 const int kIp1Code = 17;
101 const int kFramePointerRegCode = 29;
102 const int kLinkRegCode = 30;
103 const int kZeroRegCode = 31;
104 const int kSPRegInternalCode = 63;
105 const unsigned kRegCodeMask = 0x1f;
106 const unsigned kShiftAmountWRegMask = 0x1f;
107 const unsigned kShiftAmountXRegMask = 0x3f;
108 // Standard machine types defined by AAPCS64.
109 const unsigned kHalfWordSize = 16;
110 const unsigned kHalfWordSizeLog2 = 4;
111 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3;
112 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3;
113 const unsigned kWordSize = 32;
114 const unsigned kWordSizeLog2 = 5;
115 const unsigned kWordSizeInBytes = kWordSize >> 3;
116 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3;
117 const unsigned kDoubleWordSize = 64;
118 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
119 const unsigned kQuadWordSize = 128;
120 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
121 const int kMaxLanesPerVector = 16;
122
123 const unsigned kAddressTagOffset = 56;
124 const unsigned kAddressTagWidth = 8;
125 const uint64_t kAddressTagMask = ((UINT64_C(1) << kAddressTagWidth) - 1)
126 << kAddressTagOffset;
127 static_assert(kAddressTagMask == UINT64_C(0xff00000000000000),
128 "AddressTagMask must represent most-significant eight bits.");
129
130 const uint64_t kTTBRMask = UINT64_C(1) << 55;
131
132 // AArch64 floating-point specifics. These match IEEE-754.
133 const unsigned kDoubleMantissaBits = 52;
134 const unsigned kDoubleExponentBits = 11;
135 const unsigned kDoubleExponentBias = 1023;
136 const unsigned kFloatMantissaBits = 23;
137 const unsigned kFloatExponentBits = 8;
138 const unsigned kFloatExponentBias = 127;
139 const unsigned kFloat16MantissaBits = 10;
140 const unsigned kFloat16ExponentBits = 5;
141 const unsigned kFloat16ExponentBias = 15;
142
143 // Actual value of root register is offset from the root array's start
144 // to take advantage of negative displacement values.
145 // TODO(sigurds): Choose best value.
146 // TODO(ishell): Choose best value for ptr-compr.
147 constexpr int kRootRegisterBias = kSystemPointerSize == kTaggedSize ? 256 : 0;
148
149 using float16 = uint16_t;
150
151 #define INSTRUCTION_FIELDS_LIST(V_) \
152 /* Register fields */ \
153 V_(Rd, 4, 0, Bits) /* Destination register. */ \
154 V_(Rn, 9, 5, Bits) /* First source register. */ \
155 V_(Rm, 20, 16, Bits) /* Second source register. */ \
156 V_(Ra, 14, 10, Bits) /* Third source register. */ \
157 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
158 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
159 /* store second source. */ \
160 V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \
161 V_(PrefetchMode, 4, 0, Bits) \
162 \
163 /* Common bits */ \
164 V_(SixtyFourBits, 31, 31, Bits) \
165 V_(FlagsUpdate, 29, 29, Bits) \
166 \
167 /* PC relative addressing */ \
168 V_(ImmPCRelHi, 23, 5, SignedBits) \
169 V_(ImmPCRelLo, 30, 29, Bits) \
170 \
171 /* Add/subtract/logical shift register */ \
172 V_(ShiftDP, 23, 22, Bits) \
173 V_(ImmDPShift, 15, 10, Bits) \
174 \
175 /* Add/subtract immediate */ \
176 V_(ImmAddSub, 21, 10, Bits) \
177 V_(ShiftAddSub, 23, 22, Bits) \
178 \
179 /* Add/subtract extend */ \
180 V_(ImmExtendShift, 12, 10, Bits) \
181 V_(ExtendMode, 15, 13, Bits) \
182 \
183 /* Move wide */ \
184 V_(ImmMoveWide, 20, 5, Bits) \
185 V_(ShiftMoveWide, 22, 21, Bits) \
186 \
187 /* Logical immediate, bitfield and extract */ \
188 V_(BitN, 22, 22, Bits) \
189 V_(ImmRotate, 21, 16, Bits) \
190 V_(ImmSetBits, 15, 10, Bits) \
191 V_(ImmR, 21, 16, Bits) \
192 V_(ImmS, 15, 10, Bits) \
193 \
194 /* Test and branch immediate */ \
195 V_(ImmTestBranch, 18, 5, SignedBits) \
196 V_(ImmTestBranchBit40, 23, 19, Bits) \
197 V_(ImmTestBranchBit5, 31, 31, Bits) \
198 \
199 /* Conditionals */ \
200 V_(Condition, 15, 12, Bits) \
201 V_(ConditionBranch, 3, 0, Bits) \
202 V_(Nzcv, 3, 0, Bits) \
203 V_(ImmCondCmp, 20, 16, Bits) \
204 V_(ImmCondBranch, 23, 5, SignedBits) \
205 \
206 /* Floating point */ \
207 V_(FPType, 23, 22, Bits) \
208 V_(ImmFP, 20, 13, Bits) \
209 V_(FPScale, 15, 10, Bits) \
210 \
211 /* Load Store */ \
212 V_(ImmLS, 20, 12, SignedBits) \
213 V_(ImmLSUnsigned, 21, 10, Bits) \
214 V_(ImmLSPair, 21, 15, SignedBits) \
215 V_(ImmShiftLS, 12, 12, Bits) \
216 V_(LSOpc, 23, 22, Bits) \
217 V_(LSVector, 26, 26, Bits) \
218 V_(LSSize, 31, 30, Bits) \
219 \
220 /* NEON generic fields */ \
221 V_(NEONQ, 30, 30, Bits) \
222 V_(NEONSize, 23, 22, Bits) \
223 V_(NEONLSSize, 11, 10, Bits) \
224 V_(NEONS, 12, 12, Bits) \
225 V_(NEONL, 21, 21, Bits) \
226 V_(NEONM, 20, 20, Bits) \
227 V_(NEONH, 11, 11, Bits) \
228 V_(ImmNEONExt, 14, 11, Bits) \
229 V_(ImmNEON5, 20, 16, Bits) \
230 V_(ImmNEON4, 14, 11, Bits) \
231 \
232 /* Other immediates */ \
233 V_(ImmUncondBranch, 25, 0, SignedBits) \
234 V_(ImmCmpBranch, 23, 5, SignedBits) \
235 V_(ImmLLiteral, 23, 5, SignedBits) \
236 V_(ImmException, 20, 5, Bits) \
237 V_(ImmHint, 11, 5, Bits) \
238 V_(ImmBarrierDomain, 11, 10, Bits) \
239 V_(ImmBarrierType, 9, 8, Bits) \
240 \
241 /* System (MRS, MSR) */ \
242 V_(ImmSystemRegister, 19, 5, Bits) \
243 V_(SysO0, 19, 19, Bits) \
244 V_(SysOp1, 18, 16, Bits) \
245 V_(SysOp2, 7, 5, Bits) \
246 V_(CRn, 15, 12, Bits) \
247 V_(CRm, 11, 8, Bits) \
248 \
249 /* Load-/store-exclusive */ \
250 V_(LoadStoreXLoad, 22, 22, Bits) \
251 V_(LoadStoreXNotExclusive, 23, 23, Bits) \
252 V_(LoadStoreXAcquireRelease, 15, 15, Bits) \
253 V_(LoadStoreXSizeLog2, 31, 30, Bits) \
254 V_(LoadStoreXPair, 21, 21, Bits) \
255 \
256 /* NEON load/store */ \
257 V_(NEONLoad, 22, 22, Bits) \
258 \
259 /* NEON Modified Immediate fields */ \
260 V_(ImmNEONabc, 18, 16, Bits) \
261 V_(ImmNEONdefgh, 9, 5, Bits) \
262 V_(NEONModImmOp, 29, 29, Bits) \
263 V_(NEONCmode, 15, 12, Bits) \
264 \
265 /* NEON Shift Immediate fields */ \
266 V_(ImmNEONImmhImmb, 22, 16, Bits) \
267 V_(ImmNEONImmh, 22, 19, Bits) \
268 V_(ImmNEONImmb, 18, 16, Bits)
269
270 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
271 /* NZCV */ \
272 V_(Flags, 31, 28, Bits, uint32_t) \
273 V_(N, 31, 31, Bits, bool) \
274 V_(Z, 30, 30, Bits, bool) \
275 V_(C, 29, 29, Bits, bool) \
276 V_(V, 28, 28, Bits, bool) \
277 M_(NZCV, Flags_mask) \
278 \
279 /* FPCR */ \
280 V_(AHP, 26, 26, Bits, bool) \
281 V_(DN, 25, 25, Bits, bool) \
282 V_(FZ, 24, 24, Bits, bool) \
283 V_(RMode, 23, 22, Bits, FPRounding) \
284 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
285
286 // Fields offsets.
287 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \
288 const int Name##_offset = LowBit; \
289 const int Name##_width = HighBit - LowBit + 1; \
290 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
291 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \
292 DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2)
293 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS)
294 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
295 #undef DECLARE_FIELDS_OFFSETS
296 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS
297
298 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
299 // from ImmPCRelLo and ImmPCRelHi.
300 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
301
302 // Condition codes.
303 enum Condition {
304 eq = 0,
305 ne = 1,
306 hs = 2,
307 cs = hs,
308 lo = 3,
309 cc = lo,
310 mi = 4,
311 pl = 5,
312 vs = 6,
313 vc = 7,
314 hi = 8,
315 ls = 9,
316 ge = 10,
317 lt = 11,
318 gt = 12,
319 le = 13,
320 al = 14,
321 nv = 15 // Behaves as always/al.
322 };
323
NegateCondition(Condition cond)324 inline Condition NegateCondition(Condition cond) {
325 // Conditions al and nv behave identically, as "always true". They can't be
326 // inverted, because there is no never condition.
327 DCHECK((cond != al) && (cond != nv));
328 return static_cast<Condition>(cond ^ 1);
329 }
330
331 enum FlagsUpdate { SetFlags = 1, LeaveFlags = 0 };
332
333 enum StatusFlags {
334 NoFlag = 0,
335
336 // Derive the flag combinations from the system register bit descriptions.
337 NFlag = N_mask,
338 ZFlag = Z_mask,
339 CFlag = C_mask,
340 VFlag = V_mask,
341 NZFlag = NFlag | ZFlag,
342 NCFlag = NFlag | CFlag,
343 NVFlag = NFlag | VFlag,
344 ZCFlag = ZFlag | CFlag,
345 ZVFlag = ZFlag | VFlag,
346 CVFlag = CFlag | VFlag,
347 NZCFlag = NFlag | ZFlag | CFlag,
348 NZVFlag = NFlag | ZFlag | VFlag,
349 NCVFlag = NFlag | CFlag | VFlag,
350 ZCVFlag = ZFlag | CFlag | VFlag,
351 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
352
353 // Floating-point comparison results.
354 FPEqualFlag = ZCFlag,
355 FPLessThanFlag = NFlag,
356 FPGreaterThanFlag = CFlag,
357 FPUnorderedFlag = CVFlag
358 };
359
360 enum Shift {
361 NO_SHIFT = -1,
362 LSL = 0x0,
363 LSR = 0x1,
364 ASR = 0x2,
365 ROR = 0x3,
366 MSL = 0x4
367 };
368
369 enum Extend {
370 NO_EXTEND = -1,
371 UXTB = 0,
372 UXTH = 1,
373 UXTW = 2,
374 UXTX = 3,
375 SXTB = 4,
376 SXTH = 5,
377 SXTW = 6,
378 SXTX = 7
379 };
380
381 enum SystemHint {
382 NOP = 0,
383 YIELD = 1,
384 WFE = 2,
385 WFI = 3,
386 SEV = 4,
387 SEVL = 5,
388 CSDB = 20,
389 BTI = 32,
390 BTI_c = 34,
391 BTI_j = 36,
392 BTI_jc = 38
393 };
394
395 // In a guarded page, only BTI and PACI[AB]SP instructions are allowed to be
396 // the target of indirect branches. Details on which kinds of branches each
397 // instruction allows follow in the comments below:
398 enum class BranchTargetIdentifier {
399 // Do not emit a BTI instruction.
400 kNone,
401
402 // Emit a BTI instruction. Cannot be the target of indirect jumps/calls.
403 kBti,
404
405 // Emit a "BTI c" instruction. Can be the target of indirect jumps (BR) with
406 // x16/x17 as the target register, or indirect calls (BLR).
407 kBtiCall,
408
409 // Emit a "BTI j" instruction. Can be the target of indirect jumps (BR).
410 kBtiJump,
411
412 // Emit a "BTI jc" instruction, which is a combination of "BTI j" and "BTI c".
413 kBtiJumpCall,
414
415 // Emit a PACIBSP instruction, which acts like a "BTI c" or a "BTI jc",
416 // based on the value of SCTLR_EL1.BT0.
417 kPacibsp
418 };
419
420 enum BarrierDomain {
421 OuterShareable = 0,
422 NonShareable = 1,
423 InnerShareable = 2,
424 FullSystem = 3
425 };
426
427 enum BarrierType {
428 BarrierOther = 0,
429 BarrierReads = 1,
430 BarrierWrites = 2,
431 BarrierAll = 3
432 };
433
434 // System/special register names.
435 // This information is not encoded as one field but as the concatenation of
436 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2).
437 enum SystemRegister {
438 NZCV = ((0x1 << SysO0_offset) | (0x3 << SysOp1_offset) | (0x4 << CRn_offset) |
439 (0x2 << CRm_offset) | (0x0 << SysOp2_offset)) >>
440 ImmSystemRegister_offset,
441 FPCR = ((0x1 << SysO0_offset) | (0x3 << SysOp1_offset) | (0x4 << CRn_offset) |
442 (0x4 << CRm_offset) | (0x0 << SysOp2_offset)) >>
443 ImmSystemRegister_offset
444 };
445
446 // Instruction enumerations.
447 //
448 // These are the masks that define a class of instructions, and the list of
449 // instructions within each class. Each enumeration has a Fixed, FMask and
450 // Mask value.
451 //
452 // Fixed: The fixed bits in this instruction class.
453 // FMask: The mask used to extract the fixed bits in the class.
454 // Mask: The mask used to identify the instructions within a class.
455 //
456 // The enumerations can be used like this:
457 //
458 // DCHECK(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
459 // switch(instr->Mask(PCRelAddressingMask)) {
460 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
461 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
462 // default: printf("Unknown instruction\n");
463 // }
464
465 // Used to corrupt encodings by setting all bits when orred. Although currently
466 // unallocated in AArch64, this encoding is not guaranteed to be undefined
467 // indefinitely.
468 const uint32_t kUnallocatedInstruction = 0xffffffff;
469
470 // Generic fields.
471 enum GenericInstrField : uint32_t {
472 SixtyFourBits = 0x80000000,
473 ThirtyTwoBits = 0x00000000,
474 FP32 = 0x00000000,
475 FP64 = 0x00400000
476 };
477
478 enum NEONFormatField : uint32_t {
479 NEONFormatFieldMask = 0x40C00000,
480 NEON_Q = 0x40000000,
481 NEON_8B = 0x00000000,
482 NEON_16B = NEON_8B | NEON_Q,
483 NEON_4H = 0x00400000,
484 NEON_8H = NEON_4H | NEON_Q,
485 NEON_2S = 0x00800000,
486 NEON_4S = NEON_2S | NEON_Q,
487 NEON_1D = 0x00C00000,
488 NEON_2D = 0x00C00000 | NEON_Q
489 };
490
491 enum NEONFPFormatField : uint32_t {
492 NEONFPFormatFieldMask = 0x40400000,
493 NEON_FP_2S = FP32,
494 NEON_FP_4S = FP32 | NEON_Q,
495 NEON_FP_2D = FP64 | NEON_Q
496 };
497
498 enum NEONLSFormatField : uint32_t {
499 NEONLSFormatFieldMask = 0x40000C00,
500 LS_NEON_8B = 0x00000000,
501 LS_NEON_16B = LS_NEON_8B | NEON_Q,
502 LS_NEON_4H = 0x00000400,
503 LS_NEON_8H = LS_NEON_4H | NEON_Q,
504 LS_NEON_2S = 0x00000800,
505 LS_NEON_4S = LS_NEON_2S | NEON_Q,
506 LS_NEON_1D = 0x00000C00,
507 LS_NEON_2D = LS_NEON_1D | NEON_Q
508 };
509
510 enum NEONScalarFormatField : uint32_t {
511 NEONScalarFormatFieldMask = 0x00C00000,
512 NEONScalar = 0x10000000,
513 NEON_B = 0x00000000,
514 NEON_H = 0x00400000,
515 NEON_S = 0x00800000,
516 NEON_D = 0x00C00000
517 };
518
519 // PC relative addressing.
520 enum PCRelAddressingOp : uint32_t {
521 PCRelAddressingFixed = 0x10000000,
522 PCRelAddressingFMask = 0x1F000000,
523 PCRelAddressingMask = 0x9F000000,
524 ADR = PCRelAddressingFixed | 0x00000000,
525 ADRP = PCRelAddressingFixed | 0x80000000
526 };
527
528 // Add/sub (immediate, shifted and extended.)
529 const int kSFOffset = 31;
530 enum AddSubOp : uint32_t {
531 AddSubOpMask = 0x60000000,
532 AddSubSetFlagsBit = 0x20000000,
533 ADD = 0x00000000,
534 ADDS = ADD | AddSubSetFlagsBit,
535 SUB = 0x40000000,
536 SUBS = SUB | AddSubSetFlagsBit
537 };
538
539 #define ADD_SUB_OP_LIST(V) V(ADD), V(ADDS), V(SUB), V(SUBS)
540
541 enum AddSubImmediateOp : uint32_t {
542 AddSubImmediateFixed = 0x11000000,
543 AddSubImmediateFMask = 0x1F000000,
544 AddSubImmediateMask = 0xFF000000,
545 #define ADD_SUB_IMMEDIATE(A) \
546 A##_w_imm = AddSubImmediateFixed | A, \
547 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
548 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
549 #undef ADD_SUB_IMMEDIATE
550 };
551
552 enum AddSubShiftedOp : uint32_t {
553 AddSubShiftedFixed = 0x0B000000,
554 AddSubShiftedFMask = 0x1F200000,
555 AddSubShiftedMask = 0xFF200000,
556 #define ADD_SUB_SHIFTED(A) \
557 A##_w_shift = AddSubShiftedFixed | A, \
558 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
559 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
560 #undef ADD_SUB_SHIFTED
561 };
562
563 enum AddSubExtendedOp : uint32_t {
564 AddSubExtendedFixed = 0x0B200000,
565 AddSubExtendedFMask = 0x1F200000,
566 AddSubExtendedMask = 0xFFE00000,
567 #define ADD_SUB_EXTENDED(A) \
568 A##_w_ext = AddSubExtendedFixed | A, \
569 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
570 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
571 #undef ADD_SUB_EXTENDED
572 };
573
574 // Add/sub with carry.
575 enum AddSubWithCarryOp : uint32_t {
576 AddSubWithCarryFixed = 0x1A000000,
577 AddSubWithCarryFMask = 0x1FE00000,
578 AddSubWithCarryMask = 0xFFE0FC00,
579 ADC_w = AddSubWithCarryFixed | ADD,
580 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
581 ADC = ADC_w,
582 ADCS_w = AddSubWithCarryFixed | ADDS,
583 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
584 SBC_w = AddSubWithCarryFixed | SUB,
585 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
586 SBC = SBC_w,
587 SBCS_w = AddSubWithCarryFixed | SUBS,
588 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
589 };
590
591 // Logical (immediate and shifted register).
592 enum LogicalOp : uint32_t {
593 LogicalOpMask = 0x60200000,
594 NOT = 0x00200000,
595 AND = 0x00000000,
596 BIC = AND | NOT,
597 ORR = 0x20000000,
598 ORN = ORR | NOT,
599 EOR = 0x40000000,
600 EON = EOR | NOT,
601 ANDS = 0x60000000,
602 BICS = ANDS | NOT
603 };
604
605 // Logical immediate.
606 enum LogicalImmediateOp : uint32_t {
607 LogicalImmediateFixed = 0x12000000,
608 LogicalImmediateFMask = 0x1F800000,
609 LogicalImmediateMask = 0xFF800000,
610 AND_w_imm = LogicalImmediateFixed | AND,
611 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
612 ORR_w_imm = LogicalImmediateFixed | ORR,
613 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
614 EOR_w_imm = LogicalImmediateFixed | EOR,
615 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
616 ANDS_w_imm = LogicalImmediateFixed | ANDS,
617 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
618 };
619
620 // Logical shifted register.
621 enum LogicalShiftedOp : uint32_t {
622 LogicalShiftedFixed = 0x0A000000,
623 LogicalShiftedFMask = 0x1F000000,
624 LogicalShiftedMask = 0xFF200000,
625 AND_w = LogicalShiftedFixed | AND,
626 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
627 AND_shift = AND_w,
628 BIC_w = LogicalShiftedFixed | BIC,
629 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
630 BIC_shift = BIC_w,
631 ORR_w = LogicalShiftedFixed | ORR,
632 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
633 ORR_shift = ORR_w,
634 ORN_w = LogicalShiftedFixed | ORN,
635 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
636 ORN_shift = ORN_w,
637 EOR_w = LogicalShiftedFixed | EOR,
638 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
639 EOR_shift = EOR_w,
640 EON_w = LogicalShiftedFixed | EON,
641 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
642 EON_shift = EON_w,
643 ANDS_w = LogicalShiftedFixed | ANDS,
644 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
645 ANDS_shift = ANDS_w,
646 BICS_w = LogicalShiftedFixed | BICS,
647 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
648 BICS_shift = BICS_w
649 };
650
651 // Move wide immediate.
652 enum MoveWideImmediateOp : uint32_t {
653 MoveWideImmediateFixed = 0x12800000,
654 MoveWideImmediateFMask = 0x1F800000,
655 MoveWideImmediateMask = 0xFF800000,
656 MOVN = 0x00000000,
657 MOVZ = 0x40000000,
658 MOVK = 0x60000000,
659 MOVN_w = MoveWideImmediateFixed | MOVN,
660 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
661 MOVZ_w = MoveWideImmediateFixed | MOVZ,
662 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
663 MOVK_w = MoveWideImmediateFixed | MOVK,
664 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
665 };
666
667 // Bitfield.
668 const int kBitfieldNOffset = 22;
669 enum BitfieldOp : uint32_t {
670 BitfieldFixed = 0x13000000,
671 BitfieldFMask = 0x1F800000,
672 BitfieldMask = 0xFF800000,
673 SBFM_w = BitfieldFixed | 0x00000000,
674 SBFM_x = BitfieldFixed | 0x80000000,
675 SBFM = SBFM_w,
676 BFM_w = BitfieldFixed | 0x20000000,
677 BFM_x = BitfieldFixed | 0xA0000000,
678 BFM = BFM_w,
679 UBFM_w = BitfieldFixed | 0x40000000,
680 UBFM_x = BitfieldFixed | 0xC0000000,
681 UBFM = UBFM_w
682 // Bitfield N field.
683 };
684
685 // Extract.
686 enum ExtractOp : uint32_t {
687 ExtractFixed = 0x13800000,
688 ExtractFMask = 0x1F800000,
689 ExtractMask = 0xFFA00000,
690 EXTR_w = ExtractFixed | 0x00000000,
691 EXTR_x = ExtractFixed | 0x80000000,
692 EXTR = EXTR_w
693 };
694
695 // Unconditional branch.
696 enum UnconditionalBranchOp : uint32_t {
697 UnconditionalBranchFixed = 0x14000000,
698 UnconditionalBranchFMask = 0x7C000000,
699 UnconditionalBranchMask = 0xFC000000,
700 B = UnconditionalBranchFixed | 0x00000000,
701 BL = UnconditionalBranchFixed | 0x80000000
702 };
703
704 // Unconditional branch to register.
705 enum UnconditionalBranchToRegisterOp : uint32_t {
706 UnconditionalBranchToRegisterFixed = 0xD6000000,
707 UnconditionalBranchToRegisterFMask = 0xFE000000,
708 UnconditionalBranchToRegisterMask = 0xFFFFFC1F,
709 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
710 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
711 RET = UnconditionalBranchToRegisterFixed | 0x005F0000
712 };
713
714 // Compare and branch.
715 enum CompareBranchOp : uint32_t {
716 CompareBranchFixed = 0x34000000,
717 CompareBranchFMask = 0x7E000000,
718 CompareBranchMask = 0xFF000000,
719 CBZ_w = CompareBranchFixed | 0x00000000,
720 CBZ_x = CompareBranchFixed | 0x80000000,
721 CBZ = CBZ_w,
722 CBNZ_w = CompareBranchFixed | 0x01000000,
723 CBNZ_x = CompareBranchFixed | 0x81000000,
724 CBNZ = CBNZ_w
725 };
726
727 // Test and branch.
728 enum TestBranchOp : uint32_t {
729 TestBranchFixed = 0x36000000,
730 TestBranchFMask = 0x7E000000,
731 TestBranchMask = 0x7F000000,
732 TBZ = TestBranchFixed | 0x00000000,
733 TBNZ = TestBranchFixed | 0x01000000
734 };
735
736 // Conditional branch.
737 enum ConditionalBranchOp : uint32_t {
738 ConditionalBranchFixed = 0x54000000,
739 ConditionalBranchFMask = 0xFE000000,
740 ConditionalBranchMask = 0xFF000010,
741 B_cond = ConditionalBranchFixed | 0x00000000
742 };
743
744 // System.
745 // System instruction encoding is complicated because some instructions use op
746 // and CR fields to encode parameters. To handle this cleanly, the system
747 // instructions are split into more than one enum.
748
749 enum SystemOp : uint32_t { SystemFixed = 0xD5000000, SystemFMask = 0xFFC00000 };
750
751 enum SystemSysRegOp : uint32_t {
752 SystemSysRegFixed = 0xD5100000,
753 SystemSysRegFMask = 0xFFD00000,
754 SystemSysRegMask = 0xFFF00000,
755 MRS = SystemSysRegFixed | 0x00200000,
756 MSR = SystemSysRegFixed | 0x00000000
757 };
758
759 enum SystemHintOp : uint32_t {
760 SystemHintFixed = 0xD503201F,
761 SystemHintFMask = 0xFFFFF01F,
762 SystemHintMask = 0xFFFFF01F,
763 HINT = SystemHintFixed | 0x00000000
764 };
765
766 // Exception.
767 enum ExceptionOp : uint32_t {
768 ExceptionFixed = 0xD4000000,
769 ExceptionFMask = 0xFF000000,
770 ExceptionMask = 0xFFE0001F,
771 HLT = ExceptionFixed | 0x00400000,
772 BRK = ExceptionFixed | 0x00200000,
773 SVC = ExceptionFixed | 0x00000001,
774 HVC = ExceptionFixed | 0x00000002,
775 SMC = ExceptionFixed | 0x00000003,
776 DCPS1 = ExceptionFixed | 0x00A00001,
777 DCPS2 = ExceptionFixed | 0x00A00002,
778 DCPS3 = ExceptionFixed | 0x00A00003
779 };
780 // Code used to spot hlt instructions that should not be hit.
781 const int kHltBadCode = 0xbad;
782
783 enum MemBarrierOp : uint32_t {
784 MemBarrierFixed = 0xD503309F,
785 MemBarrierFMask = 0xFFFFF09F,
786 MemBarrierMask = 0xFFFFF0FF,
787 DSB = MemBarrierFixed | 0x00000000,
788 DMB = MemBarrierFixed | 0x00000020,
789 ISB = MemBarrierFixed | 0x00000040
790 };
791
792 enum SystemPAuthOp : uint32_t {
793 SystemPAuthFixed = 0xD503211F,
794 SystemPAuthFMask = 0xFFFFFD1F,
795 SystemPAuthMask = 0xFFFFFFFF,
796 PACIB1716 = SystemPAuthFixed | 0x00000140,
797 AUTIB1716 = SystemPAuthFixed | 0x000001C0,
798 PACIBSP = SystemPAuthFixed | 0x00000360,
799 AUTIBSP = SystemPAuthFixed | 0x000003E0
800 };
801
802 // Any load or store (including pair).
803 enum LoadStoreAnyOp : uint32_t {
804 LoadStoreAnyFMask = 0x0a000000,
805 LoadStoreAnyFixed = 0x08000000
806 };
807
808 // Any load pair or store pair.
809 enum LoadStorePairAnyOp : uint32_t {
810 LoadStorePairAnyFMask = 0x3a000000,
811 LoadStorePairAnyFixed = 0x28000000
812 };
813
814 #define LOAD_STORE_PAIR_OP_LIST(V) \
815 V(STP, w, 0x00000000) \
816 , V(LDP, w, 0x00400000), V(LDPSW, x, 0x40400000), V(STP, x, 0x80000000), \
817 V(LDP, x, 0x80400000), V(STP, s, 0x04000000), V(LDP, s, 0x04400000), \
818 V(STP, d, 0x44000000), V(LDP, d, 0x44400000), V(STP, q, 0x84000000), \
819 V(LDP, q, 0x84400000)
820
821 // Load/store pair (post, pre and offset.)
822 enum LoadStorePairOp : uint32_t {
823 LoadStorePairMask = 0xC4400000,
824 LoadStorePairLBit = 1 << 22,
825 #define LOAD_STORE_PAIR(A, B, C) A##_##B = C
826 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
827 #undef LOAD_STORE_PAIR
828 };
829
830 enum LoadStorePairPostIndexOp : uint32_t {
831 LoadStorePairPostIndexFixed = 0x28800000,
832 LoadStorePairPostIndexFMask = 0x3B800000,
833 LoadStorePairPostIndexMask = 0xFFC00000,
834 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
835 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
836 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
837 #undef LOAD_STORE_PAIR_POST_INDEX
838 };
839
840 enum LoadStorePairPreIndexOp : uint32_t {
841 LoadStorePairPreIndexFixed = 0x29800000,
842 LoadStorePairPreIndexFMask = 0x3B800000,
843 LoadStorePairPreIndexMask = 0xFFC00000,
844 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
845 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
846 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
847 #undef LOAD_STORE_PAIR_PRE_INDEX
848 };
849
850 enum LoadStorePairOffsetOp : uint32_t {
851 LoadStorePairOffsetFixed = 0x29000000,
852 LoadStorePairOffsetFMask = 0x3B800000,
853 LoadStorePairOffsetMask = 0xFFC00000,
854 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
855 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
856 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
857 #undef LOAD_STORE_PAIR_OFFSET
858 };
859
860 // Load literal.
861 enum LoadLiteralOp : uint32_t {
862 LoadLiteralFixed = 0x18000000,
863 LoadLiteralFMask = 0x3B000000,
864 LoadLiteralMask = 0xFF000000,
865 LDR_w_lit = LoadLiteralFixed | 0x00000000,
866 LDR_x_lit = LoadLiteralFixed | 0x40000000,
867 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
868 PRFM_lit = LoadLiteralFixed | 0xC0000000,
869 LDR_s_lit = LoadLiteralFixed | 0x04000000,
870 LDR_d_lit = LoadLiteralFixed | 0x44000000
871 };
872
873 // clang-format off
874
875 #define LOAD_STORE_OP_LIST(V) \
876 V(ST, RB, w, 0x00000000), \
877 V(ST, RH, w, 0x40000000), \
878 V(ST, R, w, 0x80000000), \
879 V(ST, R, x, 0xC0000000), \
880 V(LD, RB, w, 0x00400000), \
881 V(LD, RH, w, 0x40400000), \
882 V(LD, R, w, 0x80400000), \
883 V(LD, R, x, 0xC0400000), \
884 V(LD, RSB, x, 0x00800000), \
885 V(LD, RSH, x, 0x40800000), \
886 V(LD, RSW, x, 0x80800000), \
887 V(LD, RSB, w, 0x00C00000), \
888 V(LD, RSH, w, 0x40C00000), \
889 V(ST, R, b, 0x04000000), \
890 V(ST, R, h, 0x44000000), \
891 V(ST, R, s, 0x84000000), \
892 V(ST, R, d, 0xC4000000), \
893 V(ST, R, q, 0x04800000), \
894 V(LD, R, b, 0x04400000), \
895 V(LD, R, h, 0x44400000), \
896 V(LD, R, s, 0x84400000), \
897 V(LD, R, d, 0xC4400000), \
898 V(LD, R, q, 0x04C00000)
899
900 // clang-format on
901
902 // Load/store unscaled offset.
903 enum LoadStoreUnscaledOffsetOp : uint32_t {
904 LoadStoreUnscaledOffsetFixed = 0x38000000,
905 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
906 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
907 #define LOAD_STORE_UNSCALED(A, B, C, D) \
908 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
909 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
910 #undef LOAD_STORE_UNSCALED
911 };
912
913 // Load/store (post, pre, offset and unsigned.)
914 enum LoadStoreOp : uint32_t {
915 LoadStoreMask = 0xC4C00000,
916 #define LOAD_STORE(A, B, C, D) A##B##_##C = D
917 LOAD_STORE_OP_LIST(LOAD_STORE),
918 #undef LOAD_STORE
919 PRFM = 0xC0800000
920 };
921
922 // Load/store post index.
923 enum LoadStorePostIndex : uint32_t {
924 LoadStorePostIndexFixed = 0x38000400,
925 LoadStorePostIndexFMask = 0x3B200C00,
926 LoadStorePostIndexMask = 0xFFE00C00,
927 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
928 A##B##_##C##_post = LoadStorePostIndexFixed | D
929 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
930 #undef LOAD_STORE_POST_INDEX
931 };
932
933 // Load/store pre index.
934 enum LoadStorePreIndex : uint32_t {
935 LoadStorePreIndexFixed = 0x38000C00,
936 LoadStorePreIndexFMask = 0x3B200C00,
937 LoadStorePreIndexMask = 0xFFE00C00,
938 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
939 A##B##_##C##_pre = LoadStorePreIndexFixed | D
940 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
941 #undef LOAD_STORE_PRE_INDEX
942 };
943
944 // Load/store unsigned offset.
945 enum LoadStoreUnsignedOffset : uint32_t {
946 LoadStoreUnsignedOffsetFixed = 0x39000000,
947 LoadStoreUnsignedOffsetFMask = 0x3B000000,
948 LoadStoreUnsignedOffsetMask = 0xFFC00000,
949 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
950 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
951 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
952 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
953 #undef LOAD_STORE_UNSIGNED_OFFSET
954 };
955
956 // Load/store register offset.
957 enum LoadStoreRegisterOffset : uint32_t {
958 LoadStoreRegisterOffsetFixed = 0x38200800,
959 LoadStoreRegisterOffsetFMask = 0x3B200C00,
960 LoadStoreRegisterOffsetMask = 0xFFE00C00,
961 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
962 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
963 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
964 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
965 #undef LOAD_STORE_REGISTER_OFFSET
966 };
967
968 // Load/store acquire/release.
969 enum LoadStoreAcquireReleaseOp : uint32_t {
970 LoadStoreAcquireReleaseFixed = 0x08000000,
971 LoadStoreAcquireReleaseFMask = 0x3F000000,
972 LoadStoreAcquireReleaseMask = 0xCFC08000,
973 STLXR_b = LoadStoreAcquireReleaseFixed | 0x00008000,
974 LDAXR_b = LoadStoreAcquireReleaseFixed | 0x00408000,
975 STLR_b = LoadStoreAcquireReleaseFixed | 0x00808000,
976 LDAR_b = LoadStoreAcquireReleaseFixed | 0x00C08000,
977 STLXR_h = LoadStoreAcquireReleaseFixed | 0x40008000,
978 LDAXR_h = LoadStoreAcquireReleaseFixed | 0x40408000,
979 STLR_h = LoadStoreAcquireReleaseFixed | 0x40808000,
980 LDAR_h = LoadStoreAcquireReleaseFixed | 0x40C08000,
981 STLXR_w = LoadStoreAcquireReleaseFixed | 0x80008000,
982 LDAXR_w = LoadStoreAcquireReleaseFixed | 0x80408000,
983 STLR_w = LoadStoreAcquireReleaseFixed | 0x80808000,
984 LDAR_w = LoadStoreAcquireReleaseFixed | 0x80C08000,
985 STLXR_x = LoadStoreAcquireReleaseFixed | 0xC0008000,
986 LDAXR_x = LoadStoreAcquireReleaseFixed | 0xC0408000,
987 STLR_x = LoadStoreAcquireReleaseFixed | 0xC0808000,
988 LDAR_x = LoadStoreAcquireReleaseFixed | 0xC0C08000,
989 };
990
991 // Conditional compare.
992 enum ConditionalCompareOp : uint32_t {
993 ConditionalCompareMask = 0x60000000,
994 CCMN = 0x20000000,
995 CCMP = 0x60000000
996 };
997
998 // Conditional compare register.
999 enum ConditionalCompareRegisterOp : uint32_t {
1000 ConditionalCompareRegisterFixed = 0x1A400000,
1001 ConditionalCompareRegisterFMask = 0x1FE00800,
1002 ConditionalCompareRegisterMask = 0xFFE00C10,
1003 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1004 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1005 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1006 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1007 };
1008
1009 // Conditional compare immediate.
1010 enum ConditionalCompareImmediateOp : uint32_t {
1011 ConditionalCompareImmediateFixed = 0x1A400800,
1012 ConditionalCompareImmediateFMask = 0x1FE00800,
1013 ConditionalCompareImmediateMask = 0xFFE00C10,
1014 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1015 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1016 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1017 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1018 };
1019
1020 // Conditional select.
1021 enum ConditionalSelectOp : uint32_t {
1022 ConditionalSelectFixed = 0x1A800000,
1023 ConditionalSelectFMask = 0x1FE00000,
1024 ConditionalSelectMask = 0xFFE00C00,
1025 CSEL_w = ConditionalSelectFixed | 0x00000000,
1026 CSEL_x = ConditionalSelectFixed | 0x80000000,
1027 CSEL = CSEL_w,
1028 CSINC_w = ConditionalSelectFixed | 0x00000400,
1029 CSINC_x = ConditionalSelectFixed | 0x80000400,
1030 CSINC = CSINC_w,
1031 CSINV_w = ConditionalSelectFixed | 0x40000000,
1032 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1033 CSINV = CSINV_w,
1034 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1035 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1036 CSNEG = CSNEG_w
1037 };
1038
1039 // Data processing 1 source.
1040 enum DataProcessing1SourceOp : uint32_t {
1041 DataProcessing1SourceFixed = 0x5AC00000,
1042 DataProcessing1SourceFMask = 0x5FE00000,
1043 DataProcessing1SourceMask = 0xFFFFFC00,
1044 RBIT = DataProcessing1SourceFixed | 0x00000000,
1045 RBIT_w = RBIT,
1046 RBIT_x = RBIT | SixtyFourBits,
1047 REV16 = DataProcessing1SourceFixed | 0x00000400,
1048 REV16_w = REV16,
1049 REV16_x = REV16 | SixtyFourBits,
1050 REV = DataProcessing1SourceFixed | 0x00000800,
1051 REV_w = REV,
1052 REV32_x = REV | SixtyFourBits,
1053 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1054 CLZ = DataProcessing1SourceFixed | 0x00001000,
1055 CLZ_w = CLZ,
1056 CLZ_x = CLZ | SixtyFourBits,
1057 CLS = DataProcessing1SourceFixed | 0x00001400,
1058 CLS_w = CLS,
1059 CLS_x = CLS | SixtyFourBits
1060 };
1061
1062 // Data processing 2 source.
1063 enum DataProcessing2SourceOp : uint32_t {
1064 DataProcessing2SourceFixed = 0x1AC00000,
1065 DataProcessing2SourceFMask = 0x5FE00000,
1066 DataProcessing2SourceMask = 0xFFE0FC00,
1067 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1068 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1069 UDIV = UDIV_w,
1070 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1071 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1072 SDIV = SDIV_w,
1073 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1074 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1075 LSLV = LSLV_w,
1076 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1077 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1078 LSRV = LSRV_w,
1079 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1080 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1081 ASRV = ASRV_w,
1082 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1083 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1084 RORV = RORV_w,
1085 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1086 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1087 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1088 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1089 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1090 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1091 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1092 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1093 };
1094
1095 // Data processing 3 source.
1096 enum DataProcessing3SourceOp : uint32_t {
1097 DataProcessing3SourceFixed = 0x1B000000,
1098 DataProcessing3SourceFMask = 0x1F000000,
1099 DataProcessing3SourceMask = 0xFFE08000,
1100 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1101 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1102 MADD = MADD_w,
1103 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1104 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1105 MSUB = MSUB_w,
1106 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1107 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1108 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1109 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1110 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1111 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1112 };
1113
1114 // Floating point compare.
1115 enum FPCompareOp : uint32_t {
1116 FPCompareFixed = 0x1E202000,
1117 FPCompareFMask = 0x5F203C00,
1118 FPCompareMask = 0xFFE0FC1F,
1119 FCMP_s = FPCompareFixed | 0x00000000,
1120 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1121 FCMP = FCMP_s,
1122 FCMP_s_zero = FPCompareFixed | 0x00000008,
1123 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1124 FCMP_zero = FCMP_s_zero,
1125 FCMPE_s = FPCompareFixed | 0x00000010,
1126 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1127 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1128 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018
1129 };
1130
1131 // Floating point conditional compare.
1132 enum FPConditionalCompareOp : uint32_t {
1133 FPConditionalCompareFixed = 0x1E200400,
1134 FPConditionalCompareFMask = 0x5F200C00,
1135 FPConditionalCompareMask = 0xFFE00C10,
1136 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1137 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1138 FCCMP = FCCMP_s,
1139 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1140 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1141 FCCMPE = FCCMPE_s
1142 };
1143
1144 // Floating point conditional select.
1145 enum FPConditionalSelectOp : uint32_t {
1146 FPConditionalSelectFixed = 0x1E200C00,
1147 FPConditionalSelectFMask = 0x5F200C00,
1148 FPConditionalSelectMask = 0xFFE00C00,
1149 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1150 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1151 FCSEL = FCSEL_s
1152 };
1153
1154 // Floating point immediate.
1155 enum FPImmediateOp : uint32_t {
1156 FPImmediateFixed = 0x1E201000,
1157 FPImmediateFMask = 0x5F201C00,
1158 FPImmediateMask = 0xFFE01C00,
1159 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1160 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1161 };
1162
1163 // Floating point data processing 1 source.
1164 enum FPDataProcessing1SourceOp : uint32_t {
1165 FPDataProcessing1SourceFixed = 0x1E204000,
1166 FPDataProcessing1SourceFMask = 0x5F207C00,
1167 FPDataProcessing1SourceMask = 0xFFFFFC00,
1168 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1169 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1170 FMOV = FMOV_s,
1171 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1172 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1173 FABS = FABS_s,
1174 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1175 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1176 FNEG = FNEG_s,
1177 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1178 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1179 FSQRT = FSQRT_s,
1180 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1181 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1182 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1183 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1184 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1185 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1186 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1187 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1188 FRINTN = FRINTN_s,
1189 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1190 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1191 FRINTP = FRINTP_s,
1192 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1193 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1194 FRINTM = FRINTM_s,
1195 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1196 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1197 FRINTZ = FRINTZ_s,
1198 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1199 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1200 FRINTA = FRINTA_s,
1201 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1202 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1203 FRINTX = FRINTX_s,
1204 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1205 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1206 FRINTI = FRINTI_s
1207 };
1208
1209 // Floating point data processing 2 source.
1210 enum FPDataProcessing2SourceOp : uint32_t {
1211 FPDataProcessing2SourceFixed = 0x1E200800,
1212 FPDataProcessing2SourceFMask = 0x5F200C00,
1213 FPDataProcessing2SourceMask = 0xFFE0FC00,
1214 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1215 FMUL_s = FMUL,
1216 FMUL_d = FMUL | FP64,
1217 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1218 FDIV_s = FDIV,
1219 FDIV_d = FDIV | FP64,
1220 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1221 FADD_s = FADD,
1222 FADD_d = FADD | FP64,
1223 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1224 FSUB_s = FSUB,
1225 FSUB_d = FSUB | FP64,
1226 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1227 FMAX_s = FMAX,
1228 FMAX_d = FMAX | FP64,
1229 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1230 FMIN_s = FMIN,
1231 FMIN_d = FMIN | FP64,
1232 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1233 FMAXNM_s = FMAXNM,
1234 FMAXNM_d = FMAXNM | FP64,
1235 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1236 FMINNM_s = FMINNM,
1237 FMINNM_d = FMINNM | FP64,
1238 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1239 FNMUL_s = FNMUL,
1240 FNMUL_d = FNMUL | FP64
1241 };
1242
1243 // Floating point data processing 3 source.
1244 enum FPDataProcessing3SourceOp : uint32_t {
1245 FPDataProcessing3SourceFixed = 0x1F000000,
1246 FPDataProcessing3SourceFMask = 0x5F000000,
1247 FPDataProcessing3SourceMask = 0xFFE08000,
1248 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1249 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1250 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1251 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1252 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1253 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1254 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1255 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1256 };
1257
1258 // Conversion between floating point and integer.
1259 enum FPIntegerConvertOp : uint32_t {
1260 FPIntegerConvertFixed = 0x1E200000,
1261 FPIntegerConvertFMask = 0x5F20FC00,
1262 FPIntegerConvertMask = 0xFFFFFC00,
1263 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1264 FCVTNS_ws = FCVTNS,
1265 FCVTNS_xs = FCVTNS | SixtyFourBits,
1266 FCVTNS_wd = FCVTNS | FP64,
1267 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1268 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1269 FCVTNU_ws = FCVTNU,
1270 FCVTNU_xs = FCVTNU | SixtyFourBits,
1271 FCVTNU_wd = FCVTNU | FP64,
1272 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1273 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1274 FCVTPS_ws = FCVTPS,
1275 FCVTPS_xs = FCVTPS | SixtyFourBits,
1276 FCVTPS_wd = FCVTPS | FP64,
1277 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1278 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1279 FCVTPU_ws = FCVTPU,
1280 FCVTPU_xs = FCVTPU | SixtyFourBits,
1281 FCVTPU_wd = FCVTPU | FP64,
1282 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1283 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1284 FCVTMS_ws = FCVTMS,
1285 FCVTMS_xs = FCVTMS | SixtyFourBits,
1286 FCVTMS_wd = FCVTMS | FP64,
1287 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1288 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1289 FCVTMU_ws = FCVTMU,
1290 FCVTMU_xs = FCVTMU | SixtyFourBits,
1291 FCVTMU_wd = FCVTMU | FP64,
1292 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1293 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1294 FCVTZS_ws = FCVTZS,
1295 FCVTZS_xs = FCVTZS | SixtyFourBits,
1296 FCVTZS_wd = FCVTZS | FP64,
1297 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1298 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1299 FCVTZU_ws = FCVTZU,
1300 FCVTZU_xs = FCVTZU | SixtyFourBits,
1301 FCVTZU_wd = FCVTZU | FP64,
1302 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1303 SCVTF = FPIntegerConvertFixed | 0x00020000,
1304 SCVTF_sw = SCVTF,
1305 SCVTF_sx = SCVTF | SixtyFourBits,
1306 SCVTF_dw = SCVTF | FP64,
1307 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1308 UCVTF = FPIntegerConvertFixed | 0x00030000,
1309 UCVTF_sw = UCVTF,
1310 UCVTF_sx = UCVTF | SixtyFourBits,
1311 UCVTF_dw = UCVTF | FP64,
1312 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1313 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1314 FCVTAS_ws = FCVTAS,
1315 FCVTAS_xs = FCVTAS | SixtyFourBits,
1316 FCVTAS_wd = FCVTAS | FP64,
1317 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1318 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1319 FCVTAU_ws = FCVTAU,
1320 FCVTAU_xs = FCVTAU | SixtyFourBits,
1321 FCVTAU_wd = FCVTAU | FP64,
1322 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1323 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1324 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1325 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1326 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1327 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1328 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000,
1329 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000
1330 };
1331
1332 // Conversion between fixed point and floating point.
1333 enum FPFixedPointConvertOp : uint32_t {
1334 FPFixedPointConvertFixed = 0x1E000000,
1335 FPFixedPointConvertFMask = 0x5F200000,
1336 FPFixedPointConvertMask = 0xFFFF0000,
1337 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1338 FCVTZS_ws_fixed = FCVTZS_fixed,
1339 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1340 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1341 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1342 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1343 FCVTZU_ws_fixed = FCVTZU_fixed,
1344 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1345 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1346 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1347 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1348 SCVTF_sw_fixed = SCVTF_fixed,
1349 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1350 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1351 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1352 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1353 UCVTF_sw_fixed = UCVTF_fixed,
1354 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1355 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1356 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1357 };
1358
1359 // NEON instructions with two register operands.
1360 enum NEON2RegMiscOp : uint32_t {
1361 NEON2RegMiscFixed = 0x0E200800,
1362 NEON2RegMiscFMask = 0x9F3E0C00,
1363 NEON2RegMiscMask = 0xBF3FFC00,
1364 NEON2RegMiscUBit = 0x20000000,
1365 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1366 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1367 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1368 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1369 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1370 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1371 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1372 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1373 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1374 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1375 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1376 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1377 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1378 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1379 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1380 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1381 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1382 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1383 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1384 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1385 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1386 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1387 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1388 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1389 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1390 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1391 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1392
1393 NEON2RegMiscOpcode = 0x0001F000,
1394 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1395 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1396 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1397 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1398
1399 // These instructions use only one bit of the size field. The other bit is
1400 // used to distinguish between instructions.
1401 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1402 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1403 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1404 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1405 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1406 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1407 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1408 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1409 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1410 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1411 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1412 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1413 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1414 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1415 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1416 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1417 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1418 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1419 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1420 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1421 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1422 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1423 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1424 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1425 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1426 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1427 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1428 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1429 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1430 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1431 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1432 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1433 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1434 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1435 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1436
1437 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1438 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1439 };
1440
1441 // NEON instructions with three same-type operands.
1442 enum NEON3SameOp : uint32_t {
1443 NEON3SameFixed = 0x0E200400,
1444 NEON3SameFMask = 0x9F200400,
1445 NEON3SameMask = 0xBF20FC00,
1446 NEON3SameUBit = 0x20000000,
1447 NEON_ADD = NEON3SameFixed | 0x00008000,
1448 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1449 NEON_SHADD = NEON3SameFixed | 0x00000000,
1450 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1451 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1452 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1453 NEON_CMGE = NEON3SameFixed | 0x00003800,
1454 NEON_CMGT = NEON3SameFixed | 0x00003000,
1455 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
1456 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
1457 NEON_CMTST = NEON3SameFixed | 0x00008800,
1458 NEON_MLA = NEON3SameFixed | 0x00009000,
1459 NEON_MLS = NEON3SameFixed | 0x20009000,
1460 NEON_MUL = NEON3SameFixed | 0x00009800,
1461 NEON_PMUL = NEON3SameFixed | 0x20009800,
1462 NEON_SRSHL = NEON3SameFixed | 0x00005000,
1463 NEON_SQSHL = NEON3SameFixed | 0x00004800,
1464 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
1465 NEON_SSHL = NEON3SameFixed | 0x00004000,
1466 NEON_SMAX = NEON3SameFixed | 0x00006000,
1467 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
1468 NEON_SMIN = NEON3SameFixed | 0x00006800,
1469 NEON_SMINP = NEON3SameFixed | 0x0000A800,
1470 NEON_SABD = NEON3SameFixed | 0x00007000,
1471 NEON_SABA = NEON3SameFixed | 0x00007800,
1472 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
1473 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
1474 NEON_SQADD = NEON3SameFixed | 0x00000800,
1475 NEON_SQSUB = NEON3SameFixed | 0x00002800,
1476 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
1477 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
1478 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
1479 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
1480 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
1481 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
1482 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
1483 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
1484 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
1485 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
1486 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
1487 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
1488 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
1489 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
1490 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
1491 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
1492
1493 // NEON floating point instructions with three same-type operands.
1494 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
1495 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
1496 NEON3SameFPMask = NEON3SameMask | 0x00800000,
1497 NEON_FADD = NEON3SameFixed | 0x0000D000,
1498 NEON_FSUB = NEON3SameFixed | 0x0080D000,
1499 NEON_FMUL = NEON3SameFixed | 0x2000D800,
1500 NEON_FDIV = NEON3SameFixed | 0x2000F800,
1501 NEON_FMAX = NEON3SameFixed | 0x0000F000,
1502 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
1503 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
1504 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
1505 NEON_FMIN = NEON3SameFixed | 0x0080F000,
1506 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
1507 NEON_FMINP = NEON3SameFixed | 0x2080F000,
1508 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
1509 NEON_FMLA = NEON3SameFixed | 0x0000C800,
1510 NEON_FMLS = NEON3SameFixed | 0x0080C800,
1511 NEON_FMULX = NEON3SameFixed | 0x0000D800,
1512 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
1513 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
1514 NEON_FABD = NEON3SameFixed | 0x2080D000,
1515 NEON_FADDP = NEON3SameFixed | 0x2000D000,
1516 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
1517 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
1518 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
1519 NEON_FACGE = NEON3SameFixed | 0x2000E800,
1520 NEON_FACGT = NEON3SameFixed | 0x2080E800,
1521
1522 // NEON logical instructions with three same-type operands.
1523 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
1524 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
1525 NEON3SameLogicalMask = 0xBFE0FC00,
1526 NEON3SameLogicalFormatMask = NEON_Q,
1527 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
1528 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
1529 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
1530 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
1531 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
1532 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
1533 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
1534 NEON_BSL = NEON3SameLogicalFixed | 0x20400000
1535 };
1536
1537 // NEON instructions with three different-type operands.
1538 enum NEON3DifferentOp : uint32_t {
1539 NEON3DifferentFixed = 0x0E200000,
1540 NEON3DifferentFMask = 0x9F200C00,
1541 NEON3DifferentMask = 0xFF20FC00,
1542 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
1543 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
1544 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
1545 NEON_PMULL2 = NEON_PMULL | NEON_Q,
1546 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
1547 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
1548 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
1549 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
1550 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
1551 NEON_SABAL2 = NEON_SABAL | NEON_Q,
1552 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
1553 NEON_SABDL2 = NEON_SABDL | NEON_Q,
1554 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
1555 NEON_SADDL2 = NEON_SADDL | NEON_Q,
1556 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
1557 NEON_SADDW2 = NEON_SADDW | NEON_Q,
1558 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
1559 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
1560 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
1561 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
1562 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
1563 NEON_SMULL2 = NEON_SMULL | NEON_Q,
1564 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
1565 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
1566 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
1567 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
1568 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
1569 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
1570 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
1571 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
1572 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
1573 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
1574 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
1575 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
1576 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
1577 NEON_UABAL2 = NEON_UABAL | NEON_Q,
1578 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
1579 NEON_UABDL2 = NEON_UABDL | NEON_Q,
1580 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
1581 NEON_UADDL2 = NEON_UADDL | NEON_Q,
1582 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
1583 NEON_UADDW2 = NEON_UADDW | NEON_Q,
1584 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
1585 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
1586 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
1587 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
1588 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
1589 NEON_UMULL2 = NEON_UMULL | NEON_Q,
1590 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
1591 NEON_USUBL2 = NEON_USUBL | NEON_Q,
1592 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
1593 NEON_USUBW2 = NEON_USUBW | NEON_Q
1594 };
1595
1596 // NEON instructions operating across vectors.
1597 enum NEONAcrossLanesOp : uint32_t {
1598 NEONAcrossLanesFixed = 0x0E300800,
1599 NEONAcrossLanesFMask = 0x9F3E0C00,
1600 NEONAcrossLanesMask = 0xBF3FFC00,
1601 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
1602 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
1603 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
1604 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
1605 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
1606 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
1607 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
1608
1609 // NEON floating point across instructions.
1610 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000,
1611 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000,
1612 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000,
1613
1614 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
1615 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
1616 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
1617 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
1618 };
1619
1620 // NEON instructions with indexed element operand.
1621 enum NEONByIndexedElementOp : uint32_t {
1622 NEONByIndexedElementFixed = 0x0F000000,
1623 NEONByIndexedElementFMask = 0x9F000400,
1624 NEONByIndexedElementMask = 0xBF00F400,
1625 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
1626 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
1627 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
1628 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
1629 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
1630 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
1631 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
1632 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
1633 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
1634 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
1635 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
1636 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
1637 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
1638 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
1639
1640 // Floating point instructions.
1641 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
1642 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
1643 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
1644 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
1645 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
1646 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000
1647 };
1648
1649 // NEON modified immediate.
1650 enum NEONModifiedImmediateOp : uint32_t {
1651 NEONModifiedImmediateFixed = 0x0F000400,
1652 NEONModifiedImmediateFMask = 0x9FF80400,
1653 NEONModifiedImmediateOpBit = 0x20000000,
1654 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
1655 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
1656 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
1657 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
1658 };
1659
1660 // NEON extract.
1661 enum NEONExtractOp : uint32_t {
1662 NEONExtractFixed = 0x2E000000,
1663 NEONExtractFMask = 0xBF208400,
1664 NEONExtractMask = 0xBFE08400,
1665 NEON_EXT = NEONExtractFixed | 0x00000000
1666 };
1667
1668 enum NEONLoadStoreMultiOp : uint32_t {
1669 NEONLoadStoreMultiL = 0x00400000,
1670 NEONLoadStoreMulti1_1v = 0x00007000,
1671 NEONLoadStoreMulti1_2v = 0x0000A000,
1672 NEONLoadStoreMulti1_3v = 0x00006000,
1673 NEONLoadStoreMulti1_4v = 0x00002000,
1674 NEONLoadStoreMulti2 = 0x00008000,
1675 NEONLoadStoreMulti3 = 0x00004000,
1676 NEONLoadStoreMulti4 = 0x00000000
1677 };
1678
1679 // NEON load/store multiple structures.
1680 enum NEONLoadStoreMultiStructOp : uint32_t {
1681 NEONLoadStoreMultiStructFixed = 0x0C000000,
1682 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
1683 NEONLoadStoreMultiStructMask = 0xBFFFF000,
1684 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
1685 NEONLoadStoreMultiStructLoad =
1686 NEONLoadStoreMultiStructFixed | NEONLoadStoreMultiL,
1687 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
1688 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
1689 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
1690 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
1691 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
1692 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
1693 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
1694 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
1695 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
1696 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
1697 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
1698 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
1699 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
1700 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
1701 };
1702
1703 // NEON load/store multiple structures with post-index addressing.
1704 enum NEONLoadStoreMultiStructPostIndexOp : uint32_t {
1705 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
1706 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
1707 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
1708 NEONLoadStoreMultiStructPostIndex = 0x00800000,
1709 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
1710 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
1711 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
1712 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
1713 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
1714 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
1715 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
1716 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
1717 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
1718 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
1719 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
1720 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
1721 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
1722 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
1723 };
1724
1725 enum NEONLoadStoreSingleOp : uint32_t {
1726 NEONLoadStoreSingle1 = 0x00000000,
1727 NEONLoadStoreSingle2 = 0x00200000,
1728 NEONLoadStoreSingle3 = 0x00002000,
1729 NEONLoadStoreSingle4 = 0x00202000,
1730 NEONLoadStoreSingleL = 0x00400000,
1731 NEONLoadStoreSingle_b = 0x00000000,
1732 NEONLoadStoreSingle_h = 0x00004000,
1733 NEONLoadStoreSingle_s = 0x00008000,
1734 NEONLoadStoreSingle_d = 0x00008400,
1735 NEONLoadStoreSingleAllLanes = 0x0000C000,
1736 NEONLoadStoreSingleLenMask = 0x00202000
1737 };
1738
1739 // NEON load/store single structure.
1740 enum NEONLoadStoreSingleStructOp : uint32_t {
1741 NEONLoadStoreSingleStructFixed = 0x0D000000,
1742 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
1743 NEONLoadStoreSingleStructMask = 0xBFFFE000,
1744 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
1745 NEONLoadStoreSingleStructLoad =
1746 NEONLoadStoreSingleStructFixed | NEONLoadStoreSingleL,
1747 NEONLoadStoreSingleStructLoad1 =
1748 NEONLoadStoreSingle1 | NEONLoadStoreSingleStructLoad,
1749 NEONLoadStoreSingleStructLoad2 =
1750 NEONLoadStoreSingle2 | NEONLoadStoreSingleStructLoad,
1751 NEONLoadStoreSingleStructLoad3 =
1752 NEONLoadStoreSingle3 | NEONLoadStoreSingleStructLoad,
1753 NEONLoadStoreSingleStructLoad4 =
1754 NEONLoadStoreSingle4 | NEONLoadStoreSingleStructLoad,
1755 NEONLoadStoreSingleStructStore1 =
1756 NEONLoadStoreSingle1 | NEONLoadStoreSingleStructFixed,
1757 NEONLoadStoreSingleStructStore2 =
1758 NEONLoadStoreSingle2 | NEONLoadStoreSingleStructFixed,
1759 NEONLoadStoreSingleStructStore3 =
1760 NEONLoadStoreSingle3 | NEONLoadStoreSingleStructFixed,
1761 NEONLoadStoreSingleStructStore4 =
1762 NEONLoadStoreSingle4 | NEONLoadStoreSingleStructFixed,
1763 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
1764 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
1765 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
1766 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
1767 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
1768 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
1769 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
1770 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
1771 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
1772
1773 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
1774 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
1775 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
1776 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
1777 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
1778 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
1779 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
1780 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
1781 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
1782
1783 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
1784 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
1785 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
1786 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
1787 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
1788 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
1789 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
1790 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
1791 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
1792
1793 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
1794 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
1795 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
1796 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
1797 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
1798 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
1799 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
1800 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
1801 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
1802 };
1803
1804 // NEON load/store single structure with post-index addressing.
1805 enum NEONLoadStoreSingleStructPostIndexOp : uint32_t {
1806 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
1807 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
1808 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
1809 NEONLoadStoreSingleStructPostIndex = 0x00800000,
1810 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
1811 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
1812 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
1813 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
1814 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
1815 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
1816 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
1817 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
1818 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
1819
1820 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
1821 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
1822 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
1823 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
1824 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
1825 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
1826 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
1827 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
1828 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
1829
1830 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
1831 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
1832 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
1833 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
1834 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
1835 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
1836 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
1837 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
1838 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
1839
1840 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
1841 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
1842 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
1843 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
1844 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
1845 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
1846 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
1847 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
1848 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
1849 };
1850
1851 // NEON register copy.
1852 enum NEONCopyOp : uint32_t {
1853 NEONCopyFixed = 0x0E000400,
1854 NEONCopyFMask = 0x9FE08400,
1855 NEONCopyMask = 0x3FE08400,
1856 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
1857 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
1858 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
1859 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
1860 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
1861 NEONCopySmovMask = NEONCopyMask | 0x20007800,
1862 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
1863 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
1864 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
1865 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
1866 NEON_SMOV = NEONCopyFixed | 0x00002800,
1867 NEON_UMOV = NEONCopyFixed | 0x00003800
1868 };
1869
1870 // NEON scalar instructions with indexed element operand.
1871 enum NEONScalarByIndexedElementOp : uint32_t {
1872 NEONScalarByIndexedElementFixed = 0x5F000000,
1873 NEONScalarByIndexedElementFMask = 0xDF000400,
1874 NEONScalarByIndexedElementMask = 0xFF00F400,
1875 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
1876 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
1877 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
1878 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
1879 NEON_SQRDMULH_byelement_scalar =
1880 NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
1881
1882 // Floating point instructions.
1883 NEONScalarByIndexedElementFPFixed =
1884 NEONScalarByIndexedElementFixed | 0x00800000,
1885 NEONScalarByIndexedElementFPMask =
1886 NEONScalarByIndexedElementMask | 0x00800000,
1887 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
1888 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
1889 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
1890 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
1891 };
1892
1893 // NEON shift immediate.
1894 enum NEONShiftImmediateOp : uint32_t {
1895 NEONShiftImmediateFixed = 0x0F000400,
1896 NEONShiftImmediateFMask = 0x9F800400,
1897 NEONShiftImmediateMask = 0xBF80FC00,
1898 NEONShiftImmediateUBit = 0x20000000,
1899 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
1900 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
1901 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
1902 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
1903 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
1904 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
1905 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
1906 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
1907 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
1908 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
1909 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
1910 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
1911 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
1912 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
1913 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
1914 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
1915 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
1916 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
1917 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
1918 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
1919 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
1920 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
1921 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
1922 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
1923 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
1924 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
1925 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
1926 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
1927 };
1928
1929 // NEON scalar register copy.
1930 enum NEONScalarCopyOp : uint32_t {
1931 NEONScalarCopyFixed = 0x5E000400,
1932 NEONScalarCopyFMask = 0xDFE08400,
1933 NEONScalarCopyMask = 0xFFE0FC00,
1934 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
1935 };
1936
1937 // NEON scalar pairwise instructions.
1938 enum NEONScalarPairwiseOp : uint32_t {
1939 NEONScalarPairwiseFixed = 0x5E300800,
1940 NEONScalarPairwiseFMask = 0xDF3E0C00,
1941 NEONScalarPairwiseMask = 0xFFB1F800,
1942 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
1943 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
1944 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
1945 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
1946 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
1947 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
1948 };
1949
1950 // NEON scalar shift immediate.
1951 enum NEONScalarShiftImmediateOp : uint32_t {
1952 NEONScalarShiftImmediateFixed = 0x5F000400,
1953 NEONScalarShiftImmediateFMask = 0xDF800400,
1954 NEONScalarShiftImmediateMask = 0xFF80FC00,
1955 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
1956 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
1957 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
1958 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
1959 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
1960 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
1961 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
1962 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
1963 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
1964 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
1965 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
1966 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
1967 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
1968 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
1969 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
1970 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
1971 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
1972 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
1973 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
1974 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
1975 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
1976 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
1977 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
1978 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
1979 };
1980
1981 // NEON table.
1982 enum NEONTableOp : uint32_t {
1983 NEONTableFixed = 0x0E000000,
1984 NEONTableFMask = 0xBF208C00,
1985 NEONTableExt = 0x00001000,
1986 NEONTableMask = 0xBF20FC00,
1987 NEON_TBL_1v = NEONTableFixed | 0x00000000,
1988 NEON_TBL_2v = NEONTableFixed | 0x00002000,
1989 NEON_TBL_3v = NEONTableFixed | 0x00004000,
1990 NEON_TBL_4v = NEONTableFixed | 0x00006000,
1991 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
1992 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
1993 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
1994 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
1995 };
1996
1997 // NEON perm.
1998 enum NEONPermOp : uint32_t {
1999 NEONPermFixed = 0x0E000800,
2000 NEONPermFMask = 0xBF208C00,
2001 NEONPermMask = 0x3F20FC00,
2002 NEON_UZP1 = NEONPermFixed | 0x00001000,
2003 NEON_TRN1 = NEONPermFixed | 0x00002000,
2004 NEON_ZIP1 = NEONPermFixed | 0x00003000,
2005 NEON_UZP2 = NEONPermFixed | 0x00005000,
2006 NEON_TRN2 = NEONPermFixed | 0x00006000,
2007 NEON_ZIP2 = NEONPermFixed | 0x00007000
2008 };
2009
2010 // NEON scalar instructions with two register operands.
2011 enum NEONScalar2RegMiscOp : uint32_t {
2012 NEONScalar2RegMiscFixed = 0x5E200800,
2013 NEONScalar2RegMiscFMask = 0xDF3E0C00,
2014 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
2015 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
2016 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
2017 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
2018 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
2019 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
2020 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
2021 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
2022 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
2023 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
2024 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2025 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2026 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2027 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2028 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2029
2030 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2031 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2032
2033 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2034 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2035 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2036 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2037 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2038 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2039 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2040 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2041 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2042 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2043 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2044 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2045 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2046 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2047 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2048 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2049 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2050 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2051 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2052 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2053 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2054 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2055 };
2056
2057 // NEON scalar instructions with three same-type operands.
2058 enum NEONScalar3SameOp : uint32_t {
2059 NEONScalar3SameFixed = 0x5E200400,
2060 NEONScalar3SameFMask = 0xDF200400,
2061 NEONScalar3SameMask = 0xFF20FC00,
2062 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2063 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2064 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2065 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2066 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2067 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2068 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2069 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2070 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2071 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2072 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2073 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2074 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2075 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2076 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2077 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2078 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2079 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2080 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2081 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2082 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2083 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2084
2085 // NEON floating point scalar instructions with three same-type operands.
2086 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2087 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2088 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2089 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2090 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2091 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2092 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2093 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2094 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2095 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2096 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2097 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2098 };
2099
2100 // NEON scalar instructions with three different-type operands.
2101 enum NEONScalar3DiffOp : uint32_t {
2102 NEONScalar3DiffFixed = 0x5E200000,
2103 NEONScalar3DiffFMask = 0xDF200C00,
2104 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2105 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2106 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2107 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2108 };
2109
2110 // Unimplemented and unallocated instructions. These are defined to make fixed
2111 // bit assertion easier.
2112 enum UnimplementedOp : uint32_t {
2113 UnimplementedFixed = 0x00000000,
2114 UnimplementedFMask = 0x00000000
2115 };
2116
2117 enum UnallocatedOp : uint32_t {
2118 UnallocatedFixed = 0x00000000,
2119 UnallocatedFMask = 0x00000000
2120 };
2121
2122 } // namespace internal
2123 } // namespace v8
2124
2125 #endif // V8_CODEGEN_ARM64_CONSTANTS_ARM64_H_
2126