1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cortina CS4315/CS4340 10G PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 *
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <malloc.h>
13 #include <linux/ctype.h>
14 #include <linux/string.h>
15 #include <linux/err.h>
16 #include <phy.h>
17 #include <cortina.h>
18 #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
19 #include <nand.h>
20 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
21 #include <spi_flash.h>
22 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
23 #include <mmc.h>
24 #endif
25
26 #ifndef CONFIG_PHYLIB_10G
27 #error The Cortina PHY needs 10G support
28 #endif
29
30 #ifndef CORTINA_NO_FW_UPLOAD
31 struct cortina_reg_config cortina_reg_cfg[] = {
32 /* CS4315_enable_sr_mode */
33 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
34 {VILLA_MSEQ_OPTIONS, 0xf},
35 {VILLA_MSEQ_PC, 0x0},
36 {VILLA_MSEQ_BANKSELECT, 0x4},
37 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
38 {VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
39 {VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
40 {VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
41 {VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
42 {VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
43 {VILLA_MSEQ_ENABLE_MSB, 0x0000},
44 {VILLA_MSEQ_SPARE21_LSB, 0x6},
45 {VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
46 {VILLA_MSEQ_SPARE12_MSB, 0x0000},
47 /*
48 * to invert the receiver path, uncomment the next line
49 * write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
50 *
51 * SPARE2_LSB is used to configure the device while in sr mode to
52 * enable power savings and to use the optical module LOS signal.
53 * in power savings mode, the internal prbs checker can not be used.
54 * if the optical module LOS signal is used as an input to the micro
55 * code, then the micro code will wait until the optical module
56 * LOS = 0 before turning on the adaptive equalizer.
57 * Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
58 * while setting bit 0 to 0 disables power savings mode.
59 * Setting SPARE2_LSB bit 2 to 0 configures the device to use the
60 * optical module LOS signal while setting bit 2 to 1 configures the
61 * device so that it will ignore the optical module LOS SPARE2_LSB = 0
62 */
63
64 /* enable power savings, ignore optical module LOS */
65 {VILLA_MSEQ_SPARE2_LSB, 0x5},
66
67 {VILLA_MSEQ_SPARE7_LSB, 0x1e},
68 {VILLA_MSEQ_BANKSELECT, 0x4},
69 {VILLA_MSEQ_SPARE9_LSB, 0x2},
70 {VILLA_MSEQ_SPARE3_LSB, 0x0F53},
71 {VILLA_MSEQ_SPARE3_MSB, 0x2006},
72 {VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
73 {VILLA_MSEQ_SPARE8_MSB, 0x0A46},
74 {VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
75 {VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
76 {VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
77 {VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
78 {VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
79 {VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
80 {VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
81 {VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
82 {VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
83 {VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
84 {VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
85 {VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
86 {VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
87 {VILLA_MSEQ_CAL_RX_SLICER, 0x80},
88 {VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
89 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
90 {VILLA_MSEQ_OPTIONS, 0x7},
91
92 /* set up min value for ffe1 */
93 {VILLA_MSEQ_COEF_INIT_SEL, 0x2},
94 {VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
95
96 /* CS4315_sr_rx_pre_eq_set_4in */
97 {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
98 {VILLA_MSEQ_OPTIONS, 0xf},
99 {VILLA_MSEQ_BANKSELECT, 0x4},
100 {VILLA_MSEQ_PC, 0x0},
101
102 /* for lengths from 3.5 to 4.5inches */
103 {VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
104 {VILLA_MSEQ_SPARE25_LSB, 0x0306},
105 {VILLA_MSEQ_SPARE21_LSB, 0x2},
106 {VILLA_MSEQ_SPARE23_LSB, 0x2},
107 {VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
108
109 {VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
110 {VILLA_MSEQ_OPTIONS, 0x7},
111
112 /* CS4315_rx_drive_4inch */
113 /* for length 4inches */
114 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
115 {VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
116 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
117
118 /* CS4315_tx_drive_4inch */
119 /* for length 4inches */
120 {VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
121 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
122 {VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
123 };
124
cs4340_upload_firmware(struct phy_device * phydev)125 void cs4340_upload_firmware(struct phy_device *phydev)
126 {
127 char line_temp[0x50] = {0};
128 char reg_addr[0x50] = {0};
129 char reg_data[0x50] = {0};
130 int i, line_cnt = 0, column_cnt = 0;
131 struct cortina_reg_config fw_temp;
132 char *addr = NULL;
133
134 #if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
135 defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
136
137 addr = (char *)CONFIG_CORTINA_FW_ADDR;
138 #elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
139 int ret;
140 size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
141
142 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
143 ret = nand_read(get_nand_dev_by_index(0),
144 (loff_t)CONFIG_CORTINA_FW_ADDR,
145 &fw_length, (u_char *)addr);
146 if (ret == -EUCLEAN) {
147 printf("NAND read of Cortina firmware at 0x%x failed %d\n",
148 CONFIG_CORTINA_FW_ADDR, ret);
149 }
150 #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
151 int ret;
152 struct spi_flash *ucode_flash;
153
154 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
155 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
156 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
157 if (!ucode_flash) {
158 puts("SF: probe for Cortina ucode failed\n");
159 } else {
160 ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
161 CONFIG_CORTINA_FW_LENGTH, addr);
162 if (ret)
163 puts("SF: read for Cortina ucode failed\n");
164 spi_flash_free(ucode_flash);
165 }
166 #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
167 int dev = CONFIG_SYS_MMC_ENV_DEV;
168 u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
169 u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
170 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
171
172 if (!mmc) {
173 puts("Failed to find MMC device for Cortina ucode\n");
174 } else {
175 addr = malloc(CONFIG_CORTINA_FW_LENGTH);
176 printf("MMC read: dev # %u, block # %u, count %u ...\n",
177 dev, blk, cnt);
178 mmc_init(mmc);
179 #ifdef CONFIG_BLK
180 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
181 addr);
182 #else
183 (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt,
184 addr);
185 #endif
186 }
187 #endif
188
189 while (*addr != 'Q') {
190 i = 0;
191
192 while (*addr != 0x0a) {
193 line_temp[i++] = *addr++;
194 if (0x50 < i) {
195 printf("Not found Cortina PHY ucode at 0x%p\n",
196 (char *)CONFIG_CORTINA_FW_ADDR);
197 return;
198 }
199 }
200
201 addr++; /* skip '\n' */
202 line_cnt++;
203 column_cnt = i;
204 line_temp[column_cnt] = '\0';
205
206 if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
207 return;
208
209 for (i = 0; i < column_cnt; i++) {
210 if (isspace(line_temp[i++]))
211 break;
212 }
213
214 memcpy(reg_addr, line_temp, i);
215 memcpy(reg_data, &line_temp[i], column_cnt - i);
216 strim(reg_addr);
217 strim(reg_data);
218 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
219 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
220 0xffff;
221 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
222 }
223 }
224 #endif
225
cs4340_phy_init(struct phy_device * phydev)226 int cs4340_phy_init(struct phy_device *phydev)
227 {
228 #ifndef CORTINA_NO_FW_UPLOAD
229 int timeout = 100; /* 100ms */
230 #endif
231 int reg_value;
232
233 /*
234 * Cortina phy has provision to store
235 * phy firmware in attached dedicated EEPROM.
236 * Boards designed with EEPROM attached to Cortina
237 * does not require FW upload.
238 */
239 #ifndef CORTINA_NO_FW_UPLOAD
240 /* step1: BIST test */
241 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
242 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
243 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
244 while (--timeout) {
245 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
246 if (reg_value & mseq_edc_bist_done) {
247 if (0 == (reg_value & mseq_edc_bist_fail))
248 break;
249 }
250 udelay(1000);
251 }
252
253 if (!timeout) {
254 printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
255 return -1;
256 }
257
258 /* setp2: upload ucode */
259 cs4340_upload_firmware(phydev);
260 #endif
261 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
262 if (reg_value) {
263 debug("%s checksum status failed.\n", __func__);
264 return -1;
265 }
266
267 return 0;
268 }
269
cs4340_config(struct phy_device * phydev)270 int cs4340_config(struct phy_device *phydev)
271 {
272 cs4340_phy_init(phydev);
273 return 0;
274 }
275
cs4340_probe(struct phy_device * phydev)276 int cs4340_probe(struct phy_device *phydev)
277 {
278 phydev->flags = PHY_FLAG_BROKEN_RESET;
279 return 0;
280 }
281
cs4340_startup(struct phy_device * phydev)282 int cs4340_startup(struct phy_device *phydev)
283 {
284 phydev->link = 1;
285
286 /* For now just lie and say it's 10G all the time */
287 phydev->speed = SPEED_10000;
288 phydev->duplex = DUPLEX_FULL;
289 return 0;
290 }
291
cs4223_phy_init(struct phy_device * phydev)292 int cs4223_phy_init(struct phy_device *phydev)
293 {
294 int reg_value;
295
296 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS);
297 if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) {
298 printf("%s CS4223 Firmware not present in EERPOM\n", __func__);
299 return -ENOSYS;
300 }
301
302 return 0;
303 }
304
cs4223_config(struct phy_device * phydev)305 int cs4223_config(struct phy_device *phydev)
306 {
307 return cs4223_phy_init(phydev);
308 }
309
cs4223_probe(struct phy_device * phydev)310 int cs4223_probe(struct phy_device *phydev)
311 {
312 phydev->flags = PHY_FLAG_BROKEN_RESET;
313 return 0;
314 }
315
cs4223_startup(struct phy_device * phydev)316 int cs4223_startup(struct phy_device *phydev)
317 {
318 phydev->link = 1;
319 phydev->speed = SPEED_10000;
320 phydev->duplex = DUPLEX_FULL;
321 return 0;
322 }
323
324 struct phy_driver cs4340_driver = {
325 .name = "Cortina CS4315/CS4340",
326 .uid = PHY_UID_CS4340,
327 .mask = 0xfffffff0,
328 .features = PHY_10G_FEATURES,
329 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
330 MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
331 MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
332 .config = &cs4340_config,
333 .probe = &cs4340_probe,
334 .startup = &cs4340_startup,
335 .shutdown = &gen10g_shutdown,
336 };
337
338 struct phy_driver cs4223_driver = {
339 .name = "Cortina CS4223",
340 .uid = PHY_UID_CS4223,
341 .mask = 0x0ffff00f,
342 .features = PHY_10G_FEATURES,
343 .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
344 MDIO_DEVS_AN),
345 .config = &cs4223_config,
346 .probe = &cs4223_probe,
347 .startup = &cs4223_startup,
348 .shutdown = &gen10g_shutdown,
349 };
350
phy_cortina_init(void)351 int phy_cortina_init(void)
352 {
353 phy_register(&cs4340_driver);
354 phy_register(&cs4223_driver);
355 return 0;
356 }
357
get_phy_id(struct mii_dev * bus,int addr,int devad,u32 * phy_id)358 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
359 {
360 int phy_reg;
361
362 /* Cortina PHY has non-standard offset of PHY ID registers */
363 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
364 if (phy_reg < 0)
365 return -EIO;
366 *phy_id = (phy_reg & 0xffff) << 16;
367
368 phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
369 if (phy_reg < 0)
370 return -EIO;
371 *phy_id |= (phy_reg & 0xffff);
372
373 if ((*phy_id == PHY_UID_CS4340) || (*phy_id == PHY_UID_CS4223))
374 return 0;
375
376 /*
377 * If Cortina PHY not detected,
378 * try generic way to find PHY ID registers
379 */
380 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
381 if (phy_reg < 0)
382 return -EIO;
383 *phy_id = (phy_reg & 0xffff) << 16;
384
385 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
386 if (phy_reg < 0)
387 return -EIO;
388 *phy_id |= (phy_reg & 0xffff);
389
390 return 0;
391 }
392