1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 */
5
6 /*
7 * CPU specific code for the MPC83xx family.
8 *
9 * Derived from the MPC8260 and MPC85xx.
10 */
11
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <irq_func.h>
15 #include <vsprintf.h>
16 #include <watchdog.h>
17 #include <command.h>
18 #include <mpc83xx.h>
19 #include <asm/processor.h>
20 #include <linux/libfdt.h>
21 #include <tsec.h>
22 #include <netdev.h>
23 #include <fsl_esdhc.h>
24 #if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
25 #include <linux/immap_qe.h>
26 #include <asm/io.h>
27 #endif
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 #ifndef CONFIG_CPU_MPC83XX
checkcpu(void)32 int checkcpu(void)
33 {
34 volatile immap_t *immr;
35 ulong clock = gd->cpu_clk;
36 u32 pvr = get_pvr();
37 u32 spridr;
38 char buf[32];
39 int ret;
40 int i;
41
42 const struct cpu_type {
43 char name[15];
44 u32 partid;
45 } cpu_type_list [] = {
46 CPU_TYPE_ENTRY(8308),
47 CPU_TYPE_ENTRY(8309),
48 CPU_TYPE_ENTRY(8311),
49 CPU_TYPE_ENTRY(8313),
50 CPU_TYPE_ENTRY(8314),
51 CPU_TYPE_ENTRY(8315),
52 CPU_TYPE_ENTRY(8321),
53 CPU_TYPE_ENTRY(8323),
54 CPU_TYPE_ENTRY(8343),
55 CPU_TYPE_ENTRY(8347_TBGA_),
56 CPU_TYPE_ENTRY(8347_PBGA_),
57 CPU_TYPE_ENTRY(8349),
58 CPU_TYPE_ENTRY(8358_TBGA_),
59 CPU_TYPE_ENTRY(8358_PBGA_),
60 CPU_TYPE_ENTRY(8360),
61 CPU_TYPE_ENTRY(8377),
62 CPU_TYPE_ENTRY(8378),
63 CPU_TYPE_ENTRY(8379),
64 };
65
66 immr = (immap_t *)CONFIG_SYS_IMMR;
67
68 ret = prt_83xx_rsr();
69 if (ret)
70 return ret;
71
72 puts("CPU: ");
73
74 switch (pvr & 0xffff0000) {
75 case PVR_E300C1:
76 printf("e300c1, ");
77 break;
78
79 case PVR_E300C2:
80 printf("e300c2, ");
81 break;
82
83 case PVR_E300C3:
84 printf("e300c3, ");
85 break;
86
87 case PVR_E300C4:
88 printf("e300c4, ");
89 break;
90
91 default:
92 printf("Unknown core, ");
93 }
94
95 spridr = immr->sysconf.spridr;
96
97 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
98 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
99 puts("MPC");
100 puts(cpu_type_list[i].name);
101 if (IS_E_PROCESSOR(spridr))
102 puts("E");
103 if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
104 SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
105 REVID_MAJOR(spridr) >= 2)
106 puts("A");
107 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
108 REVID_MINOR(spridr));
109 break;
110 }
111
112 if (i == ARRAY_SIZE(cpu_type_list))
113 printf("(SPRIDR %08x unknown), ", spridr);
114
115 printf(" at %s MHz, ", strmhz(buf, clock));
116
117 printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
118
119 return 0;
120 }
121 #endif
122
123 #ifndef CONFIG_SYSRESET
124 int
do_reset(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])125 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
126 {
127 ulong msr;
128 #ifndef MPC83xx_RESET
129 ulong addr;
130 #endif
131
132 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
133
134 puts("Resetting the board.\n");
135
136 #ifdef MPC83xx_RESET
137
138 /* Interrupts and MMU off */
139 msr = mfmsr();
140 msr &= ~(MSR_EE | MSR_IR | MSR_DR);
141 mtmsr(msr);
142
143 /* enable Reset Control Reg */
144 immap->reset.rpr = 0x52535445;
145 sync();
146 isync();
147
148 /* confirm Reset Control Reg is enabled */
149 while(!((immap->reset.rcer) & RCER_CRE))
150 ;
151
152 udelay(200);
153
154 /* perform reset, only one bit */
155 immap->reset.rcr = RCR_SWHR;
156
157 #else /* ! MPC83xx_RESET */
158
159 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
160
161 /* Interrupts and MMU off */
162 msr = mfmsr();
163 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
164 mtmsr(msr);
165
166 /*
167 * Trying to execute the next instruction at a non-existing address
168 * should cause a machine check, resulting in reset
169 */
170 addr = CONFIG_SYS_RESET_ADDRESS;
171
172 ((void (*)(void)) addr) ();
173 #endif /* MPC83xx_RESET */
174
175 return 1;
176 }
177 #endif
178
179 /*
180 * Get timebase clock frequency (like cpu_clk in Hz)
181 */
182 #ifndef CONFIG_TIMER
get_tbclk(void)183 unsigned long get_tbclk(void)
184 {
185 return (gd->bus_clk + 3L) / 4L;
186 }
187 #endif
188
189 #if defined(CONFIG_WATCHDOG)
watchdog_reset(void)190 void watchdog_reset (void)
191 {
192 int re_enable = disable_interrupts();
193
194 /* Reset the 83xx watchdog */
195 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
196 immr->wdt.swsrr = 0x556c;
197 immr->wdt.swsrr = 0xaa39;
198
199 if (re_enable)
200 enable_interrupts();
201 }
202 #endif
203
204 #ifndef CONFIG_DM_ETH
205 /*
206 * Initializes on-chip ethernet controllers.
207 * to override, implement board_eth_init()
208 */
cpu_eth_init(bd_t * bis)209 int cpu_eth_init(bd_t *bis)
210 {
211 #if defined(CONFIG_UEC_ETH)
212 uec_standard_init(bis);
213 #endif
214
215 #if defined(CONFIG_TSEC_ENET)
216 tsec_standard_init(bis);
217 #endif
218 return 0;
219 }
220 #endif /* !CONFIG_DM_ETH */
221
222 /*
223 * Initializes on-chip MMC controllers.
224 * to override, implement board_mmc_init()
225 */
cpu_mmc_init(bd_t * bis)226 int cpu_mmc_init(bd_t *bis)
227 {
228 #ifdef CONFIG_FSL_ESDHC
229 return fsl_esdhc_mmc_init(bis);
230 #else
231 return 0;
232 #endif
233 }
234
ppcDWstore(unsigned int * addr,unsigned int * value)235 void ppcDWstore(unsigned int *addr, unsigned int *value)
236 {
237 asm("lfd 1, 0(%1)\n\t"
238 "stfd 1, 0(%0)"
239 :
240 : "r" (addr), "r" (value)
241 : "memory");
242 }
243
ppcDWload(unsigned int * addr,unsigned int * ret)244 void ppcDWload(unsigned int *addr, unsigned int *ret)
245 {
246 asm("lfd 1, 0(%0)\n\t"
247 "stfd 1, 0(%1)"
248 :
249 : "r" (addr), "r" (ret)
250 : "memory");
251 }
252