1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
10 */
11
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <irq_func.h>
15 #include <asm/arch/pxa-regs.h>
16 #include <asm/io.h>
17 #include <asm/system.h>
18 #include <command.h>
19
20 /* Flush I/D-cache */
cache_flush(void)21 static void cache_flush(void)
22 {
23 unsigned long i = 0;
24
25 asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
26 }
27
cleanup_before_linux(void)28 int cleanup_before_linux(void)
29 {
30 /*
31 * This function is called just before we call Linux. It prepares
32 * the processor for Linux by just disabling everything that can
33 * disturb booting Linux.
34 */
35
36 disable_interrupts();
37 icache_disable();
38 dcache_disable();
39 cache_flush();
40
41 return 0;
42 }
43
writelrb(uint32_t val,uint32_t addr)44 inline void writelrb(uint32_t val, uint32_t addr)
45 {
46 writel(val, addr);
47 asm volatile("" : : : "memory");
48 readl(addr);
49 asm volatile("" : : : "memory");
50 }
51
pxa2xx_dram_init(void)52 void pxa2xx_dram_init(void)
53 {
54 uint32_t tmp;
55 int i;
56 /*
57 * 1) Initialize Asynchronous static memory controller
58 */
59
60 writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
61 writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
62 writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
63 /*
64 * 2) Initialize Card Interface
65 */
66
67 /* MECR: Memory Expansion Card Register */
68 writelrb(CONFIG_SYS_MECR_VAL, MECR);
69 /* MCMEM0: Card Interface slot 0 timing */
70 writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
71 /* MCMEM1: Card Interface slot 1 timing */
72 writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
73 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
74 writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
75 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
76 writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
77 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
78 writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
79 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
80 writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
81
82 /*
83 * 3) Configure Fly-By DMA register
84 */
85
86 writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
87
88 /*
89 * 4) Initialize Timing for Sync Memory (SDCLK0)
90 */
91
92 /*
93 * Before accessing MDREFR we need a valid DRI field, so we set
94 * this to power on defaults + DRI field.
95 */
96
97 /* Read current MDREFR config and zero out DRI */
98 tmp = readl(MDREFR) & ~0xfff;
99 /* Add user-specified DRI */
100 tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
101 /* Configure important bits */
102 tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
103 tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
104
105 /* Write MDREFR back */
106 writelrb(tmp, MDREFR);
107
108 /*
109 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
110 */
111
112 /* Initialize SXCNFG register. Assert the enable bits.
113 *
114 * Write SXMRS to cause an MRS command to all enabled banks of
115 * synchronous static memory. Note that SXLCR need not be written
116 * at this time.
117 */
118 writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
119
120 /*
121 * 6) Initialize SDRAM
122 */
123
124 writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
125 writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
126
127 /*
128 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
129 * but not enable each SDRAM partition pair.
130 */
131
132 writelrb(CONFIG_SYS_MDCNFG_VAL &
133 ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
134
135 /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
136 writel(0, OSCR);
137 while (readl(OSCR) < 0x300)
138 asm volatile("" : : : "memory");
139
140 /*
141 * 8) Trigger a number (usually 8) refresh cycles by attempting
142 * non-burst read or write accesses to disabled SDRAM, as commonly
143 * specified in the power up sequence documented in SDRAM data
144 * sheets. The address(es) used for this purpose must not be
145 * cacheable.
146 */
147 for (i = 9; i >= 0; i--) {
148 writel(i, 0xa0000000);
149 asm volatile("" : : : "memory");
150 }
151 /*
152 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
153 */
154
155 tmp = CONFIG_SYS_MDCNFG_VAL &
156 (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
157 tmp |= readl(MDCNFG);
158 writelrb(tmp, MDCNFG);
159
160 /*
161 * 10) Write MDMRS.
162 */
163
164 writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
165
166 /*
167 * 11) Enable APD
168 */
169
170 if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
171 tmp = readl(MDREFR);
172 tmp |= MDREFR_APD;
173 writelrb(tmp, MDREFR);
174 }
175 }
176
pxa_gpio_setup(void)177 void pxa_gpio_setup(void)
178 {
179 writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
180 writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
181 writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
182 #if defined(CONFIG_CPU_PXA27X)
183 writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
184 #endif
185
186 writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
187 writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
188 writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
189 #if defined(CONFIG_CPU_PXA27X)
190 writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
191 #endif
192
193 writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
194 writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
195 writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
196 #if defined(CONFIG_CPU_PXA27X)
197 writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
198 #endif
199
200 writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
201 writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
202 writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
203 writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
204 writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
205 writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
206 #if defined(CONFIG_CPU_PXA27X)
207 writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
208 writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
209 #endif
210
211 writel(CONFIG_SYS_PSSR_VAL, PSSR);
212 }
213
pxa_interrupt_setup(void)214 void pxa_interrupt_setup(void)
215 {
216 writel(0, ICLR);
217 writel(0, ICMR);
218 #if defined(CONFIG_CPU_PXA27X)
219 writel(0, ICLR2);
220 writel(0, ICMR2);
221 #endif
222 }
223
pxa_clock_setup(void)224 void pxa_clock_setup(void)
225 {
226 writel(CONFIG_SYS_CKEN, CKEN);
227 writel(CONFIG_SYS_CCCR, CCCR);
228 asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
229
230 /* enable the 32Khz oscillator for RTC and PowerManager */
231 writel(OSCC_OON, OSCC);
232 while (!(readl(OSCC) & OSCC_OOK))
233 asm volatile("" : : : "memory");
234 }
235
pxa_wakeup(void)236 void pxa_wakeup(void)
237 {
238 uint32_t rcsr;
239
240 rcsr = readl(RCSR);
241 writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
242
243 /* Wakeup */
244 if (rcsr & RCSR_SMR) {
245 writel(PSSR_PH, PSSR);
246 pxa2xx_dram_init();
247 icache_disable();
248 dcache_disable();
249 asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
250 }
251 }
252
arch_cpu_init(void)253 int arch_cpu_init(void)
254 {
255 pxa_gpio_setup();
256 pxa_wakeup();
257 pxa_interrupt_setup();
258 pxa_clock_setup();
259 return 0;
260 }
261
i2c_clk_enable(void)262 void i2c_clk_enable(void)
263 {
264 /* Set the global I2C clock on */
265 writel(readl(CKEN) | CKEN14_I2C, CKEN);
266 }
267
268 void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
269
reset_cpu(ulong ignored)270 void reset_cpu(ulong ignored)
271 {
272 uint32_t tmp;
273
274 setbits_le32(OWER, OWER_WME);
275
276 tmp = readl(OSCR);
277 tmp += 0x1000;
278 writel(tmp, OSMR3);
279 writel(MDREFR_SLFRSH, MDREFR);
280
281 for (;;)
282 ;
283 }
284
enable_caches(void)285 void enable_caches(void)
286 {
287 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
288 icache_enable();
289 #endif
290 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
291 dcache_enable();
292 #endif
293 }
294