| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
24 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
27 #define MMI_ADDI(reg1, reg2, immediate) \ argument
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
36 #define MMI_SRL(reg1, reg2, shift) \ argument
39 #define MMI_SLL(reg1, reg2, shift) \ argument
50 #define MMI_ADDU(reg1, reg2, reg3) \ argument
53 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
56 #define MMI_ADDI(reg1, reg2, immediate) \ argument
59 #define MMI_SUBU(reg1, reg2, reg3) \ argument
[all …]
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| /external/u-boot/arch/arm/mach-imx/ |
| D | sip.c | 10 unsigned long reg1, unsigned long reg2, in call_imx_sip()
30 unsigned long *reg1, unsigned long reg2, in call_imx_sip_ret2()
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| /external/u-boot/post/lib_powerpc/ |
| D | twox.c | 83 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_twox() local
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| D | two.c | 83 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_two() local
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| D | threei.c | 77 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threei() local
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| D | andi.c | 63 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_andi() local
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| D | srawi.c | 63 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_srawi() local
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| D | three.c | 157 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_three() local
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| D | threex.c | 127 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threex() local
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| D | rlwinm.c | 61 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwinm() local
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| D | rlwnm.c | 62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwnm() local
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| D | rlwimi.c | 64 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwimi() local
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| /external/u-boot/drivers/mtd/nand/raw/ |
| D | nand_ecc.c | 68 uint8_t idx, reg1, reg2, reg3, tmp1, tmp2; in nand_calculate_ecc() local
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| /external/u-boot/board/mscc/jr2/ |
| D | jr2.c | 40 void __iomem *reg0, *reg1; in vcoreiii_gpio_set_alternate() local
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| /external/capstone/arch/X86/ |
| D | X86Mapping.c | 47236 x86_reg reg1, reg2; member
47505 bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2) in X86_insn_reg_intel2()
47522 bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2) in X86_insn_reg_att2()
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 45 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
129 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_odd_process_store() local
355 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_even_process_store() local
435 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct8x32_column_odd_process_store() local
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| D | txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \ argument
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| /external/libyuv/files/source/ |
| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
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| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
567 v8u16 reg0, reg1; in ScaleFilterCols_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | compare_msa.cc | 59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
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| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
567 v8u16 reg0, reg1; in ScaleFilterCols_MSA() local
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
860 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_1_Box_MSA() local
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| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
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| /external/v8/src/interpreter/ |
| D | bytecode-register.cc | 97 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous()
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hisi_dvfs.c | 191 unsigned int reg1 = 0; in acpu_dvfs_freq_ascend() local
401 unsigned int reg1 = 0; in acpu_dvfs_freq_descend() local
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