1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <display.h>
10 #include <dm.h>
11 #include <edid.h>
12 #include <regmap.h>
13 #include <syscon.h>
14 #include <video.h>
15 #include <asm/gpio.h>
16 #include <asm/io.h>
17 #include <asm/arch-rockchip/clock.h>
18 #include <asm/arch-rockchip/edp_rk3288.h>
19 #include <asm/arch-rockchip/vop_rk3288.h>
20 #include <dm/device-internal.h>
21 #include <dm/uclass-internal.h>
22 #include <power/regulator.h>
23 #include "rk_vop.h"
24
25 DECLARE_GLOBAL_DATA_PTR;
26
27 enum vop_pol {
28 HSYNC_POSITIVE = 0,
29 VSYNC_POSITIVE = 1,
30 DEN_NEGATIVE = 2,
31 DCLK_INVERT = 3
32 };
33
rkvop_enable(struct rk3288_vop * regs,ulong fbbase,int fb_bits_per_pixel,const struct display_timing * edid)34 static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
35 int fb_bits_per_pixel,
36 const struct display_timing *edid)
37 {
38 u32 lb_mode;
39 u32 rgb_mode;
40 u32 hactive = edid->hactive.typ;
41 u32 vactive = edid->vactive.typ;
42
43 writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
44 ®s->win0_act_info);
45
46 writel(V_DSP_XST(edid->hsync_len.typ + edid->hback_porch.typ) |
47 V_DSP_YST(edid->vsync_len.typ + edid->vback_porch.typ),
48 ®s->win0_dsp_st);
49
50 writel(V_DSP_WIDTH(hactive - 1) |
51 V_DSP_HEIGHT(vactive - 1),
52 ®s->win0_dsp_info);
53
54 clrsetbits_le32(®s->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR,
55 V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0));
56
57 switch (fb_bits_per_pixel) {
58 case 16:
59 rgb_mode = RGB565;
60 writel(V_RGB565_VIRWIDTH(hactive), ®s->win0_vir);
61 break;
62 case 24:
63 rgb_mode = RGB888;
64 writel(V_RGB888_VIRWIDTH(hactive), ®s->win0_vir);
65 break;
66 case 32:
67 default:
68 rgb_mode = ARGB8888;
69 writel(V_ARGB888_VIRWIDTH(hactive), ®s->win0_vir);
70 break;
71 }
72
73 if (hactive > 2560)
74 lb_mode = LB_RGB_3840X2;
75 else if (hactive > 1920)
76 lb_mode = LB_RGB_2560X4;
77 else if (hactive > 1280)
78 lb_mode = LB_RGB_1920X5;
79 else
80 lb_mode = LB_RGB_1280X8;
81
82 clrsetbits_le32(®s->win0_ctrl0,
83 M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN,
84 V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) |
85 V_WIN0_EN(1));
86
87 writel(fbbase, ®s->win0_yrgb_mst);
88 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
89 }
90
rkvop_set_pin_polarity(struct udevice * dev,enum vop_modes mode,u32 polarity)91 static void rkvop_set_pin_polarity(struct udevice *dev,
92 enum vop_modes mode, u32 polarity)
93 {
94 struct rkvop_driverdata *ops =
95 (struct rkvop_driverdata *)dev_get_driver_data(dev);
96
97 if (ops->set_pin_polarity)
98 ops->set_pin_polarity(dev, mode, polarity);
99 }
100
rkvop_enable_output(struct udevice * dev,enum vop_modes mode)101 static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode)
102 {
103 struct rk_vop_priv *priv = dev_get_priv(dev);
104 struct rk3288_vop *regs = priv->regs;
105
106 /* remove from standby */
107 clrbits_le32(®s->sys_ctrl, V_STANDBY_EN(1));
108
109 switch (mode) {
110 case VOP_MODE_HDMI:
111 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
112 V_HDMI_OUT_EN(1));
113 break;
114
115 case VOP_MODE_EDP:
116 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
117 V_EDP_OUT_EN(1));
118 break;
119
120 case VOP_MODE_LVDS:
121 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
122 V_RGB_OUT_EN(1));
123 break;
124
125 case VOP_MODE_MIPI:
126 clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN,
127 V_MIPI_OUT_EN(1));
128 break;
129
130 default:
131 debug("%s: unsupported output mode %x\n", __func__, mode);
132 }
133 }
134
rkvop_mode_set(struct udevice * dev,const struct display_timing * edid,enum vop_modes mode)135 static void rkvop_mode_set(struct udevice *dev,
136 const struct display_timing *edid,
137 enum vop_modes mode)
138 {
139 struct rk_vop_priv *priv = dev_get_priv(dev);
140 struct rk3288_vop *regs = priv->regs;
141 struct rkvop_driverdata *data =
142 (struct rkvop_driverdata *)dev_get_driver_data(dev);
143
144 u32 hactive = edid->hactive.typ;
145 u32 vactive = edid->vactive.typ;
146 u32 hsync_len = edid->hsync_len.typ;
147 u32 hback_porch = edid->hback_porch.typ;
148 u32 vsync_len = edid->vsync_len.typ;
149 u32 vback_porch = edid->vback_porch.typ;
150 u32 hfront_porch = edid->hfront_porch.typ;
151 u32 vfront_porch = edid->vfront_porch.typ;
152 int mode_flags;
153 u32 pin_polarity;
154
155 pin_polarity = BIT(DCLK_INVERT);
156 if (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)
157 pin_polarity |= BIT(HSYNC_POSITIVE);
158 if (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)
159 pin_polarity |= BIT(VSYNC_POSITIVE);
160
161 rkvop_set_pin_polarity(dev, mode, pin_polarity);
162 rkvop_enable_output(dev, mode);
163
164 mode_flags = 0; /* RGB888 */
165 if ((data->features & VOP_FEATURE_OUTPUT_10BIT) &&
166 (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP))
167 mode_flags = 15; /* RGBaaa */
168
169 clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE,
170 V_DSP_OUT_MODE(mode_flags));
171
172 writel(V_HSYNC(hsync_len) |
173 V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch),
174 ®s->dsp_htotal_hs_end);
175
176 writel(V_HEAP(hsync_len + hback_porch + hactive) |
177 V_HASP(hsync_len + hback_porch),
178 ®s->dsp_hact_st_end);
179
180 writel(V_VSYNC(vsync_len) |
181 V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch),
182 ®s->dsp_vtotal_vs_end);
183
184 writel(V_VAEP(vsync_len + vback_porch + vactive)|
185 V_VASP(vsync_len + vback_porch),
186 ®s->dsp_vact_st_end);
187
188 writel(V_HEAP(hsync_len + hback_porch + hactive) |
189 V_HASP(hsync_len + hback_porch),
190 ®s->post_dsp_hact_info);
191
192 writel(V_VAEP(vsync_len + vback_porch + vactive)|
193 V_VASP(vsync_len + vback_porch),
194 ®s->post_dsp_vact_info);
195
196 writel(0x01, ®s->reg_cfg_done); /* enable reg config */
197 }
198
199 /**
200 * rk_display_init() - Try to enable the given display device
201 *
202 * This function performs many steps:
203 * - Finds the display device being referenced by @ep_node
204 * - Puts the VOP's ID into its uclass platform data
205 * - Probes the device to set it up
206 * - Reads the EDID timing information
207 * - Sets up the VOP clocks, etc. for the selected pixel clock and display mode
208 * - Enables the display (the display device handles this and will do different
209 * things depending on the display type)
210 * - Tells the uclass about the display resolution so that the console will
211 * appear correctly
212 *
213 * @dev: VOP device that we want to connect to the display
214 * @fbbase: Frame buffer address
215 * @ep_node: Device tree node to process - this is the offset of an endpoint
216 * node within the VOP's 'port' list.
217 * @return 0 if OK, -ve if something went wrong
218 */
rk_display_init(struct udevice * dev,ulong fbbase,ofnode ep_node)219 static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node)
220 {
221 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
222 struct rk_vop_priv *priv = dev_get_priv(dev);
223 int vop_id, remote_vop_id;
224 struct rk3288_vop *regs = priv->regs;
225 struct display_timing timing;
226 struct udevice *disp;
227 int ret;
228 u32 remote_phandle;
229 struct display_plat *disp_uc_plat;
230 struct clk clk;
231 enum video_log2_bpp l2bpp;
232 ofnode remote;
233
234 debug("%s(%s, %lu, %s)\n", __func__,
235 dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
236
237 vop_id = ofnode_read_s32_default(ep_node, "reg", -1);
238 debug("vop_id=%d\n", vop_id);
239 ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
240 if (ret)
241 return ret;
242
243 remote = ofnode_get_by_phandle(remote_phandle);
244 if (!ofnode_valid(remote))
245 return -EINVAL;
246 remote_vop_id = ofnode_read_u32_default(remote, "reg", -1);
247 debug("remote vop_id=%d\n", remote_vop_id);
248
249 /*
250 * The remote-endpoint references into a subnode of the encoder
251 * (i.e. HDMI, MIPI, etc.) with the DTS looking something like
252 * the following (assume 'hdmi_in_vopl' to be referenced):
253 *
254 * hdmi: hdmi@ff940000 {
255 * ports {
256 * hdmi_in: port {
257 * hdmi_in_vopb: endpoint@0 { ... };
258 * hdmi_in_vopl: endpoint@1 { ... };
259 * }
260 * }
261 * }
262 *
263 * The original code had 3 steps of "walking the parent", but
264 * a much better (as in: less likely to break if the DTS
265 * changes) way of doing this is to "find the enclosing device
266 * of UCLASS_DISPLAY".
267 */
268 while (ofnode_valid(remote)) {
269 remote = ofnode_get_parent(remote);
270 if (!ofnode_valid(remote)) {
271 debug("%s(%s): no UCLASS_DISPLAY for remote-endpoint\n",
272 __func__, dev_read_name(dev));
273 return -EINVAL;
274 }
275
276 uclass_find_device_by_ofnode(UCLASS_DISPLAY, remote, &disp);
277 if (disp)
278 break;
279 };
280
281 disp_uc_plat = dev_get_uclass_platdata(disp);
282 debug("Found device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
283 if (display_in_use(disp)) {
284 debug(" - device in use\n");
285 return -EBUSY;
286 }
287
288 disp_uc_plat->source_id = remote_vop_id;
289 disp_uc_plat->src_dev = dev;
290
291 ret = device_probe(disp);
292 if (ret) {
293 debug("%s: device '%s' display won't probe (ret=%d)\n",
294 __func__, dev->name, ret);
295 return ret;
296 }
297
298 ret = display_read_timing(disp, &timing);
299 if (ret) {
300 debug("%s: Failed to read timings\n", __func__);
301 return ret;
302 }
303
304 ret = clk_get_by_index(dev, 1, &clk);
305 if (!ret)
306 ret = clk_set_rate(&clk, timing.pixelclock.typ);
307 if (IS_ERR_VALUE(ret)) {
308 debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
309 return ret;
310 }
311
312 /* Set bitwidth for vop display according to vop mode */
313 switch (vop_id) {
314 case VOP_MODE_EDP:
315 case VOP_MODE_LVDS:
316 l2bpp = VIDEO_BPP16;
317 break;
318 case VOP_MODE_HDMI:
319 case VOP_MODE_MIPI:
320 l2bpp = VIDEO_BPP32;
321 break;
322 default:
323 l2bpp = VIDEO_BPP16;
324 }
325
326 rkvop_mode_set(dev, &timing, vop_id);
327 rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
328
329 ret = display_enable(disp, 1 << l2bpp, &timing);
330 if (ret)
331 return ret;
332
333 uc_priv->xsize = timing.hactive.typ;
334 uc_priv->ysize = timing.vactive.typ;
335 uc_priv->bpix = l2bpp;
336 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
337
338 return 0;
339 }
340
rk_vop_probe_regulators(struct udevice * dev,const char * const * names,int cnt)341 void rk_vop_probe_regulators(struct udevice *dev,
342 const char * const *names, int cnt)
343 {
344 int i, ret;
345 const char *name;
346 struct udevice *reg;
347
348 for (i = 0; i < cnt; ++i) {
349 name = names[i];
350 debug("%s: probing regulator '%s'\n", dev->name, name);
351
352 ret = regulator_autoset_by_name(name, ®);
353 if (!ret)
354 ret = regulator_set_enable(reg, true);
355 }
356 }
357
rk_vop_probe(struct udevice * dev)358 int rk_vop_probe(struct udevice *dev)
359 {
360 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
361 struct rk_vop_priv *priv = dev_get_priv(dev);
362 int ret = 0;
363 ofnode port, node;
364
365 /* Before relocation we don't need to do anything */
366 if (!(gd->flags & GD_FLG_RELOC))
367 return 0;
368
369 priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
370
371 /*
372 * Try all the ports until we find one that works. In practice this
373 * tries EDP first if available, then HDMI.
374 *
375 * Note that rockchip_vop_set_clk() always uses NPLL as the source
376 * clock so it is currently not possible to use more than one display
377 * device simultaneously.
378 */
379 port = dev_read_subnode(dev, "port");
380 if (!ofnode_valid(port)) {
381 debug("%s(%s): 'port' subnode not found\n",
382 __func__, dev_read_name(dev));
383 return -EINVAL;
384 }
385
386 for (node = ofnode_first_subnode(port);
387 ofnode_valid(node);
388 node = dev_read_next_subnode(node)) {
389 ret = rk_display_init(dev, plat->base, node);
390 if (ret)
391 debug("Device failed: ret=%d\n", ret);
392 if (!ret)
393 break;
394 }
395 video_set_flush_dcache(dev, 1);
396
397 return ret;
398 }
399
rk_vop_bind(struct udevice * dev)400 int rk_vop_bind(struct udevice *dev)
401 {
402 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
403
404 plat->size = 4 * (CONFIG_VIDEO_ROCKCHIP_MAX_XRES *
405 CONFIG_VIDEO_ROCKCHIP_MAX_YRES);
406
407 return 0;
408 }
409