| /external/v8/src/codegen/mips64/ |
| D | assembler-mips64.cc | 524 uint32_t rt = GetRtField(instr); in IsBeqc() local
531 uint32_t rt = GetRtField(instr); in IsBnec() local
594 uint32_t rt = GetRt(instr); in IsNop() local
1060 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt, in GenInstrRegister()
1069 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt, in GenInstrRegister()
1096 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, in GenInstrRegister()
1105 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, in GenInstrRegister()
1115 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt, in GenInstrImmediate()
1124 void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt, in GenInstrImmediate()
1446 void Assembler::beq(Register rs, Register rt, int16_t offset) { in beq()
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| D | assembler-mips64.h | 396 inline void beq(Register rs, Register rt, Label* L) { in beq()
401 inline void bgezc(Register rt, Label* L) { in bgezc()
405 inline void bgeuc(Register rs, Register rt, Label* L) { in bgeuc()
409 inline void bgec(Register rs, Register rt, Label* L) { in bgec()
414 inline void bgezalc(Register rt, Label* L) { in bgezalc()
423 inline void bgtzc(Register rt, Label* L) { in bgtzc()
428 inline void blezc(Register rt, Label* L) { in blezc()
433 inline void bltzc(Register rt, Label* L) { in bltzc()
437 inline void bltuc(Register rs, Register rt, Label* L) { in bltuc()
441 inline void bltc(Register rs, Register rt, Label* L) { in bltc()
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| D | macro-assembler-mips64.cc | 37 static inline bool IsZero(const Operand& rt) { in IsZero()
376 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) { in Addu()
393 void TurboAssembler::Daddu(Register rd, Register rs, const Operand& rt) { in Daddu()
410 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) { in Subu()
436 void TurboAssembler::Dsubu(Register rd, Register rs, const Operand& rt) { in Dsubu()
464 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) { in Mul()
477 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) { in Mulh()
500 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) { in Mulhu()
523 void TurboAssembler::Dmul(Register rd, Register rs, const Operand& rt) { in Dmul()
546 void TurboAssembler::Dmulh(Register rd, Register rs, const Operand& rt) { in Dmulh()
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| /external/v8/src/codegen/mips/ |
| D | assembler-mips.h | 399 inline void beq(Register rs, Register rt, Label* L) { in beq()
404 inline void bgezc(Register rt, Label* L) { in bgezc()
408 inline void bgeuc(Register rs, Register rt, Label* L) { in bgeuc()
412 inline void bgec(Register rs, Register rt, Label* L) { in bgec()
417 inline void bgezalc(Register rt, Label* L) { in bgezalc()
426 inline void bgtzc(Register rt, Label* L) { in bgtzc()
431 inline void blezc(Register rt, Label* L) { in blezc()
436 inline void bltzc(Register rt, Label* L) { in bltzc()
440 inline void bltuc(Register rs, Register rt, Label* L) { in bltuc()
444 inline void bltc(Register rs, Register rt, Label* L) { in bltc()
[all …]
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| D | assembler-mips.cc | 548 uint32_t rt = GetRtField(instr); in IsBeqc() local
555 uint32_t rt = GetRtField(instr); in IsBnec() local
611 bool Assembler::IsAddu(Instr instr, Register rd, Register rs, Register rt) { in IsAddu()
644 uint32_t rt = GetRt(instr); in IsNop() local
1134 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt, in GenInstrRegister()
1143 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt, in GenInstrRegister()
1170 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, in GenInstrRegister()
1179 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, in GenInstrRegister()
1189 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt, in GenInstrImmediate()
1198 void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt, in GenInstrImmediate()
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| D | macro-assembler-mips.cc | 37 static inline bool IsZero(const Operand& rt) { in IsZero()
378 void TurboAssembler::Addu(Register rd, Register rs, const Operand& rt) { in Addu()
395 void TurboAssembler::Subu(Register rd, Register rs, const Operand& rt) { in Subu()
420 void TurboAssembler::Mul(Register rd, Register rs, const Operand& rt) { in Mul()
444 const Operand& rt) { in Mul()
488 const Operand& rt) { in Mulu()
518 void TurboAssembler::Mulh(Register rd, Register rs, const Operand& rt) { in Mulh()
541 void TurboAssembler::Mult(Register rs, const Operand& rt) { in Mult()
554 void TurboAssembler::Mulhu(Register rd, Register rs, const Operand& rt) { in Mulhu()
577 void TurboAssembler::Multu(Register rs, const Operand& rt) { in Multu()
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| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d_nir_lower_logic_ops.c | 188 v3d_get_format_swizzle_for_rt(struct v3d_compile *c, int rt) in v3d_get_format_swizzle_for_rt()
205 v3d_nir_get_tlb_color(nir_builder *b, int rt, int sample) in v3d_nir_get_tlb_color()
227 int rt, int sample) in v3d_emit_logic_op_raw()
249 int rt, int sample, in v3d_emit_logic_op_unorm()
268 nir_ssa_def *src, int rt, int sample) in v3d_nir_emit_logic_op()
296 nir_alu_type type, int rt, int sample) in v3d_emit_ms_output()
315 int rt) in v3d_nir_lower_logic_op_instr()
370 const int rt = driver_loc; in v3d_nir_lower_logic_ops_block() local
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| /external/tensorflow/tensorflow/python/ops/ragged/ |
| D | ragged_merge_dims_op_test.py | 169 rt, argument
260 rt, argument
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| /external/toybox/toys/pending/ |
| D | route.c | 192 static void get_next_params(char **argv, struct rtentry *rt, char **netmask) in get_next_params()
242 static void verify_netmask(struct rtentry *rt, char *netmask) in verify_netmask()
260 struct rtentry rt; in setroute() local
304 static void is_prefix_inet6(char **tip, struct in6_rtmsg *rt) in is_prefix_inet6()
322 static void get_next_params_inet6(char **argv, struct sockaddr_in6 *sock_in6, struct in6_rtmsg *rt,… in get_next_params_inet6()
352 struct in6_rtmsg rt; in setroute_inet6() local
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| /external/strace/ |
| D | rtc.c | 42 print_rtc_time(struct tcb *tcp, const struct rtc_time *rt) in print_rtc_time()
58 struct rtc_time rt; in decode_rtc_time() local
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| /external/mesa3d/src/gallium/drivers/zink/ |
| D | zink_render_pass.c | 39 struct zink_rt_attrib *rt = state->rts + i; in create_render_pass() local
55 struct zink_rt_attrib *rt = state->rts + state->num_cbufs; in create_render_pass() local
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| /external/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_blend.c | 82 const struct pipe_rt_blend_state *rt; in __fd6_setup_blend_variant() local
166 const struct pipe_rt_blend_state *rt = &cso->rt[i]; in fd6_blend_state_create() local
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 290 void Assembler::cbz(const Register& rt, int64_t imm19) { in cbz()
295 void Assembler::cbz(const Register& rt, Label* label) { in cbz()
302 void Assembler::cbnz(const Register& rt, int64_t imm19) { in cbnz()
307 void Assembler::cbnz(const Register& rt, Label* label) { in cbnz()
420 void Assembler::tbz(const Register& rt, unsigned bit_pos, int64_t imm14) { in tbz()
426 void Assembler::tbz(const Register& rt, unsigned bit_pos, Label* label) { in tbz()
433 void Assembler::tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) { in tbnz()
439 void Assembler::tbnz(const Register& rt, unsigned bit_pos, Label* label) { in tbnz()
1096 void Assembler::ldp(const CPURegister& rt, in ldp()
1103 void Assembler::stp(const CPURegister& rt, in stp()
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| D | macro-assembler-aarch64.h | 1617 void Ldar(const Register& rt, const MemOperand& src) { in Ldar()
1622 void Ldarb(const Register& rt, const MemOperand& src) { in Ldarb()
1627 void Ldarh(const Register& rt, const MemOperand& src) { in Ldarh()
1632 void Ldlar(const Register& rt, const MemOperand& src) { in Ldlar()
1637 void Ldlarb(const Register& rt, const MemOperand& src) { in Ldlarb()
1642 void Ldlarh(const Register& rt, const MemOperand& src) { in Ldlarh()
1647 void Ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) { in Ldaxp()
1653 void Ldaxr(const Register& rt, const MemOperand& src) { in Ldaxr()
1658 void Ldaxrb(const Register& rt, const MemOperand& src) { in Ldaxrb()
1663 void Ldaxrh(const Register& rt, const MemOperand& src) { in Ldaxrh()
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/core/ |
| D | backend_clear.cpp | 62 SWR_RENDERTARGET_ATTACHMENT rt, in ClearMacroTile()
175 unsigned long rt = 0; in ProcessClearBE() local
248 unsigned long rt = 0; in ProcessClearBE() local
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| /external/mesa3d/src/gallium/drivers/panfrost/ |
| D | pan_blend_cso.c | 73 unsigned rt, in panfrost_get_blend_shader()
130 struct panfrost_blend_rt *rt = &so->rt[c]; in panfrost_create_blend_state() local
233 struct panfrost_blend_rt *rt = &blend->rt[rti]; in panfrost_get_blend_for_context() local
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| /external/v8/src/execution/ppc/ |
| D | simulator-ppc.cc | 1382 int rt = instr->RTValue(); in ExecuteGeneric() local
1470 int rt = instr->RTValue(); in ExecuteGeneric() local
1485 int rt = instr->RTValue(); in ExecuteGeneric() local
1500 int rt = instr->RTValue(); in ExecuteGeneric() local
1734 int rt = instr->RTValue(); in ExecuteGeneric() local
1745 int rt = instr->RTValue(); in ExecuteGeneric() local
1756 int rt = instr->RTValue(); in ExecuteGeneric() local
1770 int rt = instr->RTValue(); in ExecuteGeneric() local
1998 int rt = instr->RTValue(); in ExecuteGeneric() local
2012 int rt = instr->RTValue(); in ExecuteGeneric() local
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| /external/angle/src/tests/gles_conformance_tests/ |
| D | gles_conformance_tests_main.cpp | 21 int rt = RUN_ALL_TESTS(); in main() local
|
| /external/skia/src/gpu/d3d/ |
| D | GrD3DGpu.cpp | 26 GrRenderTarget* rt, GrSurfaceOrigin origin, const SkIRect& bounds, in getOpsRenderPass()
39 void GrD3DGpu::querySampleLocations(GrRenderTarget* rt, SkTArray<SkPoint>* sampleLocations) { in querySampleLocations()
87 sk_sp<GrRenderTarget> GrD3DGpu::onWrapBackendRenderTarget(const GrBackendRenderTarget& rt, in onWrapBackendRenderTarget()
107 const GrRenderTarget* rt, int width, int height, int numStencilSamples) { in createStencilAttachmentForRenderTarget()
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| /external/skia/src/gpu/gl/ |
| D | GrGLOpsRenderPass.cpp | 14 void GrGLOpsRenderPass::set(GrRenderTarget* rt, const SkIRect& contentBounds, in set()
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| /external/pdfium/fxjs/ |
| D | cjs_globalarrays.cpp | 9 #define GLOBAL_ARRAY(rt, name, ...) \ argument
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| D | cjs_globalconsts.cpp | 9 #define GLOBAL_STRING(rt, name, value) \ argument
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| /external/strace/linux/arm/ |
| D | raw_syscall.h | 42 register kernel_ulong_t rt; in raw_syscall_0() local
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| /external/skqp/src/gpu/gl/ |
| D | GrGLGpuCommandBuffer.cpp | 26 void GrGLGpuRTCommandBuffer::set(GrRenderTarget* rt, GrSurfaceOrigin origin, in set()
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| /external/pdfium/core/fxcrt/ |
| D | fx_coordinates.h | 390 void Inflate(const CFX_RectF& rt) { in Inflate()
409 void Deflate(const CFX_RectF& rt) { in Deflate()
421 bool Contains(const CFX_RectF& rt) const { in Contains()
452 void Union(const CFX_RectF& rt) { in Union()
464 void Intersect(const CFX_RectF& rt) { in Intersect()
476 bool IntersectWith(const CFX_RectF& rt) const { in IntersectWith()
481 bool IntersectWith(const CFX_RectF& rt, float fEpsilon) const { in IntersectWith()
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