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Searched defs:saddlv (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-across.s13 saddlv d0, v1.4s define
Dneon-diagnostics.s3659 saddlv d0, v1.2s define
/external/llvm/test/MC/AArch64/
Dneon-across.s13 saddlv d0, v1.4s define
Dneon-diagnostics.s3719 saddlv d0, v1.2s define
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1391 __ saddlv(d12, v7.V4S()); in GenerateTestSequenceNEON() local
1392 __ saddlv(h14, v28.V16B()); in GenerateTestSequenceNEON() local
1393 __ saddlv(h30, v30.V8B()); in GenerateTestSequenceNEON() local
1394 __ saddlv(s27, v3.V4H()); in GenerateTestSequenceNEON() local
1395 __ saddlv(s16, v16.V8H()); in GenerateTestSequenceNEON() local
/external/v8/src/codegen/arm64/
Dassembler-arm64.cc2005 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) { in saddlv() function in v8::internal::Assembler
/external/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1186 LogicVRegister Simulator::saddlv(VectorFormat vform, LogicVRegister dst, in saddlv() function in v8::internal::Simulator
/external/vixl/src/aarch64/
Dassembler-aarch64.cc4722 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) { in saddlv() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc1265 LogicVRegister Simulator::saddlv(VectorFormat vform, in saddlv() function in vixl::aarch64::Simulator