1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <time.h>
9 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
10 #include <hwconfig.h>
11 #endif
12 #include <asm/fsl_serdes.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/io.h>
15 #include <asm/processor.h>
16 #include <asm/fsl_law.h>
17 #include <linux/errno.h>
18 #include "fsl_corenet_serdes.h"
19
20 /*
21 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
22 * The code is already very complicated as it is, and separating the two
23 * completely would just make things worse. We try to keep them as separate
24 * as possible, but for now we require SERDES8 if SERDES_A001 is defined.
25 */
26 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
27 #ifndef CONFIG_SYS_P4080_ERRATUM_SERDES8
28 #error "CONFIG_SYS_P4080_ERRATUM_SERDES_A001 requires CONFIG_SYS_P4080_ERRATUM_SERDES8"
29 #endif
30 #endif
31
32 static u32 serdes_prtcl_map;
33
34 #ifdef DEBUG
35 static const char *serdes_prtcl_str[] = {
36 [NONE] = "NA",
37 [PCIE1] = "PCIE1",
38 [PCIE2] = "PCIE2",
39 [PCIE3] = "PCIE3",
40 [PCIE4] = "PCIE4",
41 [SATA1] = "SATA1",
42 [SATA2] = "SATA2",
43 [SRIO1] = "SRIO1",
44 [SRIO2] = "SRIO2",
45 [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
46 [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
47 [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
48 [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
49 [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
50 [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
51 [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
52 [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
53 [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
54 [SGMII_FM2_DTSEC5] = "SGMII_FM2_DTSEC5",
55 [XAUI_FM1] = "XAUI_FM1",
56 [XAUI_FM2] = "XAUI_FM2",
57 [AURORA] = "DEBUG",
58 };
59 #endif
60
61 static const struct {
62 int idx;
63 unsigned int lpd; /* RCW lane powerdown bit */
64 int bank;
65 } lanes[SRDS_MAX_LANES] = {
66 { 0, 152, FSL_SRDS_BANK_1 },
67 { 1, 153, FSL_SRDS_BANK_1 },
68 { 2, 154, FSL_SRDS_BANK_1 },
69 { 3, 155, FSL_SRDS_BANK_1 },
70 { 4, 156, FSL_SRDS_BANK_1 },
71 { 5, 157, FSL_SRDS_BANK_1 },
72 { 6, 158, FSL_SRDS_BANK_1 },
73 { 7, 159, FSL_SRDS_BANK_1 },
74 { 8, 160, FSL_SRDS_BANK_1 },
75 { 9, 161, FSL_SRDS_BANK_1 },
76 { 16, 162, FSL_SRDS_BANK_2 },
77 { 17, 163, FSL_SRDS_BANK_2 },
78 { 18, 164, FSL_SRDS_BANK_2 },
79 { 19, 165, FSL_SRDS_BANK_2 },
80 #ifdef CONFIG_ARCH_P4080
81 { 20, 170, FSL_SRDS_BANK_3 },
82 { 21, 171, FSL_SRDS_BANK_3 },
83 { 22, 172, FSL_SRDS_BANK_3 },
84 { 23, 173, FSL_SRDS_BANK_3 },
85 #else
86 { 20, 166, FSL_SRDS_BANK_3 },
87 { 21, 167, FSL_SRDS_BANK_3 },
88 { 22, 168, FSL_SRDS_BANK_3 },
89 { 23, 169, FSL_SRDS_BANK_3 },
90 #endif
91 #if SRDS_MAX_BANK > 3
92 { 24, 175, FSL_SRDS_BANK_4 },
93 { 25, 176, FSL_SRDS_BANK_4 },
94 #endif
95 };
96
serdes_get_lane_idx(int lane)97 int serdes_get_lane_idx(int lane)
98 {
99 return lanes[lane].idx;
100 }
101
serdes_get_bank_by_lane(int lane)102 int serdes_get_bank_by_lane(int lane)
103 {
104 return lanes[lane].bank;
105 }
106
serdes_lane_enabled(int lane)107 int serdes_lane_enabled(int lane)
108 {
109 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
110 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
111
112 int bank = lanes[lane].bank;
113 int word = lanes[lane].lpd / 32;
114 int bit = lanes[lane].lpd % 32;
115
116 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
117 return 0;
118
119 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
120 /*
121 * For banks two and three, use the srds_lpd_b[] array instead of the
122 * RCW, because this array contains the real values of SRDS_LPD_B2 and
123 * SRDS_LPD_B3.
124 */
125 if (bank > 0)
126 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank))));
127 #endif
128
129 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
130 }
131
is_serdes_configured(enum srds_prtcl device)132 int is_serdes_configured(enum srds_prtcl device)
133 {
134 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
135
136 /* Is serdes enabled at all? */
137 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
138 return 0;
139
140 if (!(serdes_prtcl_map & (1 << NONE)))
141 fsl_serdes_init();
142
143 return (1 << device) & serdes_prtcl_map;
144 }
145
__serdes_get_first_lane(uint32_t prtcl,enum srds_prtcl device)146 static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
147 {
148 int i;
149
150 for (i = 0; i < SRDS_MAX_LANES; i++) {
151 if (serdes_get_prtcl(prtcl, i) == device)
152 return i;
153 }
154
155 return -ENODEV;
156 }
157
158 /*
159 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
160 * device. This depends on the current SERDES protocol, as defined in the RCW.
161 *
162 * Returns a negative error code if SERDES is disabled or the given device is
163 * not supported in the current SERDES protocol.
164 */
serdes_get_first_lane(enum srds_prtcl device)165 int serdes_get_first_lane(enum srds_prtcl device)
166 {
167 u32 prtcl;
168 const ccsr_gur_t *gur;
169
170 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
171
172 /* Is serdes enabled at all? */
173 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
174 return -ENODEV;
175
176 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
177
178 return __serdes_get_first_lane(prtcl, device);
179 }
180
181 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
182 /*
183 * Returns the SERDES bank (1, 2, or 3) that a given device is on for a given
184 * SERDES protocol.
185 *
186 * Returns a negative error code if the given device is not supported for the
187 * given SERDES protocol.
188 */
serdes_get_bank_by_device(uint32_t prtcl,enum srds_prtcl device)189 static int serdes_get_bank_by_device(uint32_t prtcl, enum srds_prtcl device)
190 {
191 int lane;
192
193 lane = __serdes_get_first_lane(prtcl, device);
194 if (unlikely(lane < 0))
195 return lane;
196
197 return serdes_get_bank_by_lane(lane);
198 }
199
__serdes_get_lane_count(uint32_t prtcl,enum srds_prtcl device,int first)200 static uint32_t __serdes_get_lane_count(uint32_t prtcl, enum srds_prtcl device,
201 int first)
202 {
203 int lane;
204
205 for (lane = first; lane < SRDS_MAX_LANES; lane++) {
206 if (serdes_get_prtcl(prtcl, lane) != device)
207 break;
208 }
209
210 return lane - first;
211 }
212
__serdes_reset_rx(serdes_corenet_t * regs,uint32_t prtcl,enum srds_prtcl device)213 static void __serdes_reset_rx(serdes_corenet_t *regs,
214 uint32_t prtcl,
215 enum srds_prtcl device)
216 {
217 int lane, idx, first, last;
218
219 lane = __serdes_get_first_lane(prtcl, device);
220 if (unlikely(lane < 0))
221 return;
222 first = serdes_get_lane_idx(lane);
223 last = first + __serdes_get_lane_count(prtcl, device, lane);
224
225 /*
226 * Set BnGCRy0[RRST] = 0 for each lane in the each bank that is
227 * selected as XAUI to place the lane into reset.
228 */
229 for (idx = first; idx < last; idx++)
230 clrbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
231
232 /* Wait at least 250 ns */
233 udelay(1);
234
235 /*
236 * Set BnGCRy0[RRST] = 1 for each lane in the each bank that is
237 * selected as XAUI to bring the lane out of reset.
238 */
239 for (idx = first; idx < last; idx++)
240 setbits_be32(®s->lane[idx].gcr0, SRDS_GCR0_RRST);
241 }
242
serdes_reset_rx(enum srds_prtcl device)243 void serdes_reset_rx(enum srds_prtcl device)
244 {
245 u32 prtcl;
246 const ccsr_gur_t *gur;
247 serdes_corenet_t *regs;
248
249 if (unlikely(device == NONE))
250 return;
251
252 gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
253
254 /* Is serdes enabled at all? */
255 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
256 return;
257
258 regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
259 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
260
261 __serdes_reset_rx(regs, prtcl, device);
262 }
263 #endif
264
265 #ifndef CONFIG_SYS_DCSRBAR_PHYS
266 #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */
267 #define CONFIG_SYS_DCSRBAR 0x80000000
268 #define __DCSR_NOT_DEFINED_BY_CONFIG
269 #endif
270
271 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
272 /*
273 * Enable a SERDES bank that was disabled via the RCW
274 *
275 * We only call this function for SERDES8 and SERDES-A001 in cases we really
276 * want to enable the bank, whether we actually want to use the lanes or not,
277 * so make sure at least one lane is enabled. We're only enabling this one
278 * lane to satisfy errata requirements that the bank be enabled.
279 *
280 * We use a local variable instead of srds_lpd_b[] because we want drivers to
281 * think that the lanes actually are disabled.
282 */
enable_bank(ccsr_gur_t * gur,int bank)283 static void enable_bank(ccsr_gur_t *gur, int bank)
284 {
285 u32 rcw5;
286 u32 temp_lpd_b = srds_lpd_b[bank];
287
288 /*
289 * If we're asked to disable all lanes, just pretend we're doing
290 * that.
291 */
292 if (temp_lpd_b == 0xF)
293 temp_lpd_b = 0xE;
294
295 /*
296 * Enable the lanes SRDS_LPD_Bn. The RCW bits are read-only in
297 * CCSR, and read/write in DSCR.
298 */
299 rcw5 = in_be32(gur->rcwsr + 5);
300 if (bank == FSL_SRDS_BANK_2) {
301 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B2;
302 rcw5 |= temp_lpd_b << 26;
303 } else if (bank == FSL_SRDS_BANK_3) {
304 rcw5 &= ~FSL_CORENET_RCWSRn_SRDS_LPD_B3;
305 rcw5 |= temp_lpd_b << 18;
306 } else {
307 printf("SERDES: enable_bank: bad bank %d\n", bank + 1);
308 return;
309 }
310
311 /* See similar code in cpu/mpc85xx/cpu_init.c for an explanation
312 * of the DCSR mapping.
313 */
314 {
315 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
316 struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS);
317 int law_index;
318 if (law.index == -1)
319 law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS,
320 LAW_SIZE_1M, LAW_TRGT_IF_DCSR);
321 else
322 set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M,
323 LAW_TRGT_IF_DCSR);
324 #endif
325 u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114;
326 out_be32(p, rcw5);
327 #ifdef __DCSR_NOT_DEFINED_BY_CONFIG
328 if (law.index == -1)
329 disable_law(law_index);
330 else
331 set_law(law.index, law.addr, law.size, law.trgt_id);
332 #endif
333 }
334 }
335
336 /*
337 * To avoid problems with clock jitter, rev 2 p4080 uses the pll from
338 * bank 3 to clock banks 2 and 3, as well as a limited selection of
339 * protocol configurations. This requires that banks 2 and 3's lanes be
340 * disabled in the RCW, and enabled with some fixup here to re-enable
341 * them, and to configure bank 2's clock parameters in bank 3's pll in
342 * cases where they differ.
343 */
p4080_erratum_serdes8(serdes_corenet_t * regs,ccsr_gur_t * gur,u32 devdisr,u32 devdisr2,int cfg)344 static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur,
345 u32 devdisr, u32 devdisr2, int cfg)
346 {
347 int srds_ratio_b2;
348 int rfck_sel;
349
350 /*
351 * The disabled lanes of bank 2 will cause the associated
352 * logic blocks to be disabled in DEVDISR. We reverse that here.
353 *
354 * Note that normally it is not permitted to clear DEVDISR bits
355 * once the device has been disabled, but the hardware people
356 * say that this special case is OK.
357 */
358 clrbits_be32(&gur->devdisr, devdisr);
359 clrbits_be32(&gur->devdisr2, devdisr2);
360
361 /*
362 * Some protocols require special handling. There are a few
363 * additional protocol configurations that can be used, which are
364 * not listed here. See app note 4065 for supported protocol
365 * configurations.
366 */
367 switch (cfg) {
368 case 0x19:
369 /*
370 * Bank 2 has PCIe which wants BWSEL -- tell bank 3's PLL.
371 * SGMII on bank 3 should still be usable.
372 */
373 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
374 SRDS_PLLCR1_PLL_BWSEL);
375 break;
376
377 case 0x0f:
378 case 0x10:
379 /*
380 * Banks 2 (XAUI) and 3 (SGMII) have different clocking
381 * requirements in these configurations. Bank 3 cannot
382 * be used and should have its lanes (but not the bank
383 * itself) disabled in the RCW. We set up bank 3's pll
384 * for bank 2's needs here.
385 */
386 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7;
387
388 /* Determine refclock from XAUI ratio */
389 switch (srds_ratio_b2) {
390 case 1: /* 20:1 */
391 rfck_sel = SRDS_PLLCR0_RFCK_SEL_156_25;
392 break;
393 case 2: /* 25:1 */
394 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
395 break;
396 default:
397 printf("SERDES: bad SRDS_RATIO_B2 %d\n",
398 srds_ratio_b2);
399 return;
400 }
401
402 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
403 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
404
405 clrsetbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr0,
406 SRDS_PLLCR0_FRATE_SEL_MASK,
407 SRDS_PLLCR0_FRATE_SEL_6_25);
408 break;
409 }
410
411 enable_bank(gur, FSL_SRDS_BANK_3);
412 }
413 #endif
414
415 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
416 /*
417 * If PCIe is not selected as a protocol for any lanes driven by a given PLL,
418 * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0.
419 */
p4080_erratum_serdes_a005(serdes_corenet_t * regs,unsigned int cfg)420 static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
421 {
422 enum srds_prtcl device;
423
424 switch (cfg) {
425 case 0x13:
426 case 0x16:
427 /*
428 * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL]
429 * to 0.
430 */
431 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
432 SRDS_PLLCR1_PLL_BWSEL);
433 break;
434 case 0x19:
435 /*
436 * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and
437 * SRDSB3PLLCR1[PLLBW_SEL] to 1.
438 */
439 clrbits_be32(®s->bank[FSL_SRDS_BANK_1].pllcr1,
440 SRDS_PLLCR1_PLL_BWSEL);
441 setbits_be32(®s->bank[FSL_SRDS_BANK_3].pllcr1,
442 SRDS_PLLCR1_PLL_BWSEL);
443 break;
444 }
445
446 /*
447 * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI
448 * before XAUI is initialized.
449 */
450 for (device = XAUI_FM1; device <= XAUI_FM2; device++) {
451 if (is_serdes_configured(device)) {
452 int bank = serdes_get_bank_by_device(cfg, device);
453
454 clrbits_be32(®s->bank[bank].pllcr1,
455 SRDS_PLLCR1_PLL_BWSEL);
456 }
457 }
458 }
459 #endif
460
461 /*
462 * Wait for the RSTDONE bit to get set, or a one-second timeout.
463 */
wait_for_rstdone(unsigned int bank)464 static void wait_for_rstdone(unsigned int bank)
465 {
466 serdes_corenet_t *srds_regs =
467 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
468 unsigned long long end_tick;
469 u32 rstctl;
470
471 /* wait for reset complete or 1-second timeout */
472 end_tick = usec2ticks(1000000) + get_ticks();
473 do {
474 rstctl = in_be32(&srds_regs->bank[bank].rstctl);
475 if (rstctl & SRDS_RSTCTL_RSTDONE)
476 break;
477 } while (end_tick > get_ticks());
478
479 if (!(rstctl & SRDS_RSTCTL_RSTDONE))
480 printf("SERDES: timeout resetting bank %u\n", bank + 1);
481 }
482
483
__soc_serdes_init(void)484 static void __soc_serdes_init(void)
485 {
486 /* Allow for SoC-specific initialization in <SOC>_serdes.c */
487 };
488 void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
489
fsl_serdes_init(void)490 void fsl_serdes_init(void)
491 {
492 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
493 int cfg;
494 serdes_corenet_t *srds_regs;
495 #ifdef CONFIG_ARCH_P5040
496 serdes_corenet_t *srds2_regs;
497 #endif
498 int lane, bank, idx;
499 int have_bank[SRDS_MAX_BANK] = {};
500 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
501 u32 serdes8_devdisr = 0;
502 u32 serdes8_devdisr2 = 0;
503 char srds_lpd_opt[16];
504 const char *srds_lpd_arg;
505 size_t arglen;
506 #endif
507 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
508 int need_serdes_a001; /* true == need work-around for SERDES A001 */
509 #endif
510 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
511 char buffer[HWCONFIG_BUFFER_SIZE];
512 char *buf = NULL;
513
514 /*
515 * Extract hwconfig from environment since we have not properly setup
516 * the environment but need it for ddr config params
517 */
518 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
519 buf = buffer;
520 #endif
521 if (serdes_prtcl_map & (1 << NONE))
522 return;
523
524 /* Is serdes enabled at all? */
525 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
526 return;
527
528 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
529 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
530 debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
531
532 if (!is_serdes_prtcl_valid(cfg)) {
533 printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
534 return;
535 }
536
537 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
538 /*
539 * Display a warning if banks two and three are not disabled in the RCW,
540 * since our work-around for SERDES8 depends on these banks being
541 * disabled at power-on.
542 */
543 #define B2_B3 (FSL_CORENET_RCWSRn_SRDS_LPD_B2 | FSL_CORENET_RCWSRn_SRDS_LPD_B3)
544 if ((in_be32(&gur->rcwsr[5]) & B2_B3) != B2_B3) {
545 printf("Warning: SERDES8 requires banks two and "
546 "three to be disabled in the RCW\n");
547 }
548
549 /*
550 * Store the values of the fsl_srds_lpd_b2 and fsl_srds_lpd_b3
551 * hwconfig options into the srds_lpd_b[] array. See README.p4080ds
552 * for a description of these options.
553 */
554 for (bank = 1; bank < ARRAY_SIZE(srds_lpd_b); bank++) {
555 sprintf(srds_lpd_opt, "fsl_srds_lpd_b%u", bank + 1);
556 srds_lpd_arg =
557 hwconfig_subarg_f("serdes", srds_lpd_opt, &arglen, buf);
558 if (srds_lpd_arg)
559 srds_lpd_b[bank] =
560 simple_strtoul(srds_lpd_arg, NULL, 0) & 0xf;
561 }
562
563 if ((cfg == 0xf) || (cfg == 0x10)) {
564 /*
565 * For SERDES protocols 0xF and 0x10, force bank 3 to be
566 * disabled, because it is not supported.
567 */
568 srds_lpd_b[FSL_SRDS_BANK_3] = 0xF;
569 }
570 #endif
571
572 /* Look for banks with all lanes disabled, and power down the bank. */
573 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
574 enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
575 if (serdes_lane_enabled(lane)) {
576 have_bank[serdes_get_bank_by_lane(lane)] = 1;
577 serdes_prtcl_map |= (1 << lane_prtcl);
578 }
579 }
580
581 #ifdef CONFIG_ARCH_P5040
582 /*
583 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
584 * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
585 * to decide whether a protocol is supported on a given lane, so SATA
586 * will be identified as not supported, and therefore not initialized.
587 * So for protocols which use SATA on bank4, we add SATA support in
588 * serdes_prtcl_map.
589 */
590 switch (cfg) {
591 case 0x0:
592 case 0x1:
593 case 0x2:
594 case 0x3:
595 case 0x4:
596 case 0x5:
597 case 0x6:
598 case 0x7:
599 serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
600 break;
601 default:
602 srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
603
604 /* We don't need bank 4, so power it down */
605 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
606 }
607 #endif
608
609 soc_serdes_init();
610
611 /* Set the first bit to indicate serdes has been initialized */
612 serdes_prtcl_map |= (1 << NONE);
613
614 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
615 /*
616 * Bank two uses the clock from bank three, so if bank two is enabled,
617 * then bank three must also be enabled.
618 */
619 if (have_bank[FSL_SRDS_BANK_2])
620 have_bank[FSL_SRDS_BANK_3] = 1;
621 #endif
622
623 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
624 /*
625 * The work-aroud for erratum SERDES-A001 is needed only if bank two
626 * is disabled and bank three is enabled. The converse is also true,
627 * but SERDES8 ensures that bank 3 is always enabled if bank 2 is
628 * enabled, so there's no point in complicating the code to handle
629 * that situation.
630 */
631 need_serdes_a001 =
632 !have_bank[FSL_SRDS_BANK_2] && have_bank[FSL_SRDS_BANK_3];
633 #endif
634
635 /* Power down the banks we're not interested in */
636 for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
637 if (!have_bank[bank]) {
638 printf("SERDES: bank %d disabled\n", bank + 1);
639 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
640 /*
641 * Erratum SERDES-A001 says bank two needs to be powered
642 * down after bank three is powered up, so don't power
643 * down bank two here.
644 */
645 if (!need_serdes_a001 || (bank != FSL_SRDS_BANK_2))
646 setbits_be32(&srds_regs->bank[bank].rstctl,
647 SRDS_RSTCTL_SDPD);
648 #else
649 setbits_be32(&srds_regs->bank[bank].rstctl,
650 SRDS_RSTCTL_SDPD);
651 #endif
652 }
653 }
654
655 #ifdef CONFIG_SYS_FSL_ERRATUM_A004699
656 /*
657 * To avoid the situation that resulted in the P4080 erratum
658 * SERDES-8, a given SerDes bank will use the PLLs from the previous
659 * bank if one of the PLL frequencies is a multiple of the other. For
660 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
661 * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
662 * that, in this situation, lane synchronization is not initiated. So
663 * when we detect a bank with a "borrowed" PLL, we have to manually
664 * initiate lane synchronization.
665 */
666 for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
667 /* Determine the first lane for this bank */
668 unsigned int lane;
669
670 for (lane = 0; lane < SRDS_MAX_LANES; lane++)
671 if (lanes[lane].bank == bank)
672 break;
673 idx = lanes[lane].idx;
674
675 /*
676 * Check if the PLL for the bank is borrowed. The UOTHL
677 * bit of the first lane will tell us that.
678 */
679 if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
680 /* Manually start lane synchronization */
681 setbits_be32(&srds_regs->bank[bank].pllcr0,
682 SRDS_PLLCR0_PVCOCNT_EN);
683 }
684 }
685 #endif
686
687 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
688 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
689 enum srds_prtcl lane_prtcl;
690
691 idx = serdes_get_lane_idx(lane);
692 lane_prtcl = serdes_get_prtcl(cfg, lane);
693
694 #ifdef DEBUG
695 switch (lane) {
696 case 0:
697 puts("Bank1: ");
698 break;
699 case 10:
700 puts("\nBank2: ");
701 break;
702 case 14:
703 puts("\nBank3: ");
704 break;
705 default:
706 break;
707 }
708
709 printf("%s ", serdes_prtcl_str[lane_prtcl]);
710 #endif
711
712 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
713 /*
714 * Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
715 * for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
716 * or AURORA before the device is initialized.
717 *
718 * Note that this part of the SERDES-9 work-around is
719 * redundant if the work-around for A-4580 has already been
720 * applied via PBI.
721 */
722 switch (lane_prtcl) {
723 case SGMII_FM1_DTSEC1:
724 case SGMII_FM1_DTSEC2:
725 case SGMII_FM1_DTSEC3:
726 case SGMII_FM1_DTSEC4:
727 case SGMII_FM2_DTSEC1:
728 case SGMII_FM2_DTSEC2:
729 case SGMII_FM2_DTSEC3:
730 case SGMII_FM2_DTSEC4:
731 case SGMII_FM2_DTSEC5:
732 case XAUI_FM1:
733 case XAUI_FM2:
734 case SRIO1:
735 case SRIO2:
736 case AURORA:
737 out_be32(&srds_regs->lane[idx].ttlcr0,
738 SRDS_TTLCR0_FLT_SEL_KFR_26 |
739 SRDS_TTLCR0_FLT_SEL_KPH_28 |
740 SRDS_TTLCR0_FLT_SEL_750PPM |
741 SRDS_TTLCR0_FREQOVD_EN);
742 break;
743 default:
744 break;
745 }
746 #endif
747
748 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
749 switch (lane_prtcl) {
750 case PCIE1:
751 case PCIE2:
752 case PCIE3:
753 serdes8_devdisr |= FSL_CORENET_DEVDISR_PCIE1 >>
754 (lane_prtcl - PCIE1);
755 break;
756 case SRIO1:
757 case SRIO2:
758 serdes8_devdisr |= FSL_CORENET_DEVDISR_SRIO1 >>
759 (lane_prtcl - SRIO1);
760 break;
761 case SGMII_FM1_DTSEC1:
762 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
763 FSL_CORENET_DEVDISR2_DTSEC1_1;
764 break;
765 case SGMII_FM1_DTSEC2:
766 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
767 FSL_CORENET_DEVDISR2_DTSEC1_2;
768 break;
769 case SGMII_FM1_DTSEC3:
770 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
771 FSL_CORENET_DEVDISR2_DTSEC1_3;
772 break;
773 case SGMII_FM1_DTSEC4:
774 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
775 FSL_CORENET_DEVDISR2_DTSEC1_4;
776 break;
777 case SGMII_FM2_DTSEC1:
778 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
779 FSL_CORENET_DEVDISR2_DTSEC2_1;
780 break;
781 case SGMII_FM2_DTSEC2:
782 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
783 FSL_CORENET_DEVDISR2_DTSEC2_2;
784 break;
785 case SGMII_FM2_DTSEC3:
786 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
787 FSL_CORENET_DEVDISR2_DTSEC2_3;
788 break;
789 case SGMII_FM2_DTSEC4:
790 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
791 FSL_CORENET_DEVDISR2_DTSEC2_4;
792 break;
793 case SGMII_FM2_DTSEC5:
794 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
795 FSL_CORENET_DEVDISR2_DTSEC2_5;
796 break;
797 case XAUI_FM1:
798 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM1 |
799 FSL_CORENET_DEVDISR2_10GEC1;
800 break;
801 case XAUI_FM2:
802 serdes8_devdisr2 |= FSL_CORENET_DEVDISR2_FM2 |
803 FSL_CORENET_DEVDISR2_10GEC2;
804 break;
805 case AURORA:
806 break;
807 default:
808 break;
809 }
810
811 #endif
812 }
813 #endif
814
815 #ifdef DEBUG
816 puts("\n");
817 #endif
818
819 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005
820 p4080_erratum_serdes_a005(srds_regs, cfg);
821 #endif
822
823 for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
824 bank = idx;
825
826 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
827 /*
828 * Change bank init order to 0, 2, 1, so that the third bank's
829 * PLL is established before we start the second bank. The
830 * second bank uses the third bank's PLL.
831 */
832
833 if (idx == 1)
834 bank = FSL_SRDS_BANK_3;
835 else if (idx == 2)
836 bank = FSL_SRDS_BANK_2;
837 #endif
838
839 /* Skip disabled banks */
840 if (!have_bank[bank])
841 continue;
842
843 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
844 if (idx == 1) {
845 /*
846 * Re-enable devices on banks two and three that were
847 * disabled by the RCW, and then enable bank three. The
848 * devices need to be enabled before either bank is
849 * powered up.
850 */
851 p4080_erratum_serdes8(srds_regs, gur, serdes8_devdisr,
852 serdes8_devdisr2, cfg);
853 } else if (idx == 2) {
854 /* Enable bank two now that bank three is enabled. */
855 enable_bank(gur, FSL_SRDS_BANK_2);
856 }
857 #endif
858
859 wait_for_rstdone(bank);
860 }
861
862 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
863 if (need_serdes_a001) {
864 /* Bank 3 has been enabled, so now we can disable bank 2 */
865 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl,
866 SRDS_RSTCTL_SDPD);
867 }
868 #endif
869 }
870
serdes_clock_to_string(u32 clock)871 const char *serdes_clock_to_string(u32 clock)
872 {
873 switch (clock) {
874 case SRDS_PLLCR0_RFCK_SEL_100:
875 return "100";
876 case SRDS_PLLCR0_RFCK_SEL_125:
877 return "125";
878 case SRDS_PLLCR0_RFCK_SEL_156_25:
879 return "156.25";
880 case SRDS_PLLCR0_RFCK_SEL_161_13:
881 return "161.1328123";
882 default:
883 return "150";
884 }
885 }
886
887