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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2007
4  * Sascha Hauer, Pengutronix
5  *
6  * (C) Copyright 2009 Freescale Semiconductor, Inc.
7  */
8 
9 #include <bootm.h>
10 #include <common.h>
11 #include <netdev.h>
12 #include <linux/errno.h>
13 #include <asm/io.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/arch/crm_regs.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <imx_thermal.h>
20 #include <ipu_pixfmt.h>
21 #include <thermal.h>
22 #include <sata.h>
23 
24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h>
26 #endif
27 
28 static u32 reset_cause = -1;
29 
get_imx_reset_cause(void)30 u32 get_imx_reset_cause(void)
31 {
32 	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
33 
34 	if (reset_cause == -1) {
35 		reset_cause = readl(&src_regs->srsr);
36 /* preserve the value for U-Boot proper */
37 #if !defined(CONFIG_SPL_BUILD)
38 		writel(reset_cause, &src_regs->srsr);
39 #endif
40 	}
41 
42 	return reset_cause;
43 }
44 
45 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
get_reset_cause(void)46 static char *get_reset_cause(void)
47 {
48 	switch (get_imx_reset_cause()) {
49 	case 0x00001:
50 	case 0x00011:
51 		return "POR";
52 	case 0x00004:
53 		return "CSU";
54 	case 0x00008:
55 		return "IPP USER";
56 	case 0x00010:
57 #ifdef	CONFIG_MX7
58 		return "WDOG1";
59 #else
60 		return "WDOG";
61 #endif
62 	case 0x00020:
63 		return "JTAG HIGH-Z";
64 	case 0x00040:
65 		return "JTAG SW";
66 	case 0x00080:
67 		return "WDOG3";
68 #ifdef CONFIG_MX7
69 	case 0x00100:
70 		return "WDOG4";
71 	case 0x00200:
72 		return "TEMPSENSE";
73 #elif defined(CONFIG_IMX8M)
74 	case 0x00100:
75 		return "WDOG2";
76 	case 0x00200:
77 		return "TEMPSENSE";
78 #else
79 	case 0x00100:
80 		return "TEMPSENSE";
81 	case 0x10000:
82 		return "WARM BOOT";
83 #endif
84 	default:
85 		return "unknown reset";
86 	}
87 }
88 #endif
89 
90 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
91 
get_imx_type(u32 imxtype)92 const char *get_imx_type(u32 imxtype)
93 {
94 	switch (imxtype) {
95 	case MXC_CPU_IMX8MN:
96 		return "8MNano";/* Quad-core version of the imx8mn */
97 	case MXC_CPU_IMX8MM:
98 		return "8MMQ";	/* Quad-core version of the imx8mm */
99 	case MXC_CPU_IMX8MML:
100 		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
101 	case MXC_CPU_IMX8MMD:
102 		return "8MMD";	/* Dual-core version of the imx8mm */
103 	case MXC_CPU_IMX8MMDL:
104 		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
105 	case MXC_CPU_IMX8MMS:
106 		return "8MMS";	/* Single-core version of the imx8mm */
107 	case MXC_CPU_IMX8MMSL:
108 		return "8MMSL";	/* Single-core Lite version of the imx8mm */
109 	case MXC_CPU_IMX8MQ:
110 		return "8MQ";	/* Quad-core version of the imx8m */
111 	case MXC_CPU_MX7S:
112 		return "7S";	/* Single-core version of the mx7 */
113 	case MXC_CPU_MX7D:
114 		return "7D";	/* Dual-core version of the mx7 */
115 	case MXC_CPU_MX6QP:
116 		return "6QP";	/* Quad-Plus version of the mx6 */
117 	case MXC_CPU_MX6DP:
118 		return "6DP";	/* Dual-Plus version of the mx6 */
119 	case MXC_CPU_MX6Q:
120 		return "6Q";	/* Quad-core version of the mx6 */
121 	case MXC_CPU_MX6D:
122 		return "6D";	/* Dual-core version of the mx6 */
123 	case MXC_CPU_MX6DL:
124 		return "6DL";	/* Dual Lite version of the mx6 */
125 	case MXC_CPU_MX6SOLO:
126 		return "6SOLO";	/* Solo version of the mx6 */
127 	case MXC_CPU_MX6SL:
128 		return "6SL";	/* Solo-Lite version of the mx6 */
129 	case MXC_CPU_MX6SLL:
130 		return "6SLL";	/* SLL version of the mx6 */
131 	case MXC_CPU_MX6SX:
132 		return "6SX";   /* SoloX version of the mx6 */
133 	case MXC_CPU_MX6UL:
134 		return "6UL";   /* Ultra-Lite version of the mx6 */
135 	case MXC_CPU_MX6ULL:
136 		return "6ULL";	/* ULL version of the mx6 */
137 	case MXC_CPU_MX6ULZ:
138 		return "6ULZ";	/* ULZ version of the mx6 */
139 	case MXC_CPU_MX51:
140 		return "51";
141 	case MXC_CPU_MX53:
142 		return "53";
143 	default:
144 		return "??";
145 	}
146 }
147 
print_cpuinfo(void)148 int print_cpuinfo(void)
149 {
150 	u32 cpurev;
151 	__maybe_unused u32 max_freq;
152 
153 	cpurev = get_cpu_rev();
154 
155 #if defined(CONFIG_IMX_THERMAL)
156 	struct udevice *thermal_dev;
157 	int cpu_tmp, minc, maxc, ret;
158 
159 	printf("CPU:   Freescale i.MX%s rev%d.%d",
160 	       get_imx_type((cpurev & 0xFF000) >> 12),
161 	       (cpurev & 0x000F0) >> 4,
162 	       (cpurev & 0x0000F) >> 0);
163 	max_freq = get_cpu_speed_grade_hz();
164 	if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
165 		printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
166 	} else {
167 		printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
168 		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
169 	}
170 #else
171 	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
172 		get_imx_type((cpurev & 0xFF000) >> 12),
173 		(cpurev & 0x000F0) >> 4,
174 		(cpurev & 0x0000F) >> 0,
175 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
176 #endif
177 
178 #if defined(CONFIG_IMX_THERMAL)
179 	puts("CPU:   ");
180 	switch (get_cpu_temp_grade(&minc, &maxc)) {
181 	case TEMP_AUTOMOTIVE:
182 		puts("Automotive temperature grade ");
183 		break;
184 	case TEMP_INDUSTRIAL:
185 		puts("Industrial temperature grade ");
186 		break;
187 	case TEMP_EXTCOMMERCIAL:
188 		puts("Extended Commercial temperature grade ");
189 		break;
190 	default:
191 		puts("Commercial temperature grade ");
192 		break;
193 	}
194 	printf("(%dC to %dC)", minc, maxc);
195 	ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
196 	if (!ret) {
197 		ret = thermal_get_temp(thermal_dev, &cpu_tmp);
198 
199 		if (!ret)
200 			printf(" at %dC\n", cpu_tmp);
201 		else
202 			debug(" - invalid sensor data\n");
203 	} else {
204 		debug(" - invalid sensor device\n");
205 	}
206 #endif
207 
208 	printf("Reset cause: %s\n", get_reset_cause());
209 	return 0;
210 }
211 #endif
212 
cpu_eth_init(bd_t * bis)213 int cpu_eth_init(bd_t *bis)
214 {
215 	int rc = -ENODEV;
216 
217 #if defined(CONFIG_FEC_MXC)
218 	rc = fecmxc_initialize(bis);
219 #endif
220 
221 	return rc;
222 }
223 
224 #ifdef CONFIG_FSL_ESDHC_IMX
225 /*
226  * Initializes on-chip MMC controllers.
227  * to override, implement board_mmc_init()
228  */
cpu_mmc_init(bd_t * bis)229 int cpu_mmc_init(bd_t *bis)
230 {
231 	return fsl_esdhc_mmc_init(bis);
232 }
233 #endif
234 
235 #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
get_ahb_clk(void)236 u32 get_ahb_clk(void)
237 {
238 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
239 	u32 reg, ahb_podf;
240 
241 	reg = __raw_readl(&imx_ccm->cbcdr);
242 	reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
243 	ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
244 
245 	return get_periph_clk() / (ahb_podf + 1);
246 }
247 #endif
248 
arch_preboot_os(void)249 void arch_preboot_os(void)
250 {
251 #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
252 	imx_pcie_remove();
253 #endif
254 #if defined(CONFIG_SATA)
255 	if (!is_mx6sdl()) {
256 		sata_remove(0);
257 #if defined(CONFIG_MX6)
258 		disable_sata_clock();
259 #endif
260 	}
261 #endif
262 #if defined(CONFIG_VIDEO_IPUV3)
263 	/* disable video before launching O/S */
264 	ipuv3_fb_shutdown();
265 #endif
266 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
267 	lcdif_power_down();
268 #endif
269 }
270 
271 #ifndef CONFIG_IMX8M
set_chipselect_size(int const cs_size)272 void set_chipselect_size(int const cs_size)
273 {
274 	unsigned int reg;
275 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
276 	reg = readl(&iomuxc_regs->gpr[1]);
277 
278 	switch (cs_size) {
279 	case CS0_128:
280 		reg &= ~0x7;	/* CS0=128MB, CS1=0, CS2=0, CS3=0 */
281 		reg |= 0x5;
282 		break;
283 	case CS0_64M_CS1_64M:
284 		reg &= ~0x3F;	/* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
285 		reg |= 0x1B;
286 		break;
287 	case CS0_64M_CS1_32M_CS2_32M:
288 		reg &= ~0x1FF;	/* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
289 		reg |= 0x4B;
290 		break;
291 	case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
292 		reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
293 		reg |= 0x249;
294 		break;
295 	default:
296 		printf("Unknown chip select size: %d\n", cs_size);
297 		break;
298 	}
299 
300 	writel(reg, &iomuxc_regs->gpr[1]);
301 }
302 #endif
303 
304 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
305 /*
306  * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
307  * defines a 2-bit SPEED_GRADING
308  */
309 #define OCOTP_TESTER3_SPEED_SHIFT	8
310 enum cpu_speed {
311 	OCOTP_TESTER3_SPEED_GRADE0,
312 	OCOTP_TESTER3_SPEED_GRADE1,
313 	OCOTP_TESTER3_SPEED_GRADE2,
314 	OCOTP_TESTER3_SPEED_GRADE3,
315 };
316 
get_cpu_speed_grade_hz(void)317 u32 get_cpu_speed_grade_hz(void)
318 {
319 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
320 	struct fuse_bank *bank = &ocotp->bank[1];
321 	struct fuse_bank1_regs *fuse =
322 		(struct fuse_bank1_regs *)bank->fuse_regs;
323 	uint32_t val;
324 
325 	val = readl(&fuse->tester3);
326 	val >>= OCOTP_TESTER3_SPEED_SHIFT;
327 	val &= 0x3;
328 
329 	switch(val) {
330 	case OCOTP_TESTER3_SPEED_GRADE0:
331 		return 800000000;
332 	case OCOTP_TESTER3_SPEED_GRADE1:
333 		return is_mx7() ? 500000000 : 1000000000;
334 	case OCOTP_TESTER3_SPEED_GRADE2:
335 		return is_mx7() ? 1000000000 : 1300000000;
336 	case OCOTP_TESTER3_SPEED_GRADE3:
337 		return is_mx7() ? 1200000000 : 1500000000;
338 	}
339 
340 	return 0;
341 }
342 
343 /*
344  * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
345  * defines a 2-bit SPEED_GRADING
346  */
347 #define OCOTP_TESTER3_TEMP_SHIFT	6
348 
get_cpu_temp_grade(int * minc,int * maxc)349 u32 get_cpu_temp_grade(int *minc, int *maxc)
350 {
351 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
352 	struct fuse_bank *bank = &ocotp->bank[1];
353 	struct fuse_bank1_regs *fuse =
354 		(struct fuse_bank1_regs *)bank->fuse_regs;
355 	uint32_t val;
356 
357 	val = readl(&fuse->tester3);
358 	val >>= OCOTP_TESTER3_TEMP_SHIFT;
359 	val &= 0x3;
360 
361 	if (minc && maxc) {
362 		if (val == TEMP_AUTOMOTIVE) {
363 			*minc = -40;
364 			*maxc = 125;
365 		} else if (val == TEMP_INDUSTRIAL) {
366 			*minc = -40;
367 			*maxc = 105;
368 		} else if (val == TEMP_EXTCOMMERCIAL) {
369 			*minc = -20;
370 			*maxc = 105;
371 		} else {
372 			*minc = 0;
373 			*maxc = 95;
374 		}
375 	}
376 	return val;
377 }
378 #endif
379 
380 #if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM)
get_boot_device(void)381 enum boot_device get_boot_device(void)
382 {
383 	struct bootrom_sw_info **p =
384 		(struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
385 
386 	enum boot_device boot_dev = SD1_BOOT;
387 	u8 boot_type = (*p)->boot_dev_type;
388 	u8 boot_instance = (*p)->boot_dev_instance;
389 
390 	switch (boot_type) {
391 	case BOOT_TYPE_SD:
392 		boot_dev = boot_instance + SD1_BOOT;
393 		break;
394 	case BOOT_TYPE_MMC:
395 		boot_dev = boot_instance + MMC1_BOOT;
396 		break;
397 	case BOOT_TYPE_NAND:
398 		boot_dev = NAND_BOOT;
399 		break;
400 	case BOOT_TYPE_QSPI:
401 		boot_dev = QSPI_BOOT;
402 		break;
403 	case BOOT_TYPE_WEIM:
404 		boot_dev = WEIM_NOR_BOOT;
405 		break;
406 	case BOOT_TYPE_SPINOR:
407 		boot_dev = SPI_NOR_BOOT;
408 		break;
409 #ifdef CONFIG_IMX8M
410 	case BOOT_TYPE_USB:
411 		boot_dev = USB_BOOT;
412 		break;
413 #endif
414 	default:
415 		break;
416 	}
417 
418 	return boot_dev;
419 }
420 #endif
421 
422 #ifdef CONFIG_NXP_BOARD_REVISION
nxp_board_rev(void)423 int nxp_board_rev(void)
424 {
425 	/*
426 	 * Get Board ID information from OCOTP_GP1[15:8]
427 	 * RevA: 0x1
428 	 * RevB: 0x2
429 	 * RevC: 0x3
430 	 */
431 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
432 	struct fuse_bank *bank = &ocotp->bank[4];
433 	struct fuse_bank4_regs *fuse =
434 			(struct fuse_bank4_regs *)bank->fuse_regs;
435 
436 	return (readl(&fuse->gp1) >> 8 & 0x0F);
437 }
438 
nxp_board_rev_string(void)439 char nxp_board_rev_string(void)
440 {
441 	const char *rev = "A";
442 
443 	return (*rev + nxp_board_rev() - 1);
444 }
445 #endif
446