1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_nir_to_llvm.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_deref.h"
29 #include "compiler/nir_types.h"
30 #include "si_pipe.h"
31 #include "si_shader_internal.h"
32 #include "tgsi/tgsi_from_mesa.h"
33
tex_get_texture_deref(nir_tex_instr * instr)34 static const nir_deref_instr *tex_get_texture_deref(nir_tex_instr *instr)
35 {
36 for (unsigned i = 0; i < instr->num_srcs; i++) {
37 switch (instr->src[i].src_type) {
38 case nir_tex_src_texture_deref:
39 return nir_src_as_deref(instr->src[i].src);
40 default:
41 break;
42 }
43 }
44
45 return NULL;
46 }
47
scan_io_usage(struct si_shader_info * info,nir_intrinsic_instr * intr,bool is_input)48 static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
49 bool is_input)
50 {
51 unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
52
53 if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {
54 nir_intrinsic_instr *baryc = nir_instr_as_intrinsic(intr->src[0].ssa->parent_instr);
55
56 if (baryc) {
57 if (nir_intrinsic_infos[baryc->intrinsic].index_map[NIR_INTRINSIC_INTERP_MODE] > 0)
58 interp = nir_intrinsic_interp_mode(baryc);
59 else
60 unreachable("unknown barycentric intrinsic");
61 } else {
62 unreachable("unknown barycentric expression");
63 }
64 }
65
66 unsigned mask, bit_size;
67 bool is_output_load;
68
69 if (nir_intrinsic_infos[intr->intrinsic].index_map[NIR_INTRINSIC_WRMASK] > 0) {
70 mask = nir_intrinsic_write_mask(intr); /* store */
71 bit_size = nir_src_bit_size(intr->src[0]);
72 is_output_load = false;
73 } else {
74 mask = nir_ssa_def_components_read(&intr->dest.ssa); /* load */
75 bit_size = intr->dest.ssa.bit_size;
76 is_output_load = !is_input;
77 }
78 assert(bit_size != 64 && !(mask & ~0xf) && "64-bit IO should have been lowered");
79
80 /* Convert the 16-bit component mask to a 32-bit component mask. */
81 if (bit_size == 16) {
82 unsigned new_mask = 0;
83 for (unsigned i = 0; i < 4; i++) {
84 if (mask & (1 << i))
85 new_mask |= 0x1 << (i / 2);
86 }
87 mask = new_mask;
88 }
89
90 mask <<= nir_intrinsic_component(intr);
91
92 nir_src offset = *nir_get_io_offset_src(intr);
93 bool indirect = !nir_src_is_const(offset);
94 if (!indirect)
95 assert(nir_src_as_uint(offset) == 0);
96
97 unsigned semantic = 0;
98 /* VS doesn't have semantics. */
99 if (info->stage != MESA_SHADER_VERTEX || !is_input)
100 semantic = nir_intrinsic_io_semantics(intr).location;
101
102 if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
103 /* Never use FRAG_RESULT_COLOR directly. */
104 if (semantic == FRAG_RESULT_COLOR)
105 semantic = FRAG_RESULT_DATA0;
106 semantic += nir_intrinsic_io_semantics(intr).dual_source_blend_index;
107 }
108
109 unsigned driver_location = nir_intrinsic_base(intr);
110 unsigned num_slots = indirect ? nir_intrinsic_io_semantics(intr).num_slots : 1;
111
112 if (is_input) {
113 assert(driver_location + num_slots <= ARRAY_SIZE(info->input_usage_mask));
114
115 for (unsigned i = 0; i < num_slots; i++) {
116 unsigned loc = driver_location + i;
117
118 info->input_semantic[loc] = semantic + i;
119 info->input_interpolate[loc] = interp;
120
121 if (mask) {
122 info->input_usage_mask[loc] |= mask;
123 info->num_inputs = MAX2(info->num_inputs, loc + 1);
124 }
125 }
126 } else {
127 /* Outputs. */
128 assert(driver_location + num_slots <= ARRAY_SIZE(info->output_usagemask));
129 assert(semantic + num_slots < ARRAY_SIZE(info->output_semantic_to_slot));
130
131 for (unsigned i = 0; i < num_slots; i++) {
132 unsigned loc = driver_location + i;
133
134 info->output_semantic[loc] = semantic + i;
135 info->output_semantic_to_slot[semantic + i] = loc;
136
137 if (is_output_load) {
138 /* Output loads have only a few things that we need to track. */
139 info->output_readmask[loc] |= mask;
140 } else if (mask) {
141 /* Output stores. */
142 unsigned gs_streams = (uint32_t)nir_intrinsic_io_semantics(intr).gs_streams <<
143 (nir_intrinsic_component(intr) * 2);
144 unsigned new_mask = mask & ~info->output_usagemask[loc];
145
146 for (unsigned i = 0; i < 4; i++) {
147 unsigned stream = (gs_streams >> (i * 2)) & 0x3;
148
149 if (new_mask & (1 << i)) {
150 info->output_streams[loc] |= stream << (i * 2);
151 info->num_stream_output_components[stream]++;
152 }
153 }
154
155 if (nir_intrinsic_has_src_type(intr))
156 info->output_type[loc] = nir_intrinsic_src_type(intr);
157 else if (nir_intrinsic_has_dest_type(intr))
158 info->output_type[loc] = nir_intrinsic_dest_type(intr);
159 else
160 info->output_type[loc] = nir_type_float32;
161
162 info->output_usagemask[loc] |= mask;
163 info->num_outputs = MAX2(info->num_outputs, loc + 1);
164
165 if (info->stage == MESA_SHADER_FRAGMENT &&
166 semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
167 unsigned index = semantic - FRAG_RESULT_DATA0;
168
169 if (nir_intrinsic_src_type(intr) == nir_type_float16)
170 info->output_color_types |= SI_TYPE_FLOAT16 << (index * 2);
171 else if (nir_intrinsic_src_type(intr) == nir_type_int16)
172 info->output_color_types |= SI_TYPE_INT16 << (index * 2);
173 else if (nir_intrinsic_src_type(intr) == nir_type_uint16)
174 info->output_color_types |= SI_TYPE_UINT16 << (index * 2);
175 }
176 }
177 }
178 }
179 }
180
scan_instruction(const struct nir_shader * nir,struct si_shader_info * info,nir_instr * instr)181 static void scan_instruction(const struct nir_shader *nir, struct si_shader_info *info,
182 nir_instr *instr)
183 {
184 if (instr->type == nir_instr_type_tex) {
185 nir_tex_instr *tex = nir_instr_as_tex(instr);
186 const nir_deref_instr *deref = tex_get_texture_deref(tex);
187 nir_variable *var = deref ? nir_deref_instr_get_variable(deref) : NULL;
188
189 if (var) {
190 if (var->data.mode != nir_var_uniform || var->data.bindless)
191 info->uses_bindless_samplers = true;
192 }
193 } else if (instr->type == nir_instr_type_intrinsic) {
194 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
195
196 switch (intr->intrinsic) {
197 case nir_intrinsic_load_local_invocation_id:
198 case nir_intrinsic_load_work_group_id: {
199 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
200 while (mask) {
201 unsigned i = u_bit_scan(&mask);
202
203 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
204 info->uses_block_id[i] = true;
205 else
206 info->uses_thread_id[i] = true;
207 }
208 break;
209 }
210 case nir_intrinsic_bindless_image_load:
211 case nir_intrinsic_bindless_image_size:
212 case nir_intrinsic_bindless_image_samples:
213 info->uses_bindless_images = true;
214 break;
215 case nir_intrinsic_bindless_image_store:
216 info->uses_bindless_images = true;
217 info->num_memory_stores++;
218 break;
219 case nir_intrinsic_image_deref_store:
220 info->num_memory_stores++;
221 break;
222 case nir_intrinsic_bindless_image_atomic_add:
223 case nir_intrinsic_bindless_image_atomic_imin:
224 case nir_intrinsic_bindless_image_atomic_umin:
225 case nir_intrinsic_bindless_image_atomic_imax:
226 case nir_intrinsic_bindless_image_atomic_umax:
227 case nir_intrinsic_bindless_image_atomic_and:
228 case nir_intrinsic_bindless_image_atomic_or:
229 case nir_intrinsic_bindless_image_atomic_xor:
230 case nir_intrinsic_bindless_image_atomic_exchange:
231 case nir_intrinsic_bindless_image_atomic_comp_swap:
232 case nir_intrinsic_bindless_image_atomic_inc_wrap:
233 case nir_intrinsic_bindless_image_atomic_dec_wrap:
234 info->uses_bindless_images = true;
235 info->num_memory_stores++;
236 break;
237 case nir_intrinsic_image_deref_atomic_add:
238 case nir_intrinsic_image_deref_atomic_imin:
239 case nir_intrinsic_image_deref_atomic_umin:
240 case nir_intrinsic_image_deref_atomic_imax:
241 case nir_intrinsic_image_deref_atomic_umax:
242 case nir_intrinsic_image_deref_atomic_and:
243 case nir_intrinsic_image_deref_atomic_or:
244 case nir_intrinsic_image_deref_atomic_xor:
245 case nir_intrinsic_image_deref_atomic_exchange:
246 case nir_intrinsic_image_deref_atomic_comp_swap:
247 case nir_intrinsic_image_deref_atomic_inc_wrap:
248 case nir_intrinsic_image_deref_atomic_dec_wrap:
249 info->num_memory_stores++;
250 break;
251 case nir_intrinsic_store_ssbo:
252 case nir_intrinsic_ssbo_atomic_add:
253 case nir_intrinsic_ssbo_atomic_imin:
254 case nir_intrinsic_ssbo_atomic_umin:
255 case nir_intrinsic_ssbo_atomic_imax:
256 case nir_intrinsic_ssbo_atomic_umax:
257 case nir_intrinsic_ssbo_atomic_and:
258 case nir_intrinsic_ssbo_atomic_or:
259 case nir_intrinsic_ssbo_atomic_xor:
260 case nir_intrinsic_ssbo_atomic_exchange:
261 case nir_intrinsic_ssbo_atomic_comp_swap:
262 info->num_memory_stores++;
263 break;
264 case nir_intrinsic_load_color0:
265 case nir_intrinsic_load_color1: {
266 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
267 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
268 info->colors_read |= mask << (index * 4);
269 break;
270 }
271 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
272 case nir_intrinsic_load_barycentric_at_sample: /* uses center */
273 if (nir_intrinsic_interp_mode(intr) == INTERP_MODE_FLAT)
274 break;
275
276 if (nir_intrinsic_interp_mode(intr) == INTERP_MODE_NOPERSPECTIVE) {
277 info->uses_linear_center = true;
278 } else {
279 info->uses_persp_center = true;
280 }
281 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
282 info->uses_interp_at_sample = true;
283 break;
284 case nir_intrinsic_load_input:
285 case nir_intrinsic_load_per_vertex_input:
286 case nir_intrinsic_load_input_vertex:
287 case nir_intrinsic_load_interpolated_input:
288 scan_io_usage(info, intr, true);
289 break;
290 case nir_intrinsic_load_output:
291 case nir_intrinsic_load_per_vertex_output:
292 case nir_intrinsic_store_output:
293 case nir_intrinsic_store_per_vertex_output:
294 scan_io_usage(info, intr, false);
295 break;
296 case nir_intrinsic_load_deref:
297 case nir_intrinsic_store_deref:
298 case nir_intrinsic_interp_deref_at_centroid:
299 case nir_intrinsic_interp_deref_at_sample:
300 case nir_intrinsic_interp_deref_at_offset:
301 unreachable("these opcodes should have been lowered");
302 break;
303 default:
304 break;
305 }
306 }
307 }
308
si_nir_scan_shader(const struct nir_shader * nir,struct si_shader_info * info)309 void si_nir_scan_shader(const struct nir_shader *nir, struct si_shader_info *info)
310 {
311 nir_function *func;
312
313 info->base = nir->info;
314 info->stage = nir->info.stage;
315
316 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
317 if (info->base.tess.primitive_mode == GL_ISOLINES)
318 info->base.tess.primitive_mode = GL_LINES;
319 }
320
321 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
322 /* post_depth_coverage implies early_fragment_tests */
323 info->base.fs.early_fragment_tests |= info->base.fs.post_depth_coverage;
324
325 info->color_interpolate[0] = nir->info.fs.color0_interp;
326 info->color_interpolate[1] = nir->info.fs.color1_interp;
327 for (unsigned i = 0; i < 2; i++) {
328 if (info->color_interpolate[i] == INTERP_MODE_NONE)
329 info->color_interpolate[i] = INTERP_MODE_COLOR;
330 }
331
332 info->color_interpolate_loc[0] = nir->info.fs.color0_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
333 nir->info.fs.color0_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
334 TGSI_INTERPOLATE_LOC_CENTER;
335 info->color_interpolate_loc[1] = nir->info.fs.color1_sample ? TGSI_INTERPOLATE_LOC_SAMPLE :
336 nir->info.fs.color1_centroid ? TGSI_INTERPOLATE_LOC_CENTROID :
337 TGSI_INTERPOLATE_LOC_CENTER;
338 }
339
340 info->constbuf0_num_slots = nir->num_uniforms;
341
342 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
343 info->tessfactors_are_def_in_all_invocs = ac_are_tessfactors_def_in_all_invocs(nir);
344 }
345
346 info->uses_frontface = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
347 info->uses_instanceid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID);
348 info->uses_invocationid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID);
349 info->uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORK_GROUPS);
350 info->uses_subgroup_info = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_INVOCATION_INDEX) ||
351 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) ||
352 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS);
353 info->uses_variable_block_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_GROUP_SIZE);
354 info->uses_drawid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID);
355 info->uses_primid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
356 nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID;
357 info->reads_samplemask = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN);
358 info->reads_tess_factors = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_INNER) ||
359 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_TESS_LEVEL_OUTER);
360 info->uses_linear_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
361 info->uses_linear_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
362 info->uses_linear_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
363 info->uses_persp_sample = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
364 info->uses_persp_centroid = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
365 info->uses_persp_center = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
366
367 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
368 info->writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH);
369 info->writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL);
370 info->writes_samplemask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
371
372 info->colors_written = nir->info.outputs_written >> FRAG_RESULT_DATA0;
373 if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR)) {
374 info->color0_writes_all_cbufs = true;
375 info->colors_written |= 0x1;
376 }
377 if (nir->info.fs.color_is_dual_source)
378 info->colors_written |= 0x2;
379 } else {
380 info->writes_primid = nir->info.outputs_written & VARYING_BIT_PRIMITIVE_ID;
381 info->writes_viewport_index = nir->info.outputs_written & VARYING_BIT_VIEWPORT;
382 info->writes_layer = nir->info.outputs_written & VARYING_BIT_LAYER;
383 info->writes_psize = nir->info.outputs_written & VARYING_BIT_PSIZ;
384 info->writes_clipvertex = nir->info.outputs_written & VARYING_BIT_CLIP_VERTEX;
385 info->writes_edgeflag = nir->info.outputs_written & VARYING_BIT_EDGE;
386 info->writes_position = nir->info.outputs_written & VARYING_BIT_POS;
387 }
388
389 memset(info->output_semantic_to_slot, -1, sizeof(info->output_semantic_to_slot));
390
391 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
392 nir_foreach_block (block, func->impl) {
393 nir_foreach_instr (instr, block)
394 scan_instruction(nir, info, instr);
395 }
396
397 /* Add color inputs to the list of inputs. */
398 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
399 for (unsigned i = 0; i < 2; i++) {
400 if ((info->colors_read >> (i * 4)) & 0xf) {
401 info->input_semantic[info->num_inputs] = VARYING_SLOT_COL0 + i;
402 info->input_interpolate[info->num_inputs] = info->color_interpolate[i];
403 info->input_usage_mask[info->num_inputs] = info->colors_read >> (i * 4);
404 info->num_inputs++;
405 }
406 }
407 }
408
409 /* Trim output read masks based on write masks. */
410 for (unsigned i = 0; i < info->num_outputs; i++)
411 info->output_readmask[i] &= info->output_usagemask[i];
412 }
413
si_alu_to_scalar_filter(const nir_instr * instr,const void * data)414 static bool si_alu_to_scalar_filter(const nir_instr *instr, const void *data)
415 {
416 struct si_screen *sscreen = (struct si_screen *)data;
417
418 if (sscreen->info.has_packed_math_16bit &&
419 instr->type == nir_instr_type_alu) {
420 nir_alu_instr *alu = nir_instr_as_alu(instr);
421
422 if (alu->dest.dest.is_ssa &&
423 alu->dest.dest.ssa.bit_size == 16 &&
424 alu->dest.dest.ssa.num_components == 2)
425 return false;
426 }
427
428 return true;
429 }
430
si_nir_opts(struct si_screen * sscreen,struct nir_shader * nir,bool first)431 void si_nir_opts(struct si_screen *sscreen, struct nir_shader *nir, bool first)
432 {
433 bool progress;
434
435 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
436 NIR_PASS_V(nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen);
437 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
438
439 do {
440 progress = false;
441 bool lower_alu_to_scalar = false;
442 bool lower_phis_to_scalar = false;
443
444 if (first) {
445 NIR_PASS(progress, nir, nir_split_array_vars, nir_var_function_temp);
446 NIR_PASS(lower_alu_to_scalar, nir, nir_shrink_vec_array_vars, nir_var_function_temp);
447 NIR_PASS(progress, nir, nir_opt_find_array_copies);
448 }
449 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
450 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
451
452 NIR_PASS(lower_alu_to_scalar, nir, nir_opt_trivial_continues);
453 /* (Constant) copy propagation is needed for txf with offsets. */
454 NIR_PASS(progress, nir, nir_copy_prop);
455 NIR_PASS(progress, nir, nir_opt_remove_phis);
456 NIR_PASS(progress, nir, nir_opt_dce);
457 NIR_PASS(lower_phis_to_scalar, nir, nir_opt_if, true);
458 NIR_PASS(progress, nir, nir_opt_dead_cf);
459
460 if (lower_alu_to_scalar)
461 NIR_PASS_V(nir, nir_lower_alu_to_scalar, si_alu_to_scalar_filter, sscreen);
462 if (lower_phis_to_scalar)
463 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
464 progress |= lower_alu_to_scalar | lower_phis_to_scalar;
465
466 NIR_PASS(progress, nir, nir_opt_cse);
467 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
468
469 /* Needed for algebraic lowering */
470 NIR_PASS(progress, nir, nir_opt_algebraic);
471 NIR_PASS(progress, nir, nir_opt_constant_folding);
472
473 if (!nir->info.flrp_lowered) {
474 unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) |
475 (nir->options->lower_flrp32 ? 32 : 0) |
476 (nir->options->lower_flrp64 ? 64 : 0);
477 assert(lower_flrp);
478 bool lower_flrp_progress = false;
479
480 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */);
481 if (lower_flrp_progress) {
482 NIR_PASS(progress, nir, nir_opt_constant_folding);
483 progress = true;
484 }
485
486 /* Nothing should rematerialize any flrps, so we only
487 * need to do this lowering once.
488 */
489 nir->info.flrp_lowered = true;
490 }
491
492 NIR_PASS(progress, nir, nir_opt_undef);
493 NIR_PASS(progress, nir, nir_opt_conditional_discard);
494 if (nir->options->max_unroll_iterations) {
495 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
496 }
497
498 if (sscreen->info.has_packed_math_16bit)
499 NIR_PASS(progress, nir, nir_opt_vectorize, NULL, NULL);
500 } while (progress);
501
502 NIR_PASS_V(nir, nir_lower_var_copies);
503 }
504
type_size_vec4(const struct glsl_type * type,bool bindless)505 static int type_size_vec4(const struct glsl_type *type, bool bindless)
506 {
507 return glsl_count_attribute_slots(type, false);
508 }
509
si_nir_lower_color(nir_shader * nir)510 static void si_nir_lower_color(nir_shader *nir)
511 {
512 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
513
514 nir_builder b;
515 nir_builder_init(&b, entrypoint);
516
517 nir_foreach_block (block, entrypoint) {
518 nir_foreach_instr_safe (instr, block) {
519 if (instr->type != nir_instr_type_intrinsic)
520 continue;
521
522 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
523
524 if (intrin->intrinsic != nir_intrinsic_load_deref)
525 continue;
526
527 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
528 if (!nir_deref_mode_is(deref, nir_var_shader_in))
529 continue;
530
531 b.cursor = nir_before_instr(instr);
532 nir_variable *var = nir_deref_instr_get_variable(deref);
533 nir_ssa_def *def;
534
535 if (var->data.location == VARYING_SLOT_COL0) {
536 def = nir_load_color0(&b);
537 nir->info.fs.color0_interp = var->data.interpolation;
538 nir->info.fs.color0_sample = var->data.sample;
539 nir->info.fs.color0_centroid = var->data.centroid;
540 } else if (var->data.location == VARYING_SLOT_COL1) {
541 def = nir_load_color1(&b);
542 nir->info.fs.color1_interp = var->data.interpolation;
543 nir->info.fs.color1_sample = var->data.sample;
544 nir->info.fs.color1_centroid = var->data.centroid;
545 } else {
546 continue;
547 }
548
549 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
550 nir_instr_remove(instr);
551 }
552 }
553 }
554
si_lower_io(struct nir_shader * nir)555 static void si_lower_io(struct nir_shader *nir)
556 {
557 /* HW supports indirect indexing for: | Enabled in driver
558 * -------------------------------------------------------
559 * VS inputs | No
560 * TCS inputs | Yes
561 * TES inputs | Yes
562 * GS inputs | No
563 * -------------------------------------------------------
564 * VS outputs before TCS | No
565 * VS outputs before GS | No
566 * TCS outputs | Yes
567 * TES outputs before GS | No
568 */
569 bool has_indirect_inputs = nir->info.stage == MESA_SHADER_TESS_CTRL ||
570 nir->info.stage == MESA_SHADER_TESS_EVAL;
571 bool has_indirect_outputs = nir->info.stage == MESA_SHADER_TESS_CTRL;
572
573 if (!has_indirect_inputs || !has_indirect_outputs) {
574 NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir),
575 !has_indirect_outputs, !has_indirect_inputs);
576
577 /* Since we're doing nir_lower_io_to_temporaries late, we need
578 * to lower all the copy_deref's introduced by
579 * lower_io_to_temporaries before calling nir_lower_io.
580 */
581 NIR_PASS_V(nir, nir_split_var_copies);
582 NIR_PASS_V(nir, nir_lower_var_copies);
583 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
584 }
585
586 /* The vectorization must be done after nir_lower_io_to_temporaries, because
587 * nir_lower_io_to_temporaries after vectorization breaks:
588 * piglit/bin/arb_gpu_shader5-interpolateAtOffset -auto -fbo
589 * TODO: It's probably a bug in nir_lower_io_to_temporaries.
590 *
591 * The vectorizer can only vectorize this:
592 * op src0.x, src1.x
593 * op src0.y, src1.y
594 *
595 * So it requires that inputs are already vectors and it must be the same
596 * vector between instructions. The vectorizer doesn't create vectors
597 * from independent scalar sources, so vectorize inputs.
598 *
599 * TODO: The pass fails this for VS: assert(b.shader->info.stage != MESA_SHADER_VERTEX);
600 */
601 if (nir->info.stage != MESA_SHADER_VERTEX)
602 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_in);
603
604 /* Vectorize outputs, so that we don't split vectors before storing outputs. */
605 /* TODO: The pass fails an assertion for other shader stages. */
606 if (nir->info.stage == MESA_SHADER_TESS_CTRL ||
607 nir->info.stage == MESA_SHADER_FRAGMENT)
608 NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
609
610 if (nir->info.stage == MESA_SHADER_FRAGMENT)
611 si_nir_lower_color(nir);
612
613 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_out | nir_var_shader_in,
614 type_size_vec4, nir_lower_io_lower_64bit_to_32);
615 nir->info.io_lowered = true;
616
617 /* This pass needs actual constants */
618 NIR_PASS_V(nir, nir_opt_constant_folding);
619 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in |
620 nir_var_shader_out);
621
622 /* Remove dead derefs, so that nir_validate doesn't fail. */
623 NIR_PASS_V(nir, nir_opt_dce);
624
625 /* Remove input and output nir_variables, because we don't need them
626 * anymore. Also remove uniforms, because those should have been lowered
627 * to UBOs already.
628 */
629 unsigned modes = nir_var_shader_in | nir_var_shader_out | nir_var_uniform;
630 nir_foreach_variable_with_modes_safe(var, nir, modes) {
631 if (var->data.mode == nir_var_uniform &&
632 (glsl_type_get_image_count(var->type) ||
633 glsl_type_get_sampler_count(var->type)))
634 continue;
635
636 exec_node_remove(&var->node);
637 }
638 }
639
640 /**
641 * Perform "lowering" operations on the NIR that are run once when the shader
642 * selector is created.
643 */
si_lower_nir(struct si_screen * sscreen,struct nir_shader * nir)644 static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
645 {
646 /* Perform lowerings (and optimizations) of code.
647 *
648 * Performance considerations aside, we must:
649 * - lower certain ALU operations
650 * - ensure constant offsets for texture instructions are folded
651 * and copy-propagated
652 */
653
654 static const struct nir_lower_tex_options lower_tex_options = {
655 .lower_txp = ~0u,
656 };
657 NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options);
658
659 const nir_lower_subgroups_options subgroups_options = {
660 .subgroup_size = 64,
661 .ballot_bit_size = 64,
662 .lower_to_scalar = true,
663 .lower_subgroup_masks = true,
664 .lower_vote_trivial = false,
665 .lower_vote_eq_to_ballot = true,
666 .lower_elect = true,
667 };
668 NIR_PASS_V(nir, nir_lower_subgroups, &subgroups_options);
669
670 /* Lower load constants to scalar and then clean up the mess */
671 NIR_PASS_V(nir, nir_lower_load_const_to_scalar);
672 NIR_PASS_V(nir, nir_lower_var_copies);
673 NIR_PASS_V(nir, nir_opt_intrinsics);
674 NIR_PASS_V(nir, nir_lower_system_values);
675 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL);
676
677 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
678 sscreen->info.has_packed_math_16bit &&
679 sscreen->b.get_shader_param(&sscreen->b, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_FP16))
680 NIR_PASS_V(nir, nir_lower_mediump_outputs);
681
682 si_nir_opts(sscreen, nir, true);
683
684 /* Lower large variables that are always constant with load_constant
685 * intrinsics, which get turned into PC-relative loads from a data
686 * section next to the shader.
687 *
688 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
689 */
690 bool changed = false;
691 if (!nir->constant_data) {
692 /* The pass crashes if there are dead temps of lowered IO interface types. */
693 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
694 NIR_PASS(changed, nir, nir_opt_large_constants, glsl_get_natural_size_align_bytes, 16);
695 }
696
697 changed |= ac_lower_indirect_derefs(nir, sscreen->info.chip_class);
698 if (changed)
699 si_nir_opts(sscreen, nir, false);
700
701 /* Run late optimizations to fuse ffma. */
702 bool more_late_algebraic = true;
703 while (more_late_algebraic) {
704 more_late_algebraic = false;
705 NIR_PASS(more_late_algebraic, nir, nir_opt_algebraic_late);
706 NIR_PASS_V(nir, nir_opt_constant_folding);
707 NIR_PASS_V(nir, nir_copy_prop);
708 NIR_PASS_V(nir, nir_opt_dce);
709 NIR_PASS_V(nir, nir_opt_cse);
710 }
711
712 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL);
713
714 if (sscreen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
715 NIR_PASS_V(nir, nir_lower_discard_to_demote);
716 }
717
si_finalize_nir(struct pipe_screen * screen,void * nirptr,bool optimize)718 void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize)
719 {
720 struct si_screen *sscreen = (struct si_screen *)screen;
721 struct nir_shader *nir = (struct nir_shader *)nirptr;
722
723 si_lower_io(nir);
724 si_lower_nir(sscreen, nir);
725 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
726
727 if (sscreen->options.inline_uniforms)
728 nir_find_inlinable_uniforms(nir);
729 }
730