1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor
4 * Copyright 2019 NXP
5 */
6
7 #include <common.h>
8 #include <env.h>
9 #include <fsl_immap.h>
10 #include <fsl_ifc.h>
11 #include <init.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/soc.h>
14 #include <asm/io.h>
15 #include <asm/global_data.h>
16 #include <asm/arch-fsl-layerscape/config.h>
17 #include <asm/arch-fsl-layerscape/ns_access.h>
18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
19 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
20 #include <fsl_csu.h>
21 #endif
22 #ifdef CONFIG_SYS_FSL_DDR
23 #include <fsl_ddr_sdram.h>
24 #include <fsl_ddr.h>
25 #endif
26 #ifdef CONFIG_CHAIN_OF_TRUST
27 #include <fsl_validate.h>
28 #endif
29 #include <fsl_immap.h>
30 #ifdef CONFIG_TFABOOT
31 #include <env_internal.h>
32 DECLARE_GLOBAL_DATA_PTR;
33 #endif
34
soc_has_dp_ddr(void)35 bool soc_has_dp_ddr(void)
36 {
37 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
38 u32 svr = gur_in32(&gur->svr);
39
40 /* LS2085A, LS2088A, LS2048A has DP_DDR */
41 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
42 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
43 (SVR_SOC_VER(svr) == SVR_LS2048A))
44 return true;
45
46 return false;
47 }
48
soc_has_aiop(void)49 bool soc_has_aiop(void)
50 {
51 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
52 u32 svr = gur_in32(&gur->svr);
53
54 /* LS2085A has AIOP */
55 if (SVR_SOC_VER(svr) == SVR_LS2085A)
56 return true;
57
58 return false;
59 }
60
set_usb_txvreftune(u32 __iomem * scfg,u32 offset)61 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
62 {
63 scfg_clrsetbits32(scfg + offset / 4,
64 0xF << 6,
65 SCFG_USB_TXVREFTUNE << 6);
66 }
67
erratum_a009008(void)68 static void erratum_a009008(void)
69 {
70 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
71 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
72
73 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
74 defined(CONFIG_ARCH_LS1012A)
75 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
76 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
77 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
78 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
79 #endif
80 #elif defined(CONFIG_ARCH_LS2080A)
81 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
82 #endif
83 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
84 }
85
set_usb_sqrxtune(u32 __iomem * scfg,u32 offset)86 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
87 {
88 scfg_clrbits32(scfg + offset / 4,
89 SCFG_USB_SQRXTUNE_MASK << 23);
90 }
91
erratum_a009798(void)92 static void erratum_a009798(void)
93 {
94 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
95 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
96
97 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
98 defined(CONFIG_ARCH_LS1012A)
99 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
100 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
101 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
102 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
103 #endif
104 #elif defined(CONFIG_ARCH_LS2080A)
105 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
106 #endif
107 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
108 }
109
110 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
111 defined(CONFIG_ARCH_LS1012A)
set_usb_pcstxswingfull(u32 __iomem * scfg,u32 offset)112 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
113 {
114 scfg_clrsetbits32(scfg + offset / 4,
115 0x7F << 9,
116 SCFG_USB_PCSTXSWINGFULL << 9);
117 }
118 #endif
119
erratum_a008997(void)120 static void erratum_a008997(void)
121 {
122 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
123 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
124 defined(CONFIG_ARCH_LS1012A)
125 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
126
127 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
128 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
129 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
130 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
131 #endif
132 #elif defined(CONFIG_ARCH_LS1028A)
133 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
134 0x7F << 11,
135 DCSR_USB_PCSTXSWINGFULL << 11);
136 #endif
137 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
138 }
139
140 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
141 defined(CONFIG_ARCH_LS1012A)
142
143 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
144 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
145 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
146 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
147 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
148
149 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
150 defined(CONFIG_ARCH_LS1028A)
151
152 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
153 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
154 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
155 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
156 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
157
158 #endif
159
erratum_a009007(void)160 static void erratum_a009007(void)
161 {
162 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
163 defined(CONFIG_ARCH_LS1012A)
164 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
165
166 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
167 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
168 usb_phy = (void __iomem *)SCFG_USB_PHY2;
169 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
170
171 usb_phy = (void __iomem *)SCFG_USB_PHY3;
172 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
173 #endif
174 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
175 defined(CONFIG_ARCH_LS1028A)
176 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
177
178 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
179 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
180 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
181 }
182
183 #if defined(CONFIG_FSL_LSCH3)
184 /*
185 * This erratum requires setting a value to eddrtqcr1 to
186 * optimal the DDR performance.
187 */
erratum_a008336(void)188 static void erratum_a008336(void)
189 {
190 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
191 u32 *eddrtqcr1;
192
193 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
194 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
195 if (fsl_ddr_get_version(0) == 0x50200)
196 out_le32(eddrtqcr1, 0x63b30002);
197 #endif
198 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
199 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
200 if (fsl_ddr_get_version(0) == 0x50200)
201 out_le32(eddrtqcr1, 0x63b30002);
202 #endif
203 #endif
204 }
205
206 /*
207 * This erratum requires a register write before being Memory
208 * controller 3 being enabled.
209 */
erratum_a008514(void)210 static void erratum_a008514(void)
211 {
212 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
213 u32 *eddrtqcr1;
214
215 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
216 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
217 out_le32(eddrtqcr1, 0x63b20002);
218 #endif
219 #endif
220 }
221 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
222 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
223
get_internval_val_mhz(void)224 static unsigned long get_internval_val_mhz(void)
225 {
226 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
227 /*
228 * interval is the number of platform cycles(MHz) between
229 * wake up events generated by EPU.
230 */
231 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
232
233 if (interval)
234 interval_mhz = simple_strtoul(interval, NULL, 10);
235
236 return interval_mhz;
237 }
238
erratum_a009635(void)239 void erratum_a009635(void)
240 {
241 u32 val;
242 unsigned long interval_mhz = get_internval_val_mhz();
243
244 if (!interval_mhz)
245 return;
246
247 val = in_le32(DCSR_CGACRE5);
248 writel(val | 0x00000200, DCSR_CGACRE5);
249
250 val = in_le32(EPU_EPCMPR5);
251 writel(interval_mhz, EPU_EPCMPR5);
252 val = in_le32(EPU_EPCCR5);
253 writel(val | 0x82820000, EPU_EPCCR5);
254 val = in_le32(EPU_EPSMCR5);
255 writel(val | 0x002f0000, EPU_EPSMCR5);
256 val = in_le32(EPU_EPECR5);
257 writel(val | 0x20000000, EPU_EPECR5);
258 val = in_le32(EPU_EPGCR);
259 writel(val | 0x80000000, EPU_EPGCR);
260 }
261 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
262
erratum_rcw_src(void)263 static void erratum_rcw_src(void)
264 {
265 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
266 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
267 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
268 u32 val;
269
270 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
271 val &= ~DCFG_PORSR1_RCW_SRC;
272 val |= DCFG_PORSR1_RCW_SRC_NOR;
273 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
274 #endif
275 }
276
277 #define I2C_DEBUG_REG 0x6
278 #define I2C_GLITCH_EN 0x8
279 /*
280 * This erratum requires setting glitch_en bit to enable
281 * digital glitch filter to improve clock stability.
282 */
283 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203(void)284 static void erratum_a009203(void)
285 {
286 #ifdef CONFIG_SYS_I2C
287 u8 __iomem *ptr;
288 #ifdef I2C1_BASE_ADDR
289 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
290
291 writeb(I2C_GLITCH_EN, ptr);
292 #endif
293 #ifdef I2C2_BASE_ADDR
294 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
295
296 writeb(I2C_GLITCH_EN, ptr);
297 #endif
298 #ifdef I2C3_BASE_ADDR
299 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
300
301 writeb(I2C_GLITCH_EN, ptr);
302 #endif
303 #ifdef I2C4_BASE_ADDR
304 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
305
306 writeb(I2C_GLITCH_EN, ptr);
307 #endif
308 #endif
309 }
310 #endif
311
bypass_smmu(void)312 void bypass_smmu(void)
313 {
314 u32 val;
315 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
316 out_le32(SMMU_SCR0, val);
317 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
318 out_le32(SMMU_NSCR0, val);
319 }
fsl_lsch3_early_init_f(void)320 void fsl_lsch3_early_init_f(void)
321 {
322 erratum_rcw_src();
323 #ifdef CONFIG_FSL_IFC
324 init_early_memctl_regs(); /* tighten IFC timing */
325 #endif
326 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
327 erratum_a009203();
328 #endif
329 erratum_a008514();
330 erratum_a008336();
331 erratum_a009008();
332 erratum_a009798();
333 erratum_a008997();
334 erratum_a009007();
335 #ifdef CONFIG_CHAIN_OF_TRUST
336 /* In case of Secure Boot, the IBR configures the SMMU
337 * to allow only Secure transactions.
338 * SMMU must be reset in bypass mode.
339 * Set the ClientPD bit and Clear the USFCFG Bit
340 */
341 if (fsl_check_boot_mode_secure() == 1)
342 bypass_smmu();
343 #endif
344
345 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
346 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
347 set_icids();
348 #endif
349 }
350
351 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)352 int get_core_volt_from_fuse(void)
353 {
354 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
355 int vdd;
356 u32 fusesr;
357 u8 vid;
358
359 /* get the voltage ID from fuse status register */
360 fusesr = in_le32(&gur->dcfg_fusesr);
361 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
362 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
363 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
364 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
365 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
366 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
367 }
368 debug("%s: VID = 0x%x\n", __func__, vid);
369 switch (vid) {
370 case 0x00: /* VID isn't supported */
371 vdd = -EINVAL;
372 debug("%s: The VID feature is not supported\n", __func__);
373 break;
374 case 0x08: /* 0.9V silicon */
375 vdd = 900;
376 break;
377 case 0x10: /* 1.0V silicon */
378 vdd = 1000;
379 break;
380 default: /* Other core voltage */
381 vdd = -EINVAL;
382 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
383 break;
384 }
385 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
386
387 return vdd;
388 }
389
390 #elif defined(CONFIG_FSL_LSCH2)
391
erratum_a009929(void)392 static void erratum_a009929(void)
393 {
394 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
395 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
396 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
397 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
398
399 rstrqmr1 |= 0x00000400;
400 gur_out32(&gur->rstrqmr1, rstrqmr1);
401 writel(0x01000000, dcsr_cop_ccp);
402 #endif
403 }
404
405 /*
406 * This erratum requires setting a value to eddrtqcr1 to optimal
407 * the DDR performance. The eddrtqcr1 register is in SCFG space
408 * of LS1043A and the offset is 0x157_020c.
409 */
410 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
411 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
412 #error A009660 and A008514 can not be both enabled.
413 #endif
414
erratum_a009660(void)415 static void erratum_a009660(void)
416 {
417 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
418 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
419 out_be32(eddrtqcr1, 0x63b20042);
420 #endif
421 }
422
erratum_a008850_early(void)423 static void erratum_a008850_early(void)
424 {
425 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
426 /* part 1 of 2 */
427 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
428 CONFIG_SYS_CCI400_OFFSET);
429 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
430
431 /* Skip if running at lower exception level */
432 if (current_el() < 3)
433 return;
434
435 /* disables propagation of barrier transactions to DDRC from CCI400 */
436 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
437
438 /* disable the re-ordering in DDRC */
439 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
440 #endif
441 }
442
erratum_a008850_post(void)443 void erratum_a008850_post(void)
444 {
445 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
446 /* part 2 of 2 */
447 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
448 CONFIG_SYS_CCI400_OFFSET);
449 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
450 u32 tmp;
451
452 /* Skip if running at lower exception level */
453 if (current_el() < 3)
454 return;
455
456 /* enable propagation of barrier transactions to DDRC from CCI400 */
457 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
458
459 /* enable the re-ordering in DDRC */
460 tmp = ddr_in32(&ddr->eor);
461 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
462 ddr_out32(&ddr->eor, tmp);
463 #endif
464 }
465
466 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315(void)467 void erratum_a010315(void)
468 {
469 int i;
470
471 for (i = PCIE1; i <= PCIE4; i++)
472 if (!is_serdes_configured(i)) {
473 debug("PCIe%d: disabled all R/W permission!\n", i);
474 set_pcie_ns_access(i, 0);
475 }
476 }
477 #endif
478
erratum_a010539(void)479 static void erratum_a010539(void)
480 {
481 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
482 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
483 u32 porsr1;
484
485 porsr1 = in_be32(&gur->porsr1);
486 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
487 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
488 porsr1);
489 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
490 #endif
491 }
492
493 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)494 int get_core_volt_from_fuse(void)
495 {
496 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
497 int vdd;
498 u32 fusesr;
499 u8 vid;
500
501 fusesr = in_be32(&gur->dcfg_fusesr);
502 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
503 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
504 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
505 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
506 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
507 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
508 }
509 debug("%s: VID = 0x%x\n", __func__, vid);
510 switch (vid) {
511 case 0x00: /* VID isn't supported */
512 vdd = -EINVAL;
513 debug("%s: The VID feature is not supported\n", __func__);
514 break;
515 case 0x08: /* 0.9V silicon */
516 vdd = 900;
517 break;
518 case 0x10: /* 1.0V silicon */
519 vdd = 1000;
520 break;
521 default: /* Other core voltage */
522 vdd = -EINVAL;
523 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
524 break;
525 }
526 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
527
528 return vdd;
529 }
530
board_switch_core_volt(u32 vdd)531 __weak int board_switch_core_volt(u32 vdd)
532 {
533 return 0;
534 }
535
setup_core_volt(u32 vdd)536 static int setup_core_volt(u32 vdd)
537 {
538 return board_setup_core_volt(vdd);
539 }
540
541 #ifdef CONFIG_SYS_FSL_DDR
ddr_enable_0v9_volt(bool en)542 static void ddr_enable_0v9_volt(bool en)
543 {
544 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
545 u32 tmp;
546
547 tmp = ddr_in32(&ddr->ddr_cdr1);
548
549 if (en)
550 tmp |= DDR_CDR1_V0PT9_EN;
551 else
552 tmp &= ~DDR_CDR1_V0PT9_EN;
553
554 ddr_out32(&ddr->ddr_cdr1, tmp);
555 }
556 #endif
557
setup_chip_volt(void)558 int setup_chip_volt(void)
559 {
560 int vdd;
561
562 vdd = get_core_volt_from_fuse();
563 /* Nothing to do for silicons doesn't support VID */
564 if (vdd < 0)
565 return vdd;
566
567 if (setup_core_volt(vdd))
568 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
569 #ifdef CONFIG_SYS_HAS_SERDES
570 if (setup_serdes_volt(vdd))
571 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
572 #endif
573
574 #ifdef CONFIG_SYS_FSL_DDR
575 if (vdd == 900)
576 ddr_enable_0v9_volt(true);
577 #endif
578
579 return 0;
580 }
581
582 #ifdef CONFIG_FSL_PFE
init_pfe_scfg_dcfg_regs(void)583 void init_pfe_scfg_dcfg_regs(void)
584 {
585 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
586 u32 ecccr2;
587
588 out_be32(&scfg->pfeasbcr,
589 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
590 out_be32(&scfg->pfebsbcr,
591 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
592
593 /* CCI-400 QoS settings for PFE */
594 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
595 | SCFG_WR_QOS1_PFE2_QOS));
596 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
597 | SCFG_RD_QOS1_PFE2_QOS));
598
599 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
600 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
601 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
602 }
603 #endif
604
fsl_lsch2_early_init_f(void)605 void fsl_lsch2_early_init_f(void)
606 {
607 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
608 CONFIG_SYS_CCI400_OFFSET);
609 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
610 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
611 enum boot_src src;
612 #endif
613
614 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
615 enable_layerscape_ns_access();
616 #endif
617
618 #ifdef CONFIG_FSL_IFC
619 init_early_memctl_regs(); /* tighten IFC timing */
620 #endif
621
622 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
623 src = get_boot_src();
624 if (src != BOOT_SOURCE_QSPI_NOR)
625 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
626 #else
627 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
628 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
629 #endif
630 #endif
631 /* Make SEC reads and writes snoopable */
632 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
633 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
634 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
635 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
636 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
637 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
638 SCFG_SNPCNFGCR_SATAWRSNP);
639 #else
640 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
641 SCFG_SNPCNFGCR_SECWRSNP |
642 SCFG_SNPCNFGCR_SATARDSNP |
643 SCFG_SNPCNFGCR_SATAWRSNP);
644 #endif
645
646 /*
647 * Enable snoop requests and DVM message requests for
648 * Slave insterface S4 (A53 core cluster)
649 */
650 if (current_el() == 3) {
651 out_le32(&cci->slave[4].snoop_ctrl,
652 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
653 }
654
655 /*
656 * Program Central Security Unit (CSU) to grant access
657 * permission for USB 2.0 controller
658 */
659 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
660 if (current_el() == 3)
661 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
662 #endif
663 /* Erratum */
664 erratum_a008850_early(); /* part 1 of 2 */
665 erratum_a009929();
666 erratum_a009660();
667 erratum_a010539();
668 erratum_a009008();
669 erratum_a009798();
670 erratum_a008997();
671 erratum_a009007();
672
673 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
674 set_icids();
675 #endif
676 }
677 #endif
678
679 #ifdef CONFIG_QSPI_AHB_INIT
680 /* Enable 4bytes address support and fast read */
qspi_ahb_init(void)681 int qspi_ahb_init(void)
682 {
683 u32 *qspi_lut, lut_key, *qspi_key;
684
685 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
686 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
687
688 lut_key = in_be32(qspi_key);
689
690 if (lut_key == 0x5af05af0) {
691 /* That means the register is BE */
692 out_be32(qspi_key, 0x5af05af0);
693 /* Unlock the lut table */
694 out_be32(qspi_key + 1, 0x00000002);
695 out_be32(qspi_lut, 0x0820040c);
696 out_be32(qspi_lut + 1, 0x1c080c08);
697 out_be32(qspi_lut + 2, 0x00002400);
698 /* Lock the lut table */
699 out_be32(qspi_key, 0x5af05af0);
700 out_be32(qspi_key + 1, 0x00000001);
701 } else {
702 /* That means the register is LE */
703 out_le32(qspi_key, 0x5af05af0);
704 /* Unlock the lut table */
705 out_le32(qspi_key + 1, 0x00000002);
706 out_le32(qspi_lut, 0x0820040c);
707 out_le32(qspi_lut + 1, 0x1c080c08);
708 out_le32(qspi_lut + 2, 0x00002400);
709 /* Lock the lut table */
710 out_le32(qspi_key, 0x5af05af0);
711 out_le32(qspi_key + 1, 0x00000001);
712 }
713
714 return 0;
715 }
716 #endif
717
718 #ifdef CONFIG_TFABOOT
719 #define MAX_BOOTCMD_SIZE 512
720
fsl_setenv_bootcmd(void)721 int fsl_setenv_bootcmd(void)
722 {
723 int ret;
724 enum boot_src src = get_boot_src();
725 char bootcmd_str[MAX_BOOTCMD_SIZE];
726
727 switch (src) {
728 #ifdef IFC_NOR_BOOTCOMMAND
729 case BOOT_SOURCE_IFC_NOR:
730 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
731 break;
732 #endif
733 #ifdef QSPI_NOR_BOOTCOMMAND
734 case BOOT_SOURCE_QSPI_NOR:
735 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
736 break;
737 #endif
738 #ifdef XSPI_NOR_BOOTCOMMAND
739 case BOOT_SOURCE_XSPI_NOR:
740 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
741 break;
742 #endif
743 #ifdef IFC_NAND_BOOTCOMMAND
744 case BOOT_SOURCE_IFC_NAND:
745 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
746 break;
747 #endif
748 #ifdef QSPI_NAND_BOOTCOMMAND
749 case BOOT_SOURCE_QSPI_NAND:
750 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
751 break;
752 #endif
753 #ifdef XSPI_NAND_BOOTCOMMAND
754 case BOOT_SOURCE_XSPI_NAND:
755 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
756 break;
757 #endif
758 #ifdef SD_BOOTCOMMAND
759 case BOOT_SOURCE_SD_MMC:
760 sprintf(bootcmd_str, SD_BOOTCOMMAND);
761 break;
762 #endif
763 #ifdef SD2_BOOTCOMMAND
764 case BOOT_SOURCE_SD_MMC2:
765 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
766 break;
767 #endif
768 default:
769 #ifdef QSPI_NOR_BOOTCOMMAND
770 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
771 #endif
772 break;
773 }
774
775 ret = env_set("bootcmd", bootcmd_str);
776 if (ret) {
777 printf("Failed to set bootcmd: ret = %d\n", ret);
778 return ret;
779 }
780 return 0;
781 }
782
fsl_setenv_mcinitcmd(void)783 int fsl_setenv_mcinitcmd(void)
784 {
785 int ret = 0;
786 enum boot_src src = get_boot_src();
787
788 switch (src) {
789 #ifdef IFC_MC_INIT_CMD
790 case BOOT_SOURCE_IFC_NAND:
791 case BOOT_SOURCE_IFC_NOR:
792 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
793 break;
794 #endif
795 #ifdef QSPI_MC_INIT_CMD
796 case BOOT_SOURCE_QSPI_NAND:
797 case BOOT_SOURCE_QSPI_NOR:
798 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
799 break;
800 #endif
801 #ifdef XSPI_MC_INIT_CMD
802 case BOOT_SOURCE_XSPI_NAND:
803 case BOOT_SOURCE_XSPI_NOR:
804 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
805 break;
806 #endif
807 #ifdef SD_MC_INIT_CMD
808 case BOOT_SOURCE_SD_MMC:
809 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
810 break;
811 #endif
812 #ifdef SD2_MC_INIT_CMD
813 case BOOT_SOURCE_SD_MMC2:
814 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
815 break;
816 #endif
817 default:
818 #ifdef QSPI_MC_INIT_CMD
819 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
820 #endif
821 break;
822 }
823
824 if (ret) {
825 printf("Failed to set mcinitcmd: ret = %d\n", ret);
826 return ret;
827 }
828 return 0;
829 }
830 #endif
831
832 #ifdef CONFIG_BOARD_LATE_INIT
fsl_board_late_init(void)833 __weak int fsl_board_late_init(void)
834 {
835 return 0;
836 }
837
board_late_init(void)838 int board_late_init(void)
839 {
840 #ifdef CONFIG_CHAIN_OF_TRUST
841 fsl_setenv_chain_of_trust();
842 #endif
843 #ifdef CONFIG_TFABOOT
844 /*
845 * check if gd->env_addr is default_environment; then setenv bootcmd
846 * and mcinitcmd.
847 */
848 #ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
849 if (gd->env_addr == (ulong)&default_environment[0]) {
850 #else
851 if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
852 #endif
853 fsl_setenv_bootcmd();
854 fsl_setenv_mcinitcmd();
855 }
856
857 /*
858 * If the boot mode is secure, default environment is not present then
859 * setenv command needs to be run by default
860 */
861 #ifdef CONFIG_CHAIN_OF_TRUST
862 if ((fsl_check_boot_mode_secure() == 1)) {
863 fsl_setenv_bootcmd();
864 fsl_setenv_mcinitcmd();
865 }
866 #endif
867 #endif
868 #ifdef CONFIG_QSPI_AHB_INIT
869 qspi_ahb_init();
870 #endif
871
872 return fsl_board_late_init();
873 }
874 #endif
875