1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi6220 SoC 4 * 5 * Copyright (C) 2015, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/hisi,hi6220-resets.h> 10#include <dt-bindings/clock/hi6220-clock.h> 11#include <dt-bindings/pinctrl/hisi.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "hisilicon,hi6220"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 core2 { 38 cpu = <&cpu2>; 39 }; 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 cluster1 { 45 core0 { 46 cpu = <&cpu4>; 47 }; 48 core1 { 49 cpu = <&cpu5>; 50 }; 51 core2 { 52 cpu = <&cpu6>; 53 }; 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 }; 59 60 idle-states { 61 entry-method = "psci"; 62 63 CPU_SLEEP: cpu-sleep { 64 compatible = "arm,idle-state"; 65 local-timer-stop; 66 arm,psci-suspend-param = <0x0010000>; 67 entry-latency-us = <700>; 68 exit-latency-us = <250>; 69 min-residency-us = <1000>; 70 }; 71 72 CLUSTER_SLEEP: cluster-sleep { 73 compatible = "arm,idle-state"; 74 local-timer-stop; 75 arm,psci-suspend-param = <0x1010000>; 76 entry-latency-us = <1000>; 77 exit-latency-us = <700>; 78 min-residency-us = <2700>; 79 wakeup-latency-us = <1500>; 80 }; 81 }; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a53", "arm,armv8"; 85 device_type = "cpu"; 86 reg = <0x0 0x0>; 87 enable-method = "psci"; 88 next-level-cache = <&CLUSTER0_L2>; 89 clocks = <&stub_clock 0>; 90 operating-points-v2 = <&cpu_opp_table>; 91 cooling-min-level = <4>; 92 cooling-max-level = <0>; 93 #cooling-cells = <2>; /* min followed by max */ 94 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 95 dynamic-power-coefficient = <311>; 96 }; 97 98 cpu1: cpu@1 { 99 compatible = "arm,cortex-a53", "arm,armv8"; 100 device_type = "cpu"; 101 reg = <0x0 0x1>; 102 enable-method = "psci"; 103 next-level-cache = <&CLUSTER0_L2>; 104 operating-points-v2 = <&cpu_opp_table>; 105 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 106 }; 107 108 cpu2: cpu@2 { 109 compatible = "arm,cortex-a53", "arm,armv8"; 110 device_type = "cpu"; 111 reg = <0x0 0x2>; 112 enable-method = "psci"; 113 next-level-cache = <&CLUSTER0_L2>; 114 operating-points-v2 = <&cpu_opp_table>; 115 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 116 }; 117 118 cpu3: cpu@3 { 119 compatible = "arm,cortex-a53", "arm,armv8"; 120 device_type = "cpu"; 121 reg = <0x0 0x3>; 122 enable-method = "psci"; 123 next-level-cache = <&CLUSTER0_L2>; 124 operating-points-v2 = <&cpu_opp_table>; 125 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 126 }; 127 128 cpu4: cpu@100 { 129 compatible = "arm,cortex-a53", "arm,armv8"; 130 device_type = "cpu"; 131 reg = <0x0 0x100>; 132 enable-method = "psci"; 133 next-level-cache = <&CLUSTER1_L2>; 134 operating-points-v2 = <&cpu_opp_table>; 135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 136 }; 137 138 cpu5: cpu@101 { 139 compatible = "arm,cortex-a53", "arm,armv8"; 140 device_type = "cpu"; 141 reg = <0x0 0x101>; 142 enable-method = "psci"; 143 next-level-cache = <&CLUSTER1_L2>; 144 operating-points-v2 = <&cpu_opp_table>; 145 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 146 }; 147 148 cpu6: cpu@102 { 149 compatible = "arm,cortex-a53", "arm,armv8"; 150 device_type = "cpu"; 151 reg = <0x0 0x102>; 152 enable-method = "psci"; 153 next-level-cache = <&CLUSTER1_L2>; 154 operating-points-v2 = <&cpu_opp_table>; 155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 156 }; 157 158 cpu7: cpu@103 { 159 compatible = "arm,cortex-a53", "arm,armv8"; 160 device_type = "cpu"; 161 reg = <0x0 0x103>; 162 enable-method = "psci"; 163 next-level-cache = <&CLUSTER1_L2>; 164 operating-points-v2 = <&cpu_opp_table>; 165 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 166 }; 167 168 CLUSTER0_L2: l2-cache0 { 169 compatible = "cache"; 170 }; 171 172 CLUSTER1_L2: l2-cache1 { 173 compatible = "cache"; 174 }; 175 }; 176 177 cpu_opp_table: cpu_opp_table { 178 compatible = "operating-points-v2"; 179 opp-shared; 180 181 opp00 { 182 opp-hz = /bits/ 64 <208000000>; 183 opp-microvolt = <1040000>; 184 clock-latency-ns = <500000>; 185 }; 186 opp01 { 187 opp-hz = /bits/ 64 <432000000>; 188 opp-microvolt = <1040000>; 189 clock-latency-ns = <500000>; 190 }; 191 opp02 { 192 opp-hz = /bits/ 64 <729000000>; 193 opp-microvolt = <1090000>; 194 clock-latency-ns = <500000>; 195 }; 196 opp03 { 197 opp-hz = /bits/ 64 <960000000>; 198 opp-microvolt = <1180000>; 199 clock-latency-ns = <500000>; 200 }; 201 opp04 { 202 opp-hz = /bits/ 64 <1200000000>; 203 opp-microvolt = <1330000>; 204 clock-latency-ns = <500000>; 205 }; 206 }; 207 208 gic: interrupt-controller@f6801000 { 209 compatible = "arm,gic-400"; 210 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */ 211 <0x0 0xf6802000 0 0x2000>, /* GICC */ 212 <0x0 0xf6804000 0 0x2000>, /* GICH */ 213 <0x0 0xf6806000 0 0x2000>; /* GICV */ 214 #address-cells = <0>; 215 #interrupt-cells = <3>; 216 interrupt-controller; 217 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 218 }; 219 220 timer { 221 compatible = "arm,armv8-timer"; 222 interrupt-parent = <&gic>; 223 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 224 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 225 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 226 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 227 }; 228 229 soc { 230 compatible = "simple-bus"; 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges; 234 235 sram: sram@fff80000 { 236 compatible = "hisilicon,hi6220-sramctrl", "syscon"; 237 reg = <0x0 0xfff80000 0x0 0x12000>; 238 }; 239 240 ao_ctrl: ao_ctrl@f7800000 { 241 compatible = "hisilicon,hi6220-aoctrl", "syscon"; 242 reg = <0x0 0xf7800000 0x0 0x2000>; 243 #clock-cells = <1>; 244 }; 245 246 sys_ctrl: sys_ctrl@f7030000 { 247 compatible = "hisilicon,hi6220-sysctrl", "syscon"; 248 reg = <0x0 0xf7030000 0x0 0x2000>; 249 #clock-cells = <1>; 250 #reset-cells = <1>; 251 }; 252 253 media_ctrl: media_ctrl@f4410000 { 254 compatible = "hisilicon,hi6220-mediactrl", "syscon"; 255 reg = <0x0 0xf4410000 0x0 0x1000>; 256 #clock-cells = <1>; 257 #reset-cells = <1>; 258 }; 259 260 pm_ctrl: pm_ctrl@f7032000 { 261 compatible = "hisilicon,hi6220-pmctrl", "syscon"; 262 reg = <0x0 0xf7032000 0x0 0x1000>; 263 #clock-cells = <1>; 264 }; 265 266 acpu_sctrl: acpu_sctrl@f6504000 { 267 compatible = "hisilicon,hi6220-acpu-sctrl", "syscon"; 268 reg = <0x0 0xf6504000 0x0 0x1000>; 269 #clock-cells = <1>; 270 }; 271 272 medianoc_ade: medianoc_ade@f4520000 { 273 compatible = "syscon"; 274 reg = <0x0 0xf4520000 0x0 0x4000>; 275 }; 276 277 stub_clock: stub_clock { 278 compatible = "hisilicon,hi6220-stub-clk"; 279 hisilicon,hi6220-clk-sram = <&sram>; 280 #clock-cells = <1>; 281 mbox-names = "mbox-tx"; 282 mboxes = <&mailbox 1 0 11>; 283 }; 284 285 uart0: uart@f8015000 { /* console */ 286 compatible = "arm,pl011", "arm,primecell"; 287 reg = <0x0 0xf8015000 0x0 0x1000>; 288 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&ao_ctrl HI6220_UART0_PCLK>, 290 <&ao_ctrl HI6220_UART0_PCLK>; 291 clock-names = "uartclk", "apb_pclk"; 292 }; 293 294 uart1: uart@f7111000 { 295 compatible = "arm,pl011", "arm,primecell"; 296 reg = <0x0 0xf7111000 0x0 0x1000>; 297 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&sys_ctrl HI6220_UART1_PCLK>, 299 <&sys_ctrl HI6220_UART1_PCLK>; 300 clock-names = "uartclk", "apb_pclk"; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>; 303 status = "disabled"; 304 }; 305 306 uart2: uart@f7112000 { 307 compatible = "arm,pl011", "arm,primecell"; 308 reg = <0x0 0xf7112000 0x0 0x1000>; 309 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&sys_ctrl HI6220_UART2_PCLK>, 311 <&sys_ctrl HI6220_UART2_PCLK>; 312 clock-names = "uartclk", "apb_pclk"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 315 status = "disabled"; 316 }; 317 318 uart3: uart@f7113000 { 319 compatible = "arm,pl011", "arm,primecell"; 320 reg = <0x0 0xf7113000 0x0 0x1000>; 321 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&sys_ctrl HI6220_UART3_PCLK>, 323 <&sys_ctrl HI6220_UART3_PCLK>; 324 clock-names = "uartclk", "apb_pclk"; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 327 status = "disabled"; 328 }; 329 330 uart4: uart@f7114000 { 331 compatible = "arm,pl011", "arm,primecell"; 332 reg = <0x0 0xf7114000 0x0 0x1000>; 333 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&sys_ctrl HI6220_UART4_PCLK>, 335 <&sys_ctrl HI6220_UART4_PCLK>; 336 clock-names = "uartclk", "apb_pclk"; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 339 status = "disabled"; 340 }; 341 342 dma0: dma@f7370000 { 343 compatible = "hisilicon,k3-dma-1.0"; 344 reg = <0x0 0xf7370000 0x0 0x1000>; 345 #dma-cells = <1>; 346 dma-channels = <15>; 347 dma-requests = <32>; 348 interrupts = <0 84 4>; 349 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>; 350 dma-no-cci; 351 dma-type = "hi6220_dma"; 352 status = "ok"; 353 }; 354 355 dual_timer0: timer@f8008000 { 356 compatible = "arm,sp804", "arm,primecell"; 357 reg = <0x0 0xf8008000 0x0 0x1000>; 358 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>, 361 <&ao_ctrl HI6220_TIMER0_PCLK>, 362 <&ao_ctrl HI6220_TIMER0_PCLK>; 363 clock-names = "timer1", "timer2", "apb_pclk"; 364 }; 365 366 rtc0: rtc@f8003000 { 367 compatible = "arm,pl031", "arm,primecell"; 368 reg = <0x0 0xf8003000 0x0 0x1000>; 369 interrupts = <0 12 4>; 370 clocks = <&ao_ctrl HI6220_RTC0_PCLK>; 371 clock-names = "apb_pclk"; 372 }; 373 374 rtc1: rtc@f8004000 { 375 compatible = "arm,pl031", "arm,primecell"; 376 reg = <0x0 0xf8004000 0x0 0x1000>; 377 interrupts = <0 8 4>; 378 clocks = <&ao_ctrl HI6220_RTC1_PCLK>; 379 clock-names = "apb_pclk"; 380 }; 381 382 pmx0: pinmux@f7010000 { 383 compatible = "pinctrl-single"; 384 reg = <0x0 0xf7010000 0x0 0x27c>; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 #pinctrl-cells = <1>; 388 #gpio-range-cells = <3>; 389 pinctrl-single,register-width = <32>; 390 pinctrl-single,function-mask = <7>; 391 pinctrl-single,gpio-range = < 392 &range 80 8 MUX_M0 /* gpio 3: [0..7] */ 393 &range 88 8 MUX_M0 /* gpio 4: [0..7] */ 394 &range 96 8 MUX_M0 /* gpio 5: [0..7] */ 395 &range 104 8 MUX_M0 /* gpio 6: [0..7] */ 396 &range 112 8 MUX_M0 /* gpio 7: [0..7] */ 397 &range 120 2 MUX_M0 /* gpio 8: [0..1] */ 398 &range 2 6 MUX_M1 /* gpio 8: [2..7] */ 399 &range 8 8 MUX_M1 /* gpio 9: [0..7] */ 400 &range 0 1 MUX_M1 /* gpio 10: [0] */ 401 &range 16 7 MUX_M1 /* gpio 10: [1..7] */ 402 &range 23 3 MUX_M1 /* gpio 11: [0..2] */ 403 &range 28 5 MUX_M1 /* gpio 11: [3..7] */ 404 &range 33 3 MUX_M1 /* gpio 12: [0..2] */ 405 &range 43 5 MUX_M1 /* gpio 12: [3..7] */ 406 &range 48 8 MUX_M1 /* gpio 13: [0..7] */ 407 &range 56 8 MUX_M1 /* gpio 14: [0..7] */ 408 &range 74 6 MUX_M1 /* gpio 15: [0..5] */ 409 &range 122 1 MUX_M1 /* gpio 15: [6] */ 410 &range 126 1 MUX_M1 /* gpio 15: [7] */ 411 &range 127 8 MUX_M1 /* gpio 16: [0..7] */ 412 &range 135 8 MUX_M1 /* gpio 17: [0..7] */ 413 &range 143 8 MUX_M1 /* gpio 18: [0..7] */ 414 &range 151 8 MUX_M1 /* gpio 19: [0..7] */ 415 >; 416 range: gpio-range { 417 #pinctrl-single,gpio-range-cells = <3>; 418 }; 419 }; 420 421 pmx1: pinmux@f7010800 { 422 compatible = "pinconf-single"; 423 reg = <0x0 0xf7010800 0x0 0x28c>; 424 #address-cells = <1>; 425 #size-cells = <1>; 426 #pinctrl-cells = <1>; 427 pinctrl-single,register-width = <32>; 428 }; 429 430 pmx2: pinmux@f8001800 { 431 compatible = "pinconf-single"; 432 reg = <0x0 0xf8001800 0x0 0x78>; 433 #address-cells = <1>; 434 #size-cells = <1>; 435 #pinctrl-cells = <1>; 436 pinctrl-single,register-width = <32>; 437 }; 438 439 gpio0: gpio@f8011000 { 440 compatible = "arm,pl061", "arm,primecell"; 441 reg = <0x0 0xf8011000 0x0 0x1000>; 442 interrupts = <0 52 0x4>; 443 gpio-controller; 444 #gpio-cells = <2>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 clocks = <&ao_ctrl 2>; 448 clock-names = "apb_pclk"; 449 }; 450 451 gpio1: gpio@f8012000 { 452 compatible = "arm,pl061", "arm,primecell"; 453 reg = <0x0 0xf8012000 0x0 0x1000>; 454 interrupts = <0 53 0x4>; 455 gpio-controller; 456 #gpio-cells = <2>; 457 interrupt-controller; 458 #interrupt-cells = <2>; 459 clocks = <&ao_ctrl 2>; 460 clock-names = "apb_pclk"; 461 }; 462 463 gpio2: gpio@f8013000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0x0 0xf8013000 0x0 0x1000>; 466 interrupts = <0 54 0x4>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 clocks = <&ao_ctrl 2>; 472 clock-names = "apb_pclk"; 473 }; 474 475 gpio3: gpio@f8014000 { 476 compatible = "arm,pl061", "arm,primecell"; 477 reg = <0x0 0xf8014000 0x0 0x1000>; 478 interrupts = <0 55 0x4>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 gpio-ranges = <&pmx0 0 80 8>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 clocks = <&ao_ctrl 2>; 485 clock-names = "apb_pclk"; 486 }; 487 488 gpio4: gpio@f7020000 { 489 compatible = "arm,pl061", "arm,primecell"; 490 reg = <0x0 0xf7020000 0x0 0x1000>; 491 interrupts = <0 56 0x4>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 gpio-ranges = <&pmx0 0 88 8>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 clocks = <&ao_ctrl 2>; 498 clock-names = "apb_pclk"; 499 }; 500 501 gpio5: gpio@f7021000 { 502 compatible = "arm,pl061", "arm,primecell"; 503 reg = <0x0 0xf7021000 0x0 0x1000>; 504 interrupts = <0 57 0x4>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 gpio-ranges = <&pmx0 0 96 8>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 clocks = <&ao_ctrl 2>; 511 clock-names = "apb_pclk"; 512 }; 513 514 gpio6: gpio@f7022000 { 515 compatible = "arm,pl061", "arm,primecell"; 516 reg = <0x0 0xf7022000 0x0 0x1000>; 517 interrupts = <0 58 0x4>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 gpio-ranges = <&pmx0 0 104 8>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 clocks = <&ao_ctrl 2>; 524 clock-names = "apb_pclk"; 525 }; 526 527 gpio7: gpio@f7023000 { 528 compatible = "arm,pl061", "arm,primecell"; 529 reg = <0x0 0xf7023000 0x0 0x1000>; 530 interrupts = <0 59 0x4>; 531 gpio-controller; 532 #gpio-cells = <2>; 533 gpio-ranges = <&pmx0 0 112 8>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 clocks = <&ao_ctrl 2>; 537 clock-names = "apb_pclk"; 538 }; 539 540 gpio8: gpio@f7024000 { 541 compatible = "arm,pl061", "arm,primecell"; 542 reg = <0x0 0xf7024000 0x0 0x1000>; 543 interrupts = <0 60 0x4>; 544 gpio-controller; 545 #gpio-cells = <2>; 546 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>; 547 interrupt-controller; 548 #interrupt-cells = <2>; 549 clocks = <&ao_ctrl 2>; 550 clock-names = "apb_pclk"; 551 }; 552 553 gpio9: gpio@f7025000 { 554 compatible = "arm,pl061", "arm,primecell"; 555 reg = <0x0 0xf7025000 0x0 0x1000>; 556 interrupts = <0 61 0x4>; 557 gpio-controller; 558 #gpio-cells = <2>; 559 gpio-ranges = <&pmx0 0 8 8>; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 clocks = <&ao_ctrl 2>; 563 clock-names = "apb_pclk"; 564 }; 565 566 gpio10: gpio@f7026000 { 567 compatible = "arm,pl061", "arm,primecell"; 568 reg = <0x0 0xf7026000 0x0 0x1000>; 569 interrupts = <0 62 0x4>; 570 gpio-controller; 571 #gpio-cells = <2>; 572 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>; 573 interrupt-controller; 574 #interrupt-cells = <2>; 575 clocks = <&ao_ctrl 2>; 576 clock-names = "apb_pclk"; 577 }; 578 579 gpio11: gpio@f7027000 { 580 compatible = "arm,pl061", "arm,primecell"; 581 reg = <0x0 0xf7027000 0x0 0x1000>; 582 interrupts = <0 63 0x4>; 583 gpio-controller; 584 #gpio-cells = <2>; 585 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 clocks = <&ao_ctrl 2>; 589 clock-names = "apb_pclk"; 590 }; 591 592 gpio12: gpio@f7028000 { 593 compatible = "arm,pl061", "arm,primecell"; 594 reg = <0x0 0xf7028000 0x0 0x1000>; 595 interrupts = <0 64 0x4>; 596 gpio-controller; 597 #gpio-cells = <2>; 598 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 clocks = <&ao_ctrl 2>; 602 clock-names = "apb_pclk"; 603 }; 604 605 gpio13: gpio@f7029000 { 606 compatible = "arm,pl061", "arm,primecell"; 607 reg = <0x0 0xf7029000 0x0 0x1000>; 608 interrupts = <0 65 0x4>; 609 gpio-controller; 610 #gpio-cells = <2>; 611 gpio-ranges = <&pmx0 0 48 8>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 clocks = <&ao_ctrl 2>; 615 clock-names = "apb_pclk"; 616 }; 617 618 gpio14: gpio@f702a000 { 619 compatible = "arm,pl061", "arm,primecell"; 620 reg = <0x0 0xf702a000 0x0 0x1000>; 621 interrupts = <0 66 0x4>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 gpio-ranges = <&pmx0 0 56 8>; 625 interrupt-controller; 626 #interrupt-cells = <2>; 627 clocks = <&ao_ctrl 2>; 628 clock-names = "apb_pclk"; 629 }; 630 631 gpio15: gpio@f702b000 { 632 compatible = "arm,pl061", "arm,primecell"; 633 reg = <0x0 0xf702b000 0x0 0x1000>; 634 interrupts = <0 67 0x4>; 635 gpio-controller; 636 #gpio-cells = <2>; 637 gpio-ranges = < 638 &pmx0 0 74 6 639 &pmx0 6 122 1 640 &pmx0 7 126 1 641 >; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 clocks = <&ao_ctrl 2>; 645 clock-names = "apb_pclk"; 646 }; 647 648 gpio16: gpio@f702c000 { 649 compatible = "arm,pl061", "arm,primecell"; 650 reg = <0x0 0xf702c000 0x0 0x1000>; 651 interrupts = <0 68 0x4>; 652 gpio-controller; 653 #gpio-cells = <2>; 654 gpio-ranges = <&pmx0 0 127 8>; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 clocks = <&ao_ctrl 2>; 658 clock-names = "apb_pclk"; 659 }; 660 661 gpio17: gpio@f702d000 { 662 compatible = "arm,pl061", "arm,primecell"; 663 reg = <0x0 0xf702d000 0x0 0x1000>; 664 interrupts = <0 69 0x4>; 665 gpio-controller; 666 #gpio-cells = <2>; 667 gpio-ranges = <&pmx0 0 135 8>; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 clocks = <&ao_ctrl 2>; 671 clock-names = "apb_pclk"; 672 }; 673 674 gpio18: gpio@f702e000 { 675 compatible = "arm,pl061", "arm,primecell"; 676 reg = <0x0 0xf702e000 0x0 0x1000>; 677 interrupts = <0 70 0x4>; 678 gpio-controller; 679 #gpio-cells = <2>; 680 gpio-ranges = <&pmx0 0 143 8>; 681 interrupt-controller; 682 #interrupt-cells = <2>; 683 clocks = <&ao_ctrl 2>; 684 clock-names = "apb_pclk"; 685 }; 686 687 gpio19: gpio@f702f000 { 688 compatible = "arm,pl061", "arm,primecell"; 689 reg = <0x0 0xf702f000 0x0 0x1000>; 690 interrupts = <0 71 0x4>; 691 gpio-controller; 692 #gpio-cells = <2>; 693 gpio-ranges = <&pmx0 0 151 8>; 694 interrupt-controller; 695 #interrupt-cells = <2>; 696 clocks = <&ao_ctrl 2>; 697 clock-names = "apb_pclk"; 698 }; 699 700 spi0: spi@f7106000 { 701 compatible = "arm,pl022", "arm,primecell"; 702 reg = <0x0 0xf7106000 0x0 0x1000>; 703 interrupts = <0 50 4>; 704 bus-id = <0>; 705 enable-dma = <0>; 706 clocks = <&sys_ctrl HI6220_SPI_CLK>; 707 clock-names = "apb_pclk"; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; 710 num-cs = <1>; 711 cs-gpios = <&gpio6 2 0>; 712 status = "disabled"; 713 }; 714 715 i2c0: i2c@f7100000 { 716 compatible = "snps,designware-i2c"; 717 reg = <0x0 0xf7100000 0x0 0x1000>; 718 interrupts = <0 44 4>; 719 clocks = <&sys_ctrl HI6220_I2C0_CLK>; 720 i2c-sda-hold-time-ns = <300>; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 723 status = "disabled"; 724 }; 725 726 i2c1: i2c@f7101000 { 727 compatible = "snps,designware-i2c"; 728 reg = <0x0 0xf7101000 0x0 0x1000>; 729 clocks = <&sys_ctrl HI6220_I2C1_CLK>; 730 interrupts = <0 45 4>; 731 i2c-sda-hold-time-ns = <300>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 734 status = "disabled"; 735 }; 736 737 i2c2: i2c@f7102000 { 738 compatible = "snps,designware-i2c"; 739 reg = <0x0 0xf7102000 0x0 0x1000>; 740 clocks = <&sys_ctrl HI6220_I2C2_CLK>; 741 interrupts = <0 46 4>; 742 i2c-sda-hold-time-ns = <300>; 743 pinctrl-names = "default"; 744 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>; 745 status = "disabled"; 746 }; 747 748 usb_phy: usbphy { 749 compatible = "hisilicon,hi6220-usb-phy"; 750 #phy-cells = <0>; 751 phy-supply = <®_5v_hub>; 752 hisilicon,peripheral-syscon = <&sys_ctrl>; 753 }; 754 755 usb: usb@f72c0000 { 756 compatible = "hisilicon,hi6220-usb"; 757 reg = <0x0 0xf72c0000 0x0 0x40000>; 758 phys = <&usb_phy>; 759 phy-names = "usb2-phy"; 760 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>; 761 clock-names = "otg"; 762 dr_mode = "otg"; 763 g-rx-fifo-size = <512>; 764 g-np-tx-fifo-size = <128>; 765 g-tx-fifo-size = <128 128 128 128 128 128 128 128 766 16 16 16 16 16 16 16>; 767 interrupts = <0 77 0x4>; 768 }; 769 770 mailbox: mailbox@f7510000 { 771 compatible = "hisilicon,hi6220-mbox"; 772 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */ 773 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */ 774 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 775 #mbox-cells = <3>; 776 }; 777 778 dwmmc_0: dwmmc0@f723d000 { 779 compatible = "hisilicon,hi6220-dw-mshc"; 780 reg = <0x0 0xf723d000 0x0 0x1000>; 781 interrupts = <0x0 0x48 0x4>; 782 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>; 783 clock-names = "ciu", "biu"; 784 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>; 785 reset-names = "reset"; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func 788 &emmc_cfg_func &emmc_rst_cfg_func>; 789 }; 790 791 dwmmc_1: dwmmc1@f723e000 { 792 compatible = "hisilicon,hi6220-dw-mshc"; 793 hisilicon,peripheral-syscon = <&ao_ctrl>; 794 reg = <0x0 0xf723e000 0x0 0x1000>; 795 interrupts = <0x0 0x49 0x4>; 796 #address-cells = <0x1>; 797 #size-cells = <0x0>; 798 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>; 799 clock-names = "ciu", "biu"; 800 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>; 801 reset-names = "reset"; 802 pinctrl-names = "default", "idle"; 803 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>; 804 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>; 805 }; 806 807 dwmmc_2: dwmmc2@f723f000 { 808 compatible = "hisilicon,hi6220-dw-mshc"; 809 reg = <0x0 0xf723f000 0x0 0x1000>; 810 interrupts = <0x0 0x4a 0x4>; 811 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>; 812 clock-names = "ciu", "biu"; 813 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>; 814 reset-names = "reset"; 815 pinctrl-names = "default", "idle"; 816 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>; 817 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>; 818 }; 819 820 tsensor: tsensor@0,f7030700 { 821 compatible = "hisilicon,tsensor"; 822 reg = <0x0 0xf7030700 0x0 0x1000>; 823 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&sys_ctrl 22>; 825 clock-names = "thermal_clk"; 826 #thermal-sensor-cells = <1>; 827 }; 828 829 i2s0: i2s@f7118000{ 830 compatible = "hisilicon,hi6210-i2s"; 831 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ 832 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ 833 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>, 834 <&sys_ctrl HI6220_BBPPLL0_DIV>; 835 clock-names = "dacodec", "i2s-base"; 836 dmas = <&dma0 15 &dma0 14>; 837 dma-names = "rx", "tx"; 838 hisilicon,sysctrl-syscon = <&sys_ctrl>; 839 #sound-dai-cells = <1>; 840 }; 841 842 thermal-zones { 843 844 cls0: cls0 { 845 polling-delay = <1000>; 846 polling-delay-passive = <100>; 847 sustainable-power = <3326>; 848 849 /* sensor ID */ 850 thermal-sensors = <&tsensor 2>; 851 852 trips { 853 threshold: trip-point@0 { 854 temperature = <65000>; 855 hysteresis = <0>; 856 type = "passive"; 857 }; 858 859 target: trip-point@1 { 860 temperature = <75000>; 861 hysteresis = <0>; 862 type = "passive"; 863 }; 864 }; 865 866 cooling-maps { 867 map0 { 868 trip = <&target>; 869 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 870 }; 871 }; 872 }; 873 }; 874 875 ade: ade@f4100000 { 876 compatible = "hisilicon,hi6220-ade"; 877 reg = <0x0 0xf4100000 0x0 0x7800>; 878 reg-names = "ade_base"; 879 hisilicon,noc-syscon = <&medianoc_ade>; 880 resets = <&media_ctrl MEDIA_ADE>; 881 interrupts = <0 115 4>; /* ldi interrupt */ 882 883 clocks = <&media_ctrl HI6220_ADE_CORE>, 884 <&media_ctrl HI6220_CODEC_JPEG>, 885 <&media_ctrl HI6220_ADE_PIX_SRC>; 886 /*clock name*/ 887 clock-names = "clk_ade_core", 888 "clk_codec_jpeg", 889 "clk_ade_pix"; 890 891 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, 892 <&media_ctrl HI6220_CODEC_JPEG>; 893 assigned-clock-rates = <360000000>, <288000000>; 894 dma-coherent; 895 status = "disabled"; 896 897 port { 898 ade_out: endpoint { 899 remote-endpoint = <&dsi_in>; 900 }; 901 }; 902 }; 903 904 dsi: dsi@f4107800 { 905 compatible = "hisilicon,hi6220-dsi"; 906 reg = <0x0 0xf4107800 0x0 0x100>; 907 clocks = <&media_ctrl HI6220_DSI_PCLK>; 908 clock-names = "pclk"; 909 status = "disabled"; 910 911 ports { 912 #address-cells = <1>; 913 #size-cells = <0>; 914 915 /* 0 for input port */ 916 port@0 { 917 reg = <0>; 918 dsi_in: endpoint { 919 remote-endpoint = <&ade_out>; 920 }; 921 }; 922 }; 923 }; 924 925 debug@f6590000 { 926 compatible = "arm,coresight-cpu-debug","arm,primecell"; 927 reg = <0 0xf6590000 0 0x1000>; 928 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 929 clock-names = "apb_pclk"; 930 cpu = <&cpu0>; 931 }; 932 933 debug@f6592000 { 934 compatible = "arm,coresight-cpu-debug","arm,primecell"; 935 reg = <0 0xf6592000 0 0x1000>; 936 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 937 clock-names = "apb_pclk"; 938 cpu = <&cpu1>; 939 }; 940 941 debug@f6594000 { 942 compatible = "arm,coresight-cpu-debug","arm,primecell"; 943 reg = <0 0xf6594000 0 0x1000>; 944 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 945 clock-names = "apb_pclk"; 946 cpu = <&cpu2>; 947 }; 948 949 debug@f6596000 { 950 compatible = "arm,coresight-cpu-debug","arm,primecell"; 951 reg = <0 0xf6596000 0 0x1000>; 952 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 953 clock-names = "apb_pclk"; 954 cpu = <&cpu3>; 955 }; 956 957 debug@f65d0000 { 958 compatible = "arm,coresight-cpu-debug","arm,primecell"; 959 reg = <0 0xf65d0000 0 0x1000>; 960 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 961 clock-names = "apb_pclk"; 962 cpu = <&cpu4>; 963 }; 964 965 debug@f65d2000 { 966 compatible = "arm,coresight-cpu-debug","arm,primecell"; 967 reg = <0 0xf65d2000 0 0x1000>; 968 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 969 clock-names = "apb_pclk"; 970 cpu = <&cpu5>; 971 }; 972 973 debug@f65d4000 { 974 compatible = "arm,coresight-cpu-debug","arm,primecell"; 975 reg = <0 0xf65d4000 0 0x1000>; 976 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 977 clock-names = "apb_pclk"; 978 cpu = <&cpu6>; 979 }; 980 981 debug@f65d6000 { 982 compatible = "arm,coresight-cpu-debug","arm,primecell"; 983 reg = <0 0xf65d6000 0 0x1000>; 984 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 985 clock-names = "apb_pclk"; 986 cpu = <&cpu7>; 987 }; 988 }; 989}; 990 991#include "hi6220-coresight.dtsi" 992